[llvm] r329931 - [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 12 11:00:15 PDT 2018
Author: lei
Date: Thu Apr 12 11:00:14 2018
New Revision: 329931
URL: http://llvm.org/viewvc/llvm-project?rev=329931&view=rev
Log:
[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Legalize and emit code for:
* xscvsdqp
* xscvudqp
Differential Revision: https://reviews.llvm.org/D45230
Added:
llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=329931&r1=329930&r2=329931&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 12 11:00:14 2018
@@ -9409,7 +9409,12 @@ SDValue PPCTargetLowering::LowerOperatio
case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
SDLoc(Op));
case ISD::UINT_TO_FP:
- case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
+ case ISD::SINT_TO_FP:
+ // Conversions to f128 are legal.
+ if (EnableQuadPrecision && (Op->getValueType(0) == MVT::f128))
+ return Op;
+ return LowerINT_TO_FP(Op, DAG);
+
case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
// Lower 64-bit shifts.
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=329931&r1=329930&r2=329931&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Thu Apr 12 11:00:14 2018
@@ -2512,7 +2512,12 @@ let AddedComplexity = 400, Predicates =
// Convert (Un)Signed DWord -> QP
def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>;
+ def : Pat<(f128 (sint_to_fp i64:$src)),
+ (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
+
def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>;
+ def : Pat<(f128 (uint_to_fp i64:$src)),
+ (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
let UseVSXReg = 1 in {
//===--------------------------------------------------------------------===//
@@ -3117,6 +3122,17 @@ let AddedComplexity = 400, Predicates =
(COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>;
def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
(f32 (DFLOADf32 ixaddr:$src))>;
+
+ // Convert (Un)Signed DWord in memory -> QP
+ def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))),
+ (f128 (XSCVSDQP (LXSDX xaddr:$src)))>;
+ def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))),
+ (f128 (XSCVSDQP (LXSD ixaddr:$src)))>;
+ def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))),
+ (f128 (XSCVUDQP (LXSDX xaddr:$src)))>;
+ def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))),
+ (f128 (XSCVUDQP (LXSD ixaddr:$src)))>;
+
} // end HasP9Vector, AddedComplexity
let Predicates = [HasP9Vector] in {
Added: llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll?rev=329931&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-conv.ll Thu Apr 12 11:00:14 2018
@@ -0,0 +1,140 @@
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+ at mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
+ at umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
+ at swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
+
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp(fp128* nocapture %a, i64 %b) {
+entry:
+ %conv = sitofp i64 %b to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: sdwConv2qp
+; CHECK: mtvsrd [[REG:[0-9]+]], 4
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp_02(fp128* nocapture %a) {
+entry:
+ %0 = load i64, i64* getelementptr inbounds
+ ([5 x i64], [5 x i64]* @mem, i64 0, i64 2), align 8
+ %conv = sitofp i64 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: sdwConv2qp_02
+; CHECK: addis [[REG:[0-9]+]], 2, .LC0 at toc@ha
+; CHECK: ld [[REG]], .LC0 at toc@l([[REG]])
+; CHECK: lxsd [[REG0:[0-9]+]], 16([[REG]])
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp_03(fp128* nocapture %a, i64* nocapture readonly %b) {
+entry:
+ %0 = load i64, i64* %b, align 8
+ %conv = sitofp i64 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: sdwConv2qp_03
+; CHECK-NOT: ld
+; CHECK: lxsd [[REG0:[0-9]+]], 0(4)
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG0]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwConv2qp(fp128* nocapture %a, i64 %b) {
+entry:
+ %conv = uitofp i64 %b to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: udwConv2qp
+; CHECK: mtvsrd [[REG:[0-9]+]], 4
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwConv2qp_02(fp128* nocapture %a) {
+entry:
+ %0 = load i64, i64* getelementptr inbounds
+ ([5 x i64], [5 x i64]* @umem, i64 0, i64 4), align 8
+ %conv = uitofp i64 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: udwConv2qp_02
+; CHECK: addis [[REG:[0-9]+]], 2, .LC1 at toc@ha
+; CHECK: ld [[REG]], .LC1 at toc@l([[REG]])
+; CHECK: lxsd [[REG0:[0-9]+]], 32([[REG]])
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG0]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwConv2qp_03(fp128* nocapture %a, i64* nocapture readonly %b) {
+entry:
+ %0 = load i64, i64* %b, align 8
+ %conv = uitofp i64 %0 to fp128
+ store fp128 %conv, fp128* %a, align 16
+ ret void
+
+; CHECK-LABEL: udwConv2qp_03
+; CHECK-NOT: ld
+; CHECK: lxsd [[REG:[0-9]+]], 0(4)
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp_testXForm(fp128* nocapture %sink,
+ i8* nocapture readonly %a) {
+entry:
+ %add.ptr = getelementptr inbounds i8, i8* %a, i64 3
+ %0 = bitcast i8* %add.ptr to i64*
+ %1 = load i64, i64* %0, align 8
+ %conv = sitofp i64 %1 to fp128
+ store fp128 %conv, fp128* %sink, align 16
+ ret void
+
+; CHECK-LABEL: sdwConv2qp_testXForm
+; CHECK: addi [[REG:[0-9]+]], 4, 3
+; CHECK-NEXT: lxsd [[REG1:[0-9]+]], 0([[REG]])
+; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG1]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @udwConv2qp_testXForm(fp128* nocapture %sink,
+ i8* nocapture readonly %a) {
+entry:
+ %add.ptr = getelementptr inbounds i8, i8* %a, i64 3
+ %0 = bitcast i8* %add.ptr to i64*
+ %1 = load i64, i64* %0, align 8
+ %conv = uitofp i64 %1 to fp128
+ store fp128 %conv, fp128* %sink, align 16
+ ret void
+
+; CHECK-LABEL: udwConv2qp_testXForm
+; CHECK: addi [[REG:[0-9]+]], 4, 3
+; CHECK-NEXT: lxsd [[REG1:[0-9]+]], 0([[REG]])
+; CHECK-NEXT: xscvudqp [[CONV:[0-9]+]], [[REG1]]
+; CHECK-NEXT: stxv [[CONV]], 0(3)
+; CHECK-NEXT: blr
+}
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