[PATCH] D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: lib/Target/X86/X86InstrAVX512.td:2749
                              RegisterClass KRC, RegisterClass GRC> {
-  let hasSideEffects = 0 in {
+  let hasSideEffects = 0, isMoveReg = 1 in {
     def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
----------------
The widths of the registers don't always match here. Is that a problem? Bits are either truncated or zero extended.


https://reviews.llvm.org/D45204