[PATCH] D45540: [globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them

[Daniel Sanders via Phabricator via llvm-commits]

dsanders created this revision.
dsanders added reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka.
Herald added subscribers: javed.absar, kristof.beyls.

Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:

- G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes.
- All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization).
- At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted.
- The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style.

This patch begins changing the representation to:

- (G_[SZ]EXTLOAD x)
- (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()

which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.

Depends on https://reviews.llvm.org/D45466


Repository:
  rL LLVM

https://reviews.llvm.org/D45540

Files:
  include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
  include/llvm/Support/TargetOpcodes.def
  include/llvm/Target/GenericOpcodes.td
  lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  lib/Target/AArch64/AArch64LegalizerInfo.cpp
  test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
  test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
  test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir

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