[PATCH] D44785: Lowering x86 adds/addus/subs/subus intrinsics (llvm part)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Do we have test cases for types less than 128-bits to make sure we don't convert them?



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Comment at: lib/Target/X86/X86ISelLowering.cpp:36054
+  // Get addition elements.
+  auto LHS = Sat.getOperand(0);
+  auto RHS = Sat.getOperand(1);
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Use SDValue instead of auto. LLVM tends to be conservative with use of auto.


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Comment at: test/CodeGen/X86/vector-arith-sat.ll:10
+; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=-avx,+sse2 -show-mc-encoding | FileCheck %s --check-prefix=SSE
+define <32 x i8> @test_x86_avx2_padds_b(<32 x i8> %a0, <32 x i8> %a1) {
+; AVX2-LABEL: test_x86_avx2_padds_b:
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Add a blank line here.


Repository:
  rL LLVM

https://reviews.llvm.org/D44785