[llvm] r328506 - [Hexagon] Give priority to post-incremementing memory accesses in LSR
Galina Kistanova via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 10 15:29:27 PDT 2018
Hello Krzysztof,
> llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll
This test is flaky as it depends on a certain order of commands which could
be different time to time. Either test or CodeGen shall be fixed.
C:\ps4-buildslave2\llvm-clang-x86_64-expensive-checks-win\llvm\test\CodeGen\Hexagon\swp-vmult.ll:5:15:
error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}}++#4)
^
<stdin>:30:2: note: 'next' match was here
r3 = memw(r2++#4)
^
<stdin>:28:19: note: previous match ended here
r0 += mpyi(r4,r3)
^
<stdin>:29:1: note: non-matching line after previous match is here
r4 = memw(r1++#4)
^
Please also find attached the intermediate IR file I have got on the
buildbot in case that would help with your debugging.
I have made this test unsupported in r329763 for now with till it gets
fixed.
Hope this helps.
Thanks
Galina
On Mon, Mar 26, 2018 at 8:32 AM, Krzysztof Parzyszek via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: kparzysz
> Date: Mon Mar 26 08:32:03 2018
> New Revision: 328506
>
> URL: http://llvm.org/viewvc/llvm-project?rev=328506&view=rev
> Log:
> [Hexagon] Give priority to post-incremementing memory accesses in LSR
>
> Modified:
> llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h
> llvm/trunk/test/CodeGen/Hexagon/swp-epilog-numphis.ll
> llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll
> llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll
> llvm/trunk/test/CodeGen/Hexagon/vect-downscale.ll
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/
> HexagonTargetTransformInfo.cpp?rev=328506&r1=328505&r2=328506&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
> (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp Mon Mar
> 26 08:32:03 2018
> @@ -43,6 +43,10 @@ void HexagonTTIImpl::getUnrollingPrefere
> UP.Runtime = UP.Partial = true;
> }
>
> +bool HexagonTTIImpl::shouldFavorPostInc() const {
> + return true;
> +}
> +
> unsigned HexagonTTIImpl::getNumberOfRegisters(bool vector) const {
> return vector ? 0 : 32;
> }
> @@ -81,5 +85,5 @@ int HexagonTTIImpl::getUserCost(const Us
> }
>
> bool HexagonTTIImpl::shouldBuildLookupTables() const {
> - return EmitLookupTables;
> + return EmitLookupTables;
> }
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/
> HexagonTargetTransformInfo.h?rev=328506&r1=328505&r2=328506&view=diff
> ============================================================
> ==================
> --- llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonTargetTransformInfo.h Mon Mar 26
> 08:32:03 2018
> @@ -57,6 +57,9 @@ public:
> void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
> TTI::UnrollingPreferences &UP);
>
> + /// Bias LSR towards creating post-increment opportunities.
> + bool shouldFavorPostInc() const;
> +
> // L1 cache prefetch.
> unsigned getPrefetchDistance() const;
> unsigned getCacheLineSize() const;
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/swp-epilog-numphis.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/Hexagon/swp-epilog-numphis.ll?rev=328506&r1=
> 328505&r2=328506&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/Hexagon/swp-epilog-numphis.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/swp-epilog-numphis.ll Mon Mar 26
> 08:32:03 2018
> @@ -1,3 +1,5 @@
> +; XFAIL: *
> +; Needs some fixed in the pipeliner.
> ; RUN: llc -march=hexagon < %s | FileCheck %s
>
> ; CHECK: endloop0
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/Hexagon/swp-vmult.ll?rev=328506&r1=328505&r2=328506&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/swp-vmult.ll Mon Mar 26 08:32:03 2018
> @@ -1,33 +1,30 @@
> ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s |
> FileCheck %s
> -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
>
> ; Multiply and accumulate
> ; CHECK: mpyi([[REG0:r([0-9]+)]],[[REG1:r([0-9]+)]])
> -; CHECK-NEXT: add(r{{[0-9]+}},#4)
> -; CHECK-DAG: [[REG1]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
> -; CHECK-DAG: [[REG0]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
> +; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}}++#4)
> +; CHECK-NEXT: [[REG0]] = memw(r{{[0-9]+}}++#4)
> ; CHECK-NEXT: endloop0
>
> -define i32 @foo(i32* %a, i32* %b, i32 %n) {
> -entry:
> - br label %for.body
> +define i32 @f0(i32* %a0, i32* %a1, i32 %a2) {
> +b0:
> + br label %b1
>
> -for.body:
> - %sum.03 = phi i32 [ 0, %entry ], [ %add, %for.body ]
> - %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
> - %arrayidx1.phi = phi i32* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]
> - %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
> - %0 = load i32, i32* %arrayidx.phi, align 4
> - %1 = load i32, i32* %arrayidx1.phi, align 4
> - %mul = mul nsw i32 %1, %0
> - %add = add nsw i32 %mul, %sum.03
> - %inc = add nsw i32 %i.02, 1
> - %exitcond = icmp eq i32 %inc, 10000
> - %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
> - %arrayidx1.inc = getelementptr i32, i32* %arrayidx1.phi, i32 1
> - br i1 %exitcond, label %for.end, label %for.body
> +b1: ; preds = %b1, %b0
> + %v0 = phi i32 [ 0, %b0 ], [ %v7, %b1 ]
> + %v1 = phi i32* [ %a0, %b0 ], [ %v10, %b1 ]
> + %v2 = phi i32* [ %a1, %b0 ], [ %v11, %b1 ]
> + %v3 = phi i32 [ 0, %b0 ], [ %v8, %b1 ]
> + %v4 = load i32, i32* %v1, align 4
> + %v5 = load i32, i32* %v2, align 4
> + %v6 = mul nsw i32 %v5, %v4
> + %v7 = add nsw i32 %v6, %v0
> + %v8 = add nsw i32 %v3, 1
> + %v9 = icmp eq i32 %v8, 10000
> + %v10 = getelementptr i32, i32* %v1, i32 1
> + %v11 = getelementptr i32, i32* %v2, i32 1
> + br i1 %v9, label %b2, label %b1
>
> -for.end:
> - ret i32 %add
> +b2: ; preds = %b1
> + ret i32 %v7
> }
> -
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/Hexagon/swp-vsum.ll?rev=328506&r1=328505&r2=328506&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/swp-vsum.ll Mon Mar 26 08:32:03 2018
> @@ -1,29 +1,32 @@
> ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s |
> FileCheck %s
> -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
> +; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s |
> FileCheck %s --check-prefix=CHECKV60
>
> ; Simple vector total.
> ; CHECK: loop0(.LBB0_[[LOOP:.]],
> ; CHECK: .LBB0_[[LOOP]]:
> -; CHECK: add([[REG:r([0-9]+)]],r{{[0-9]+}})
> -; CHECK-NEXT: add(r{{[0-9]+}},#4)
> -; CHECK-NEXT: [[REG]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0)
> +; CHECK: add(r{{[0-9]+}},r{{[0-9]+}})
> +; CHECK-NEXT: memw(r{{[0-9]+}}++#4)
> ; CHECK-NEXT: endloop0
>
> -define i32 @foo(i32* %a, i32 %n) {
> -entry:
> - br label %for.body
> +; V60 does not pipeline due to latencies.
> +; CHECKV60: memw(r{{[0-9]+}}++#4)
> +; CHECKV60: add(r{{[0-9]+}},r{{[0-9]+}})
>
> -for.body:
> - %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
> - %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
> - %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
> - %0 = load i32, i32* %arrayidx.phi, align 4
> - %add = add nsw i32 %0, %sum.02
> - %inc = add nsw i32 %i.01, 1
> - %exitcond = icmp eq i32 %inc, 10000
> - %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
> - br i1 %exitcond, label %for.end, label %for.body
> +define i32 @f0(i32* %a0, i32 %a1) {
> +b0:
> + br label %b1
>
> -for.end:
> - ret i32 %add
> +b1: ; preds = %b1, %b0
> + %v0 = phi i32 [ 0, %b0 ], [ %v4, %b1 ]
> + %v1 = phi i32* [ %a0, %b0 ], [ %v7, %b1 ]
> + %v2 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
> + %v3 = load i32, i32* %v1, align 4
> + %v4 = add nsw i32 %v3, %v0
> + %v5 = add nsw i32 %v2, 1
> + %v6 = icmp eq i32 %v5, 10000
> + %v7 = getelementptr i32, i32* %v1, i32 1
> + br i1 %v6, label %b2, label %b1
> +
> +b2: ; preds = %b1
> + ret i32 %v4
> }
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/vect-downscale.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> CodeGen/Hexagon/vect-downscale.ll?rev=328506&r1=328505&r2=328506&view=diff
> ============================================================
> ==================
> --- llvm/trunk/test/CodeGen/Hexagon/vect-downscale.ll (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/vect-downscale.ll Mon Mar 26 08:32:03
> 2018
> @@ -12,6 +12,8 @@
> ; CHECK: {
> ; CHECK: }
> ; CHECK: {
> +; CHECK: }
> +; CHECK: {
> ; CHECK-NOT: }
> ; CHECK: }{{[ \t]*}}:endloop0
>
>
>
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> llvm-commits at lists.llvm.org
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