[PATCH] D45432: [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro.
Herald added subscribers: kristof.beyls, tschuett.

Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.

This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.


https://reviews.llvm.org/D45432

Files:
  lib/Target/AArch64/AArch64SVEInstrInfo.td
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  lib/Target/AArch64/SVEInstrFormats.td
  test/MC/AArch64/SVE/st1b-diagnostics.s
  test/MC/AArch64/SVE/st1b.s
  test/MC/AArch64/SVE/st1d-diagnostics.s
  test/MC/AArch64/SVE/st1d.s
  test/MC/AArch64/SVE/st1h-diagnostics.s
  test/MC/AArch64/SVE/st1h.s
  test/MC/AArch64/SVE/st1w-diagnostics.s
  test/MC/AArch64/SVE/st1w.s

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