[llvm] r329540 - [TargetSchedule] shrink interface for init(); NFCI
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 8 12:56:04 PDT 2018
Author: spatel
Date: Sun Apr 8 12:56:04 2018
New Revision: 329540
URL: http://llvm.org/viewvc/llvm-project?rev=329540&view=rev
Log:
[TargetSchedule] shrink interface for init(); NFCI
The TargetSchedModel is always initialized using the TargetSubtargetInfo's
MCSchedModel and TargetInstrInfo, so we don't need to extract those and
pass 3 parameters to init().
Differential Revision: https://reviews.llvm.org/D44789
Modified:
llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
llvm/trunk/lib/CodeGen/IfConversion.cpp
llvm/trunk/lib/CodeGen/MachineCombiner.cpp
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/trunk/lib/CodeGen/TargetSchedule.cpp
llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp
llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp
llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
Modified: llvm/trunk/include/llvm/CodeGen/TargetSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetSchedule.h?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetSchedule.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetSchedule.h Sun Apr 8 12:56:04 2018
@@ -50,8 +50,7 @@ public:
/// The machine model API keeps a copy of the top-level MCSchedModel table
/// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
/// dynamic properties.
- void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
- const TargetInstrInfo *tii);
+ void init(const TargetSubtargetInfo *TSInfo);
/// Return the MCSchedClassDesc for this instruction.
const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Sun Apr 8 12:56:04 2018
@@ -347,7 +347,7 @@ bool IfConverter::runOnMachineFunction(M
BranchFolder::MBFIWrapper MBFI(getAnalysis<MachineBlockFrequencyInfo>());
MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
MRI = &MF.getRegInfo();
- SchedModel.init(ST.getSchedModel(), &ST, TII);
+ SchedModel.init(&ST);
if (!TII) return false;
Modified: llvm/trunk/lib/CodeGen/MachineCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCombiner.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCombiner.cpp Sun Apr 8 12:56:04 2018
@@ -633,7 +633,7 @@ bool MachineCombiner::runOnMachineFuncti
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
SchedModel = STI->getSchedModel();
- TSchedModel.init(SchedModel, STI, TII);
+ TSchedModel.init(STI);
MRI = &MF.getRegInfo();
MLI = &getAnalysis<MachineLoopInfo>();
Traces = &getAnalysis<MachineTraceMetrics>();
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Sun Apr 8 12:56:04 2018
@@ -314,7 +314,7 @@ bool MachineLICMBase::runOnMachineFuncti
TRI = ST.getRegisterInfo();
MFI = &MF.getFrameInfo();
MRI = &MF.getRegInfo();
- SchedModel.init(ST.getSchedModel(), &ST, TII);
+ SchedModel.init(&ST);
PreRegAlloc = MRI->isSSA();
Modified: llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp Sun Apr 8 12:56:04 2018
@@ -70,7 +70,7 @@ bool MachineTraceMetrics::runOnMachineFu
TRI = ST.getRegisterInfo();
MRI = &MF->getRegInfo();
Loops = &getAnalysis<MachineLoopInfo>();
- SchedModel.init(ST.getSchedModel(), &ST, TII);
+ SchedModel.init(&ST);
BlockInfo.resize(MF->getNumBlockIDs());
ProcResourceCycles.resize(MF->getNumBlockIDs() *
SchedModel.getNumProcResourceKinds());
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Sun Apr 8 12:56:04 2018
@@ -118,7 +118,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(Mac
DbgValues.clear();
const TargetSubtargetInfo &ST = mf.getSubtarget();
- SchedModel.init(ST.getSchedModel(), &ST, TII);
+ SchedModel.init(&ST);
}
/// If this machine instr has memory reference information and it can be
Modified: llvm/trunk/lib/CodeGen/TargetSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSchedule.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSchedule.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSchedule.cpp Sun Apr 8 12:56:04 2018
@@ -61,12 +61,10 @@ static unsigned lcm(unsigned A, unsigned
return LCM;
}
-void TargetSchedModel::init(const MCSchedModel &sm,
- const TargetSubtargetInfo *sti,
- const TargetInstrInfo *tii) {
- SchedModel = sm;
- STI = sti;
- TII = tii;
+void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) {
+ STI = TSInfo;
+ SchedModel = TSInfo->getSchedModel();
+ TII = TSInfo->getInstrInfo();
STI->initInstrItins(InstrItins);
unsigned NumRes = SchedModel.getNumProcResourceKinds();
Modified: llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetSubtargetInfo.cpp Sun Apr 8 12:56:04 2018
@@ -88,7 +88,7 @@ std::string TargetSubtargetInfo::getSche
// We don't cache TSchedModel because it depends on TargetInstrInfo
// that could be changed during the compilation
TargetSchedModel TSchedModel;
- TSchedModel.init(getSchedModel(), this, getInstrInfo());
+ TSchedModel.init(this);
unsigned Latency = TSchedModel.computeInstrLatency(&MI);
Optional<double> RThroughput = TSchedModel.computeInstrRThroughput(&MI);
return createSchedInfoStr(Latency, RThroughput);
@@ -99,7 +99,7 @@ std::string TargetSubtargetInfo::getSche
// We don't cache TSchedModel because it depends on TargetInstrInfo
// that could be changed during the compilation
TargetSchedModel TSchedModel;
- TSchedModel.init(getSchedModel(), this, getInstrInfo());
+ TSchedModel.init(this);
unsigned Latency;
if (TSchedModel.hasInstrSchedModel())
Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
Modified: llvm/trunk/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp Sun Apr 8 12:56:04 2018
@@ -700,7 +700,7 @@ bool AArch64SIMDInstrOpt::runOnMachineFu
static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
if (!AAII)
return false;
- SchedModel.init(ST.getSchedModel(), &ST, AAII);
+ SchedModel.init(&ST);
if (!SchedModel.hasInstrSchedModel())
return false;
Modified: llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64StorePairSuppress.cpp Sun Apr 8 12:56:04 2018
@@ -127,7 +127,7 @@ bool AArch64StorePairSuppress::runOnMach
TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
TRI = ST.getRegisterInfo();
MRI = &MF.getRegInfo();
- SchedModel.init(ST.getSchedModel(), &ST, TII);
+ SchedModel.init(&ST);
Traces = &getAnalysis<MachineTraceMetrics>();
MinInstr = nullptr;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZMachineScheduler.cpp Sun Apr 8 12:56:04 2018
@@ -133,7 +133,7 @@ SystemZPostRASchedStrategy(const Machine
(C->MF->getSubtarget().getInstrInfo())),
MBB(nullptr), HazardRec(nullptr) {
const TargetSubtargetInfo *ST = &C->MF->getSubtarget();
- SchedModel.init(ST->getSchedModel(), ST, TII);
+ SchedModel.init(ST);
}
SystemZPostRASchedStrategy::~SystemZPostRASchedStrategy() {
Modified: llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CmovConversion.cpp?rev=329540&r1=329539&r2=329540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CmovConversion.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CmovConversion.cpp Sun Apr 8 12:56:04 2018
@@ -178,7 +178,7 @@ bool X86CmovConverterPass::runOnMachineF
MRI = &MF.getRegInfo();
TII = STI.getInstrInfo();
TRI = STI.getRegisterInfo();
- TSchedModel.init(STI.getSchedModel(), &STI, TII);
+ TSchedModel.init(&STI);
// Before we handle the more subtle cases of register-register CMOVs inside
// of potentially hot loops, we want to quickly remove all CMOVs with
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