[PATCH] D41350: [DAGCombine] Improve ReduceLoadWidth for SRL

[Sam Parker via Phabricator via llvm-commits]

samparker updated this revision to Diff 141344.
samparker added a comment.

The trunc_i64_mask_srl test has been added. This example showed that I had a typo in my patch, I was checking the user of N and not 'N0'! So I've also renamed some variables to reduce the chance of possible confusion again.


https://reviews.llvm.org/D41350

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/ARM/shift-combine.ll
  test/CodeGen/X86/h-registers-1.ll

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