[PATCH] D43235: [SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639) (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL329280: [SchedModel] Complete models shouldn't match against itineraries when they… (authored by RKSimon, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43235?vs=137636&id=141143#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43235

Files:
  llvm/trunk/lib/Target/AMDGPU/SISchedule.td
  llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
  llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
  llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td
  llvm/trunk/utils/TableGen/CodeGenSchedule.cpp


Index: llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP9.td
@@ -33,7 +33,7 @@
   // A dispatch group is 6 instructions.
   let LoopMicroOpBufferSize = 60;
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
 
   // Do not support QPX (Quad Processing eXtension) on Power 9.
   let UnsupportedFeatures = [HasQPX];
Index: llvm/trunk/lib/Target/AMDGPU/SISchedule.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SISchedule.td
+++ llvm/trunk/lib/Target/AMDGPU/SISchedule.td
@@ -46,7 +46,7 @@
 // instructions)
 
 class SISchedMachineModel : SchedMachineModel {
-  let CompleteModel = 1;
+  let CompleteModel = 0;
   // MicroOpBufferSize = 1 means that instructions will always be added
   // the ready queue when they become available.  This exposes them
   // to the register pressure analysis.
Index: llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
+++ llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td
@@ -13,7 +13,7 @@
   int LoadLatency = 4;
   int MispredictPenalty = 8; // TODO: Estimated
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
 
   list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6,
                                          HasMips64, HasMips64r2, HasCnMips,
Index: llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
+++ llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
@@ -25,7 +25,7 @@
   int HighLatency = 37;
   list<Predicate> UnsupportedFeatures = [];
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
   let PostRAScheduler = 1;
 
   // FIXME: Remove when all errors have been fixed.
Index: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
@@ -1626,6 +1626,7 @@
   bool Complete = true;
   bool HadCompleteModel = false;
   for (const CodeGenProcModel &ProcModel : procModels()) {
+    const bool HasItineraries = ProcModel.hasItineraries();
     if (!ProcModel.ModelDef->getValueAsBit("CompleteModel"))
       continue;
     for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
@@ -1646,7 +1647,7 @@
       const CodeGenSchedClass &SC = getSchedClass(SCIdx);
       if (!SC.Writes.empty())
         continue;
-      if (SC.ItinClassDef != nullptr &&
+      if (HasItineraries && SC.ItinClassDef != nullptr &&
           SC.ItinClassDef->getName() != "NoItinerary")
         continue;
 


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