[PATCH] D45230: [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.

I think overall, we want to cover all the ways we can get the input integer:

- Extending load from a smaller type (only unsigned forms for byte and halfword, both signed and unsigned for word)
- Extracting from a vector (with sign extensions as needed)
- Smaller types in registers
- An fp to int conversion
- A bitcast

I don't mind that being split up into multiple patches, but I think we can at least start with a test case for each of the cases with FIXME's for what we're going to cover in upcoming patches.



================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:3121
             (f32 (DFLOADf32 ixaddr:$src))>;
+
+  // Convert (Un)Signed DWord in memory -> QP
----------------
I just realized that we should also add patterns for converting an extracted vector value to `f128` because it will currently do `mfvsrd -> mtvsrd -> xscv[us]dqp` which is obviously redundant.
We will also need patterns for extending loads from byte, halfword and word.


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Comment at: test/CodeGen/PowerPC/f128-conv.ll:3
+; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
+
+ at mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
----------------
Please add test cases that convert from smaller integer types as well (byte, halfword and word).


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Comment at: test/CodeGen/PowerPC/f128-conv.ll:22
+; Function Attrs: norecurse nounwind
+define void @sdwConv2qp_02(fp128* nocapture %a) {
+entry:
----------------
Please also add a version of the test where the integer value is passed as a parameter by pointer (for both the signed and unsigned conversions).


https://reviews.llvm.org/D45230