[PATCH] D45229: [MI-sched] schedule following instruction latencies

[Javed Absar via Phabricator via llvm-commits]

javed.absar added a comment.

Hi Sebastian:
For the test case, the change looks good, though I am surprised the current scheduling algorithm does that (i.e. scheduling store just one cycle after load which definitely would result in stalls, especially for in-order processors). I am guessing the latency it is picking up is 1?


https://reviews.llvm.org/D45229