[PATCH] D45181: [RISCV WIP] Add diff relocation support for RISC-V

[Simon Cook via Phabricator via llvm-commits]

simoncook created this revision.
Herald added subscribers: llvm-commits, shiva0217, kito-cheng, JDevlieghere, niosHD, sabuasal, apazos, jordy.potman.lists, johnrusso, rbar, asb, aprantl.

For RISC-V it is desirable to have relaxation happen in the linker once addresses are known, and as such the size between two instructions/byte sequences in a section could change.

For most assembler expressions, this is fine, as the absolute address results in the expression being converted to a fixup, and finally relocations. However, for expressions such as `.quad .L2-.L1`, the assembler folds this down to a constant once fragments are laid out, under the assumption that the difference can no longer change, although in the case of linker relaxation the differences can change at link time, so the constant is incorrect. One place where this commonly appears is in debug information, where the size of a function expression is in a form similar to the above.

This patch extends the assembler to allow an AsmBackend to declare that it does not want the assembler to fold down this expression, and instead generate a pair of relocations that allow the linker to carry out the calculation. In this case, the expression is not folded, but when it comes to emitting a fixup, the generic FK_Data_* fixups are converted into a pair, one for the addition half, one for the subtraction, and this is passed to the relocation generating methods as usual. I have named these FK_Data_Add_* and FK_Data_Sub_* to indicate which half these are for.

For RISC-V, which supports this via e.g. the R_RISCV_ADD64, R_RISCV_SUB64 pair of relocations, these are also set to always emit relocations relative to local symbols rather than section offsets. This is to deal with the fact that if relocations were calculated on e.g. .text+8 and .text+4, the result 12 would be stored rather than 4 as both addends are added in the linker.

Note: If the overall approach is fine, there's a couple of things that need doing before committing. There are a couple of RISC-V tests which fail, either support for target-specific fixups need adding (if these are supported by the linker, this needs checking against gas), and a couple more tests need adding.


Repository:
  rL LLVM

https://reviews.llvm.org/D45181

Files:
  include/llvm/MC/MCAsmBackend.h
  include/llvm/MC/MCFixup.h
  lib/MC/MCAsmBackend.cpp
  lib/MC/MCAssembler.cpp
  lib/MC/MCExpr.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
  test/MC/RISCV/fixups-expr.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D45181.140678.patch
Type: text/x-patch
Size: 9586 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180402/57af4814/attachment.bin>