[PATCH] D45119: [RISCV] Override EmitToStreamer in RISCVAsmPrinter to handle missed compression opportunities

[Sameer AbuAsal via Phabricator via llvm-commits]

sabuasal created this revision.
sabuasal added reviewers: asb, apazos, mgrang, llvm-commits.
Herald added subscribers: shiva0217, kito-cheng, niosHD, jordy.potman.lists, simoncook, johnrusso, rbar.
sabuasal added a dependency: D41932: [RISCV] Hooks for enabling instruction compression.

Updating Comperession hooks in https://reviews.llvm.org/D41932 to move comperession from
ElfStream to AsmPrinter caused missing  opportunities for
compression. This is due to emitPseudoExpansionLowering lowering
Machine instructions to MC Instructions and emitting them directly
to the stream without calling compression.

      

this patch fixes the problem by overriding EmitToStreamer in
 RISCVAsmPrinter to call compressInst before emitting.


https://reviews.llvm.org/D45119

Files:
  include/llvm/CodeGen/AsmPrinter.h
  lib/Target/RISCV/RISCVAsmPrinter.cpp
  test/CodeGen/RISCV/compress-Pseudo.ll


Index: test/CodeGen/RISCV/compress-Pseudo.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/compress-Pseudo.ll
@@ -0,0 +1,10 @@
+; RUN: llc -mtriple=riscv32 -mattr=+c  -riscv-no-aliases -o %t1 < %s
+; RUN: FileCheck %s < %t1
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:   c.jr
+
+end:
+  ret void
+}
Index: lib/Target/RISCV/RISCVAsmPrinter.cpp
===================================================================
--- lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -49,6 +49,7 @@
                              unsigned AsmVariant, const char *ExtraCode,
                              raw_ostream &OS) override;
 
+  void EmitToStreamer(MCStreamer &S, const MCInst &Inst) override;
   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
 
@@ -59,22 +60,27 @@
 };
 }
 
+#define GEN_COMPRESS_INSTR
+#include "RISCVGenCompressInstEmitter.inc"
+void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
+  MCInst CInst;
+  bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(),
+                          OutStreamer->getContext());
+  AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
+}
+
 // Simple pseudo-instructions have their lowering (with expansion to real
 // instructions) auto-generated.
 #include "RISCVGenMCPseudoLowering.inc"
 
-#define GEN_COMPRESS_INSTR
-#include "RISCVGenCompressInstEmitter.inc"
 void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   // Do any auto-generated pseudo lowerings.
   if (emitPseudoExpansionLowering(*OutStreamer, MI))
     return;
 
-  MCInst TmpInst, CInst;
+  MCInst TmpInst;
   LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
-  bool Res = compressInst(CInst, TmpInst, *TM.getMCSubtargetInfo(),
-                          OutStreamer->getContext());
-  EmitToStreamer(*OutStreamer, Res ? CInst : TmpInst);
+  EmitToStreamer(*OutStreamer, TmpInst);
 }
 
 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
Index: include/llvm/CodeGen/AsmPrinter.h
===================================================================
--- include/llvm/CodeGen/AsmPrinter.h
+++ include/llvm/CodeGen/AsmPrinter.h
@@ -233,7 +233,7 @@
   /// Return information about subtarget.
   const MCSubtargetInfo &getSubtargetInfo() const;
 
-  void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
+  virtual void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
 
   /// Return the current section we are emitting to.
   const MCSection *getCurrentSection() const;


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