[PATCH] D44785: Lowering x86 adds/addus/subs/subus intrinsics (llvm part)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

We should probably have a test file for the IR that isn't the fast-isel or schedule test.

We should also test 512 bit vectors with AVX2/AVX512F and 1024-bit vectors with AVX512BW, etc.



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Comment at: lib/Target/X86/X86ISelLowering.cpp:36017
+        isPowerOf2_32(NumElems)))
+    return SDValue();
+
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What ensures we don't create X86ISD::ADDS for with a type smaller than 128 bits? For example if VT was v4i8


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Comment at: lib/Target/X86/X86ISelLowering.cpp:36059
+  if ((!Signed && (LHS.getOpcode() != ISD::ZERO_EXTEND ||
+                  RHS.getOpcode() != ISD::ZERO_EXTEND)) ||
+       (Signed && (LHS.getOpcode() != ISD::SIGN_EXTEND ||
----------------
Line this up with LHS on the line above


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Comment at: lib/Target/X86/X86ISelLowering.cpp:36061
+       (Signed && (LHS.getOpcode() != ISD::SIGN_EXTEND ||
+                  RHS.getOpcode() != ISD::SIGN_EXTEND)))
+    return SDValue();
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Line this up


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Comment at: lib/Target/X86/X86ISelLowering.cpp:36066
+  auto AddSubSatBuilder = [Opcode](SelectionDAG &DAG, const SDLoc &DL,
+                                            ArrayRef<SDValue> Ops) {
+    EVT VT = Ops[0].getValueType();
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Identation


Repository:
  rL LLVM

https://reviews.llvm.org/D44785