[PATCH] D44779: [AMDGPU][MC] Added ds_add_src2_f32

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL328713: [AMDGPU][MC] Added ds_add_src2_f32 (authored by dpreobra, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D44779?vs=139435&id=140092#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D44779

Files:
  llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
  llvm/trunk/test/MC/AMDGPU/ds.s
  llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt


Index: llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt
@@ -323,3 +323,6 @@
 
 # VI:   ds_read2st64_b64 v[8:11], v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0xf0 0xd8 0x02 0x00 0x00 0x08
+
+# VI:   ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
+0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00
Index: llvm/trunk/test/MC/AMDGPU/ds.s
===================================================================
--- llvm/trunk/test/MC/AMDGPU/ds.s
+++ llvm/trunk/test/MC/AMDGPU/ds.s
@@ -15,6 +15,14 @@
 // SICI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 // VI:   ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
 
+ds_add_src2_f32 v255 offset:65535
+// NOSICI: error
+// VI: ds_add_src2_f32 v255 offset:65535 ; encoding: [0xff,0xff,0x2a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_f32 v0 offset:4 gds
+// NOSICI: error
+// VI: ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
+
 //===----------------------------------------------------------------------===//
 // Checks for 2 8-bit Offsets
 //===----------------------------------------------------------------------===//
Index: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
+++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
@@ -584,6 +584,8 @@
                                        int_amdgcn_ds_bpermute>;
 }
 
+def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
+
 } // let SubtargetPredicate = isVI
 
 //===----------------------------------------------------------------------===//
@@ -1129,6 +1131,7 @@
 def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
 def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
 def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
+def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
 def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
 def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
 def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;


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