[llvm] r328710 - [AMDGPU][MC] Added PCK variants of image load/store instructions
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 28 08:44:16 PDT 2018
Author: dpreobra
Date: Wed Mar 28 08:44:16 2018
New Revision: 328710
URL: http://llvm.org/viewvc/llvm-project?rev=328710&view=rev
Log:
[AMDGPU][MC] Added PCK variants of image load/store instructions
See bug 36834: https://bugs.llvm.org/show_bug.cgi?id=36834
Differential Revision: https://reviews.llvm.org/D44795
Reviewers: artem.tamazov, arsenm, timcorringham, nhaehnle
Modified:
llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td
llvm/trunk/test/MC/AMDGPU/mimg.s
llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt
Modified: llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td?rev=328710&r1=328709&r2=328710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td Wed Mar 28 08:44:16 2018
@@ -53,27 +53,27 @@ multiclass MIMG_NoSampler_Src_Helper_Hel
RegisterClass dst_rc,
int channels, bit d16_bit,
string suffix> {
- def _V1 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, d16_bit,
- !if(!eq(channels, 1), "AMDGPU", "")>,
- MIMG_Mask<asm#"_V1"#suffix, channels>;
- def _V2 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64, d16_bit>,
- MIMG_Mask<asm#"_V2"#suffix, channels>;
- def _V4 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128, d16_bit>,
- MIMG_Mask<asm#"_V4"#suffix, channels>;
+ def NAME # _V1 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, d16_bit,
+ !if(!eq(channels, 1), "AMDGPU", "")>,
+ MIMG_Mask<asm#"_V1"#suffix, channels>;
+ def NAME # _V2 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64, d16_bit>,
+ MIMG_Mask<asm#"_V2"#suffix, channels>;
+ def NAME # _V4 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128, d16_bit>,
+ MIMG_Mask<asm#"_V4"#suffix, channels>;
}
multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
int channels> {
- defm : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 0, "">;
+ defm NAME : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 0, "">;
let d16 = 1 in {
let SubtargetPredicate = HasPackedD16VMem in {
- defm : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 1, "_D16">;
+ defm NAME : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 1, "_D16">;
} // End HasPackedD16VMem.
let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
- defm : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 1, "_D16_gfx80">;
+ defm NAME : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 1, "_D16_gfx80">;
} // End HasUnpackedD16VMem.
} // End d16 = 1.
}
@@ -85,6 +85,13 @@ multiclass MIMG_NoSampler <bits<7> op, s
defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
}
+multiclass MIMG_PckNoSampler <bits<7> op, string asm> {
+ defm NAME # _V1 : MIMG_NoSampler_Src_Helper_Helper <op, asm, VGPR_32, 1, 0, "">;
+ defm NAME # _V2 : MIMG_NoSampler_Src_Helper_Helper <op, asm, VReg_64, 2, 0, "">;
+ defm NAME # _V3 : MIMG_NoSampler_Src_Helper_Helper <op, asm, VReg_96, 3, 0, "">;
+ defm NAME # _V4 : MIMG_NoSampler_Src_Helper_Helper <op, asm, VReg_128, 4, 0, "">;
+}
+
class MIMG_Store_Helper <bits<7> op, string asm,
RegisterClass data_rc,
RegisterClass addr_rc,
@@ -108,27 +115,27 @@ multiclass MIMG_Store_Addr_Helper_Helper
RegisterClass data_rc,
int channels, bit d16_bit,
string suffix> {
- def _V1 # suffix : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, d16_bit,
- !if(!eq(channels, 1), "AMDGPU", "")>,
- MIMG_Mask<asm#"_V1"#suffix, channels>;
- def _V2 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_64, d16_bit>,
- MIMG_Mask<asm#"_V2"#suffix, channels>;
- def _V4 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_128, d16_bit>,
- MIMG_Mask<asm#"_V4"#suffix, channels>;
+ def NAME # _V1 # suffix : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, d16_bit,
+ !if(!eq(channels, 1), "AMDGPU", "")>,
+ MIMG_Mask<asm#"_V1"#suffix, channels>;
+ def NAME # _V2 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_64, d16_bit>,
+ MIMG_Mask<asm#"_V2"#suffix, channels>;
+ def NAME # _V4 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_128, d16_bit>,
+ MIMG_Mask<asm#"_V4"#suffix, channels>;
}
multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm,
RegisterClass data_rc,
int channels> {
- defm : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 0, "">;
+ defm NAME : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 0, "">;
let d16 = 1 in {
let SubtargetPredicate = HasPackedD16VMem in {
- defm : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 1, "_D16">;
+ defm NAME : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 1, "_D16">;
} // End HasPackedD16VMem.
let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
- defm : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 1, "_D16_gfx80">;
+ defm NAME : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 1, "_D16_gfx80">;
} // End HasUnpackedD16VMem.
} // End d16 = 1.
}
@@ -140,6 +147,13 @@ multiclass MIMG_Store <bits<7> op, strin
defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 4>;
}
+multiclass MIMG_PckStore <bits<7> op, string asm> {
+ defm NAME # _V1 : MIMG_Store_Addr_Helper_Helper <op, asm, VGPR_32, 1, 0, "">;
+ defm NAME # _V2 : MIMG_Store_Addr_Helper_Helper <op, asm, VReg_64, 2, 0, "">;
+ defm NAME # _V3 : MIMG_Store_Addr_Helper_Helper <op, asm, VReg_96, 3, 0, "">;
+ defm NAME # _V4 : MIMG_Store_Addr_Helper_Helper <op, asm, VReg_128, 4, 0, "">;
+}
+
class MIMG_Atomic_Helper <string asm, RegisterClass data_rc,
RegisterClass addr_rc, string dns="",
bit enableDasm = 0> : MIMG_Helper <
@@ -347,14 +361,14 @@ multiclass MIMG_Gather_WQM <bits<7> op,
let SubtargetPredicate = isGCN in {
defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
-//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
-//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
-//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
-//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
+defm IMAGE_LOAD_PCK : MIMG_PckNoSampler <0x00000002, "image_load_pck">;
+defm IMAGE_LOAD_PCK_SGN : MIMG_PckNoSampler <0x00000003, "image_load_pck_sgn">;
+defm IMAGE_LOAD_MIP_PCK : MIMG_PckNoSampler <0x00000004, "image_load_mip_pck">;
+defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_PckNoSampler <0x00000005, "image_load_mip_pck_sgn">;
defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store">;
defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip">;
-//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
-//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
+defm IMAGE_STORE_PCK : MIMG_PckStore <0x0000000a, "image_store_pck">;
+defm IMAGE_STORE_MIP_PCK : MIMG_PckStore <0x0000000b, "image_store_mip_pck">;
let mayLoad = 0, mayStore = 0 in {
defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
Modified: llvm/trunk/test/MC/AMDGPU/mimg.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/mimg.s?rev=328710&r1=328709&r2=328710&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/mimg.s (original)
+++ llvm/trunk/test/MC/AMDGPU/mimg.s Wed Mar 28 08:44:16 2018
@@ -140,6 +140,47 @@ image_load v[5:7], v[1:4], s[8:15] dmask
// GFX9: image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80]
//===----------------------------------------------------------------------===//
+// Image Load/Store: PCK variants
+//===----------------------------------------------------------------------===//
+
+image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1
+// GCN: image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x3
+// GCN: image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x3 ; encoding: [0x00,0x03,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da
+// GCN: image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da ; encoding: [0x00,0x71,0x13,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:4], s[8:15] dmask:0x5
+// GCN: image_load_mip_pck_sgn v[5:6], v[1:4], s[8:15] dmask:0x5 ; encoding: [0x00,0x05,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:4], s[8:15] dmask:0x1 glc
+// GCN: image_load_pck v5, v[1:4], s[8:15] dmask:0x1 glc ; encoding: [0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:4], s[8:15] dmask:0x1 lwe
+// GCN: image_load_pck_sgn v5, v[1:4], s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x0e,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1 d16
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+
+image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 unorm
+// GCN: image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da
+// GCN: image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da ; encoding: [0x00,0x71,0x2e,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm da
+// GCN: image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 d16
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+// NOGFX9: error: invalid operand for instruction
+
+//===----------------------------------------------------------------------===//
// Image Sample
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt?rev=328710&r1=328709&r2=328710&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/mimg_vi.txt Wed Mar 28 08:44:16 2018
@@ -78,6 +78,34 @@
0x00,0x0f,0x20,0xf0,0x04,0x00,0x02,0x80
#===------------------------------------------------------------------------===#
+# Image load/store: PCK variants
+#===------------------------------------------------------------------------===#
+
+# VI: image_load_mip_pck v5, v1, s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_load_mip_pck v[5:6], v1, s[8:15] dmask:0x3 ; encoding: [0x00,0x03,0x10,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x03,0x10,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_load_mip_pck_sgn v[5:6], v1, s[8:15] dmask:0x5 ; encoding: [0x00,0x05,0x14,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x05,0x14,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_load_pck v5, v1, s[8:15] dmask:0x1 glc ; encoding: [0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x0e,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x01,0x0e,0xf0,0x01,0x05,0x02,0x00
+
+# VI: image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00
+
+# VI: image_store_mip_pck v1, v2, s[12:19] dmask:0x1 unorm glc slc lwe da ; encoding: [0x00,0x71,0x2e,0xf2,0x02,0x01,0x03,0x00]
+0x00,0x71,0x2e,0xf2,0x02,0x01,0x03,0x00
+
+# VI: image_store_pck v1, v2, s[12:19] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x28,0xf0,0x02,0x01,0x03,0x00]
+0x00,0x51,0x28,0xf0,0x02,0x01,0x03,0x00
+
+#===------------------------------------------------------------------------===#
# Image sample
#===------------------------------------------------------------------------===#
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