[PATCH] D44920: [AMDGPU] Inline asm - added i16, half and i128 types support

Daniil Fukalov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 27 03:30:41 PDT 2018


dfukalov created this revision.
dfukalov added a reviewer: arsenm.
dfukalov added a project: AMDGPU.
Herald added subscribers: eraman, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

AMDGPU inline assembler support i16, half and i128 typed variables in constraints, but they were reported as error.
Needed to fix https://github.com/RadeonOpenCompute/ROCm/issues/341,
e.g. to be able to load with global_load_dwordx4 to a 128bit integer variable


Repository:
  rL LLVM

https://reviews.llvm.org/D44920

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/inline-constraints.ll
  test/CodeGen/AMDGPU/inlineasm-16.ll
  test/CodeGen/AMDGPU/inlineasm-illegal-type.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D44920.139898.patch
Type: text/x-patch
Size: 11052 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180327/8cd644cf/attachment.bin>


More information about the llvm-commits mailing list