[llvm] r328558 - [Power9]Legalize and emit code for quad-precision convert from double-precision

[Lei Huang via llvm-commits]

Author: lei
Date: Mon Mar 26 10:46:25 2018
New Revision: 328558

URL: http://llvm.org/viewvc/llvm-project?rev=328558&view=rev
Log:
[Power9]Legalize and emit code for quad-precision convert from double-precision

Legalize and emit code for quad-precision floating point operation xscvdpqp
and add option to guard the quad precision operation support.

Differential Revision: https://reviews.llvm.org/D44746

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
    llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=328558&r1=328557&r2=328558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Mar 26 10:46:25 2018
@@ -111,6 +111,9 @@ cl::desc("disable unaligned load/store g
 static cl::opt<bool> DisableSCO("disable-ppc-sco",
 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
 
+static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
+cl::desc("enable quad precision float support on ppc"), cl::Hidden);
+
 STATISTIC(NumTailCalls, "Number of tail calls");
 STATISTIC(NumSiblingCalls, "Number of sibling calls");
 
@@ -787,11 +790,15 @@ PPCTargetLowering::PPCTargetLowering(con
       setOperationAction(ISD::SRL, MVT::v1i128, Legal);
       setOperationAction(ISD::SRA, MVT::v1i128, Expand);
 
-      addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
-      setOperationAction(ISD::FADD, MVT::f128, Legal);
-      setOperationAction(ISD::FSUB, MVT::f128, Legal);
-      setOperationAction(ISD::FDIV, MVT::f128, Legal);
-      setOperationAction(ISD::FMUL, MVT::f128, Legal);
+      if (EnableQuadPrecision) {
+        addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
+        setOperationAction(ISD::FADD, MVT::f128, Legal);
+        setOperationAction(ISD::FSUB, MVT::f128, Legal);
+        setOperationAction(ISD::FDIV, MVT::f128, Legal);
+        setOperationAction(ISD::FMUL, MVT::f128, Legal);
+        setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
+        setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
+      }
 
     }
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=328558&r1=328557&r2=328558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Mon Mar 26 10:46:25 2018
@@ -2470,6 +2470,7 @@ let AddedComplexity = 400, Predicates =
 
   // Convert DP -> QP
   def XSCVDPQP  : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, []>;
+  def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>;
 
   // Round & Convert QP -> DP (dword[1] is set to zero)
   def XSCVQPDP  : X_VT5_XO5_VB5   <63, 20, 836, "xscvqpdp" , []>;

Modified: llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll?rev=328558&r1=328557&r2=328558&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/f128-arith.ll Mon Mar 26 10:46:25 2018
@@ -1,4 +1,5 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -enable-ppc-quad-precision < %s | FileCheck %s
 
 ; Function Attrs: norecurse nounwind
 define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
@@ -147,3 +148,30 @@ entry:
 ; CHECK: stxv
 ; CHECK: blr
 }
+
+; Function Attrs: norecurse nounwind
+define void @dpConv2qp(double* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+  %0 = load double, double* %a, align 8
+  %conv = fpext double %0 to fp128
+  store fp128 %conv, fp128* %res, align 16
+  ret void
+; CHECK-LABEL: dpConv2qp
+; CHECK-NOT: bl __extenddftf2
+; CHECK: lxsd
+; CHECK: xscvdpqp
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @dpConv2qp_02(double %a, fp128* nocapture %res) {
+entry:
+  %conv = fpext double %a to fp128
+  store fp128 %conv, fp128* %res, align 16
+  ret void
+; CHECK-LABEL: dpConv2qp_02
+; CHECK-NOT: bl __extenddftf2
+; CHECK: xxlor
+; CHECK: xscvdpqp
+; CHECK: blr
+}