[llvm] r328474 - [X86] Fix the SchedRW for intrinsic register form of SQRT/RCP/RSQRT.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 25 22:05:12 PDT 2018
Author: ctopper
Date: Sun Mar 25 22:05:12 2018
New Revision: 328474
URL: http://llvm.org/viewvc/llvm-project?rev=328474&view=rev
Log:
[X86] Fix the SchedRW for intrinsic register form of SQRT/RCP/RSQRT.
Modified:
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/sse-schedule.ll
llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=328474&r1=328473&r2=328474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Mar 25 22:05:12 2018
@@ -3149,7 +3149,7 @@ multiclass sse_fp_unop_s<bits<8> opc, st
let isCodeGenOnly = 1, Constraints = "$src1 = $dst", ExeDomain = d in {
def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
- [], itins.rr>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
+ [], itins.rr>, Sched<[itins.Sched]>;
let mayLoad = 1 in
def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, intmemop:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
@@ -3195,7 +3195,7 @@ multiclass avx_fp_unop_s<bits<8> opc, st
def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
- [], itins.rr>, Sched<[itins.Sched.Folded]>;
+ [], itins.rr>, Sched<[itins.Sched]>;
let mayLoad = 1 in
def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, intmemop:$src2),
Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=328474&r1=328473&r2=328474&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Sun Mar 25 22:05:12 2018
@@ -4272,8 +4272,8 @@ define <4 x float> @test_rcpss(float %a0
; SLM-LABEL: test_rcpss:
; SLM: # %bb.0:
; SLM-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [3:1.00]
-; SLM-NEXT: rcpss %xmm0, %xmm0 # sched: [8:1.00]
-; SLM-NEXT: rcpss %xmm1, %xmm1 # sched: [8:1.00]
+; SLM-NEXT: rcpss %xmm0, %xmm0 # sched: [5:1.00]
+; SLM-NEXT: rcpss %xmm1, %xmm1 # sched: [5:1.00]
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
@@ -4360,32 +4360,32 @@ define <4 x float> @test_rcpss(float %a0
; BTVER2-SSE-LABEL: test_rcpss:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:1.00]
-; BTVER2-SSE-NEXT: rcpss %xmm0, %xmm0 # sched: [7:1.00]
-; BTVER2-SSE-NEXT: rcpss %xmm1, %xmm1 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: rcpss %xmm0, %xmm0 # sched: [2:1.00]
+; BTVER2-SSE-NEXT: rcpss %xmm1, %xmm1 # sched: [2:1.00]
; BTVER2-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_rcpss:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:1.00]
-; BTVER2-NEXT: vrcpss %xmm0, %xmm0, %xmm0 # sched: [7:1.00]
-; BTVER2-NEXT: vrcpss %xmm1, %xmm1, %xmm1 # sched: [7:1.00]
+; BTVER2-NEXT: vrcpss %xmm0, %xmm0, %xmm0 # sched: [2:1.00]
+; BTVER2-NEXT: vrcpss %xmm1, %xmm1, %xmm1 # sched: [2:1.00]
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_rcpss:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [8:0.50]
-; ZNVER1-SSE-NEXT: rcpss %xmm0, %xmm0 # sched: [12:0.50]
-; ZNVER1-SSE-NEXT: rcpss %xmm1, %xmm1 # sched: [12:0.50]
+; ZNVER1-SSE-NEXT: rcpss %xmm0, %xmm0 # sched: [5:0.50]
+; ZNVER1-SSE-NEXT: rcpss %xmm1, %xmm1 # sched: [5:0.50]
; ZNVER1-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
; ZNVER1-LABEL: test_rcpss:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [8:0.50]
-; ZNVER1-NEXT: vrcpss %xmm0, %xmm0, %xmm0 # sched: [12:0.50]
-; ZNVER1-NEXT: vrcpss %xmm1, %xmm1, %xmm1 # sched: [12:0.50]
+; ZNVER1-NEXT: vrcpss %xmm0, %xmm0, %xmm0 # sched: [5:0.50]
+; ZNVER1-NEXT: vrcpss %xmm1, %xmm1, %xmm1 # sched: [5:0.50]
; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = insertelement <4 x float> undef, float %a0, i32 0
@@ -4549,8 +4549,8 @@ define <4 x float> @test_rsqrtss(float %
; SLM-LABEL: test_rsqrtss:
; SLM: # %bb.0:
; SLM-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [3:1.00]
-; SLM-NEXT: rsqrtss %xmm0, %xmm0 # sched: [8:1.00]
-; SLM-NEXT: rsqrtss %xmm1, %xmm1 # sched: [8:1.00]
+; SLM-NEXT: rsqrtss %xmm0, %xmm0 # sched: [5:1.00]
+; SLM-NEXT: rsqrtss %xmm1, %xmm1 # sched: [5:1.00]
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
@@ -4637,16 +4637,16 @@ define <4 x float> @test_rsqrtss(float %
; BTVER2-SSE-LABEL: test_rsqrtss:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:1.00]
-; BTVER2-SSE-NEXT: rsqrtss %xmm0, %xmm0 # sched: [7:1.00]
-; BTVER2-SSE-NEXT: rsqrtss %xmm1, %xmm1 # sched: [7:1.00]
+; BTVER2-SSE-NEXT: rsqrtss %xmm0, %xmm0 # sched: [2:1.00]
+; BTVER2-SSE-NEXT: rsqrtss %xmm1, %xmm1 # sched: [2:1.00]
; BTVER2-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_rsqrtss:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero sched: [5:1.00]
-; BTVER2-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0 # sched: [7:1.00]
-; BTVER2-NEXT: vrsqrtss %xmm1, %xmm1, %xmm1 # sched: [7:1.00]
+; BTVER2-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0 # sched: [2:1.00]
+; BTVER2-NEXT: vrsqrtss %xmm1, %xmm1, %xmm1 # sched: [2:1.00]
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@@ -5047,8 +5047,8 @@ define <4 x float> @test_sqrtss(<4 x flo
; SLM-LABEL: test_sqrtss:
; SLM: # %bb.0:
; SLM-NEXT: movaps (%rdi), %xmm1 # sched: [3:1.00]
-; SLM-NEXT: sqrtss %xmm0, %xmm0 # sched: [18:1.00]
-; SLM-NEXT: sqrtss %xmm1, %xmm1 # sched: [18:1.00]
+; SLM-NEXT: sqrtss %xmm0, %xmm0 # sched: [15:1.00]
+; SLM-NEXT: sqrtss %xmm1, %xmm1 # sched: [15:1.00]
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
@@ -5135,32 +5135,32 @@ define <4 x float> @test_sqrtss(<4 x flo
; BTVER2-SSE-LABEL: test_sqrtss:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: movaps (%rdi), %xmm1 # sched: [5:1.00]
-; BTVER2-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [26:21.00]
-; BTVER2-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [26:21.00]
+; BTVER2-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [21:21.00]
+; BTVER2-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [21:21.00]
; BTVER2-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_sqrtss:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovaps (%rdi), %xmm1 # sched: [5:1.00]
-; BTVER2-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [26:21.00]
-; BTVER2-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [26:21.00]
+; BTVER2-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [21:21.00]
+; BTVER2-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [21:21.00]
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_sqrtss:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: movaps (%rdi), %xmm1 # sched: [8:0.50]
-; ZNVER1-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [27:1.00]
-; ZNVER1-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [27:1.00]
+; ZNVER1-SSE-NEXT: sqrtss %xmm0, %xmm0 # sched: [20:1.00]
+; ZNVER1-SSE-NEXT: sqrtss %xmm1, %xmm1 # sched: [20:1.00]
; ZNVER1-SSE-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
; ZNVER1-LABEL: test_sqrtss:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: vmovaps (%rdi), %xmm1 # sched: [8:0.50]
-; ZNVER1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [27:1.00]
-; ZNVER1-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [27:1.00]
+; ZNVER1-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 # sched: [20:1.00]
+; ZNVER1-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 # sched: [20:1.00]
; ZNVER1-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a0)
Modified: llvm/trunk/test/CodeGen/X86/sse2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-schedule.ll?rev=328474&r1=328473&r2=328474&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-schedule.ll Sun Mar 25 22:05:12 2018
@@ -14289,8 +14289,8 @@ define <2 x double> @test_sqrtsd(<2 x do
; SLM-LABEL: test_sqrtsd:
; SLM: # %bb.0:
; SLM-NEXT: movapd (%rdi), %xmm1 # sched: [3:1.00]
-; SLM-NEXT: sqrtsd %xmm0, %xmm0 # sched: [18:1.00]
-; SLM-NEXT: sqrtsd %xmm1, %xmm1 # sched: [18:1.00]
+; SLM-NEXT: sqrtsd %xmm0, %xmm0 # sched: [15:1.00]
+; SLM-NEXT: sqrtsd %xmm1, %xmm1 # sched: [15:1.00]
; SLM-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; SLM-NEXT: retq # sched: [4:1.00]
;
@@ -14377,32 +14377,32 @@ define <2 x double> @test_sqrtsd(<2 x do
; BTVER2-SSE-LABEL: test_sqrtsd:
; BTVER2-SSE: # %bb.0:
; BTVER2-SSE-NEXT: movapd (%rdi), %xmm1 # sched: [5:1.00]
-; BTVER2-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [26:21.00]
-; BTVER2-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [26:21.00]
+; BTVER2-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [21:21.00]
+; BTVER2-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [21:21.00]
; BTVER2-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-SSE-NEXT: retq # sched: [4:1.00]
;
; BTVER2-LABEL: test_sqrtsd:
; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovapd (%rdi), %xmm1 # sched: [5:1.00]
-; BTVER2-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [26:21.00]
-; BTVER2-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [26:21.00]
+; BTVER2-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [21:21.00]
+; BTVER2-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [21:21.00]
; BTVER2-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-SSE-LABEL: test_sqrtsd:
; ZNVER1-SSE: # %bb.0:
; ZNVER1-SSE-NEXT: movapd (%rdi), %xmm1 # sched: [8:0.50]
-; ZNVER1-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [27:1.00]
-; ZNVER1-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [27:1.00]
+; ZNVER1-SSE-NEXT: sqrtsd %xmm0, %xmm0 # sched: [20:1.00]
+; ZNVER1-SSE-NEXT: sqrtsd %xmm1, %xmm1 # sched: [20:1.00]
; ZNVER1-SSE-NEXT: addpd %xmm1, %xmm0 # sched: [3:1.00]
; ZNVER1-SSE-NEXT: retq # sched: [1:0.50]
;
; ZNVER1-LABEL: test_sqrtsd:
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: vmovapd (%rdi), %xmm1 # sched: [8:0.50]
-; ZNVER1-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [27:1.00]
-; ZNVER1-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [27:1.00]
+; ZNVER1-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0 # sched: [20:1.00]
+; ZNVER1-NEXT: vsqrtsd %xmm1, %xmm1, %xmm1 # sched: [20:1.00]
; ZNVER1-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; ZNVER1-NEXT: retq # sched: [1:0.50]
%1 = call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a0)
More information about the llvm-commits
mailing list