[llvm] r328465 - [X86] Move (v)movss to port 5 only for Skylake. Move (v)movups/d to port 015 for Skylake.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Sun Mar 25 16:40:56 PDT 2018


Author: ctopper
Date: Sun Mar 25 16:40:56 2018
New Revision: 328465

URL: http://llvm.org/viewvc/llvm-project?rev=328465&view=rev
Log:
[X86] Move (v)movss to port 5 only for Skylake. Move (v)movups/d to port 015 for Skylake.

This matches Agner's data and is consistent with what the EVEX instructions were doing on SKX.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
    llvm/trunk/test/CodeGen/X86/sse-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=328465&r1=328464&r2=328465&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Mar 25 16:40:56 2018
@@ -361,8 +361,7 @@ def: InstRW<[SKLWriteResGroup3], (instre
                                             "(V?)MOVSDrr",
                                             "(V?)MOVSHDUP(Y?)rr",
                                             "(V?)MOVSLDUP(Y?)rr",
-                                            "(V?)MOVUPD(Y?)rr",
-                                            "(V?)MOVUPS(Y?)rr",
+                                            "(V?)MOVSSrr",
                                             "(V?)PACKSSDW(Y?)rr",
                                             "(V?)PACKSSWB(Y?)rr",
                                             "(V?)PACKUSDW(Y?)rr",
@@ -566,7 +565,8 @@ def: InstRW<[SKLWriteResGroup9], (instre
                                             "(V?)MOVDQA(Y?)rr",
                                             "(V?)MOVDQU(Y?)rr",
                                             "(V?)MOVPQI2QIrr",
-                                            "(V?)MOVSSrr",
+                                            "(V?)MOVUPD(Y?)rr",
+                                            "(V?)MOVUPS(Y?)rr",
                                             "(V?)MOVZPQILo2PQIrr",
                                             "(V?)ORPD(Y?)rr",
                                             "(V?)ORPS(Y?)rr",

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328465&r1=328464&r2=328465&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Mar 25 16:40:56 2018
@@ -402,8 +402,7 @@ def: InstRW<[SKXWriteResGroup3], (instre
                                             "MOVSDrr",
                                             "MOVSHDUPrr",
                                             "MOVSLDUPrr",
-                                            "MOVUPDrr",
-                                            "MOVUPSrr",
+                                            "MOVSSrr",
                                             "PACKSSDWrr",
                                             "PACKSSWBrr",
                                             "PACKUSDWrr",
@@ -474,10 +473,7 @@ def: InstRW<[SKXWriteResGroup3], (instre
                                             "VMOVSLDUPZrr(b?)(k?)(z?)",
                                             "VMOVSLDUPrr",
                                             "VMOVSSZrr(b?)(k?)(z?)",
-                                            "VMOVUPDYrr",
-                                            "VMOVUPDrr",
-                                            "VMOVUPSYrr",
-                                            "VMOVUPSrr",
+                                            "VMOVSSrr",
                                             "VPACKSSDWYrr",
                                             "VPACKSSDWZ128rr(b?)(k?)(z?)",
                                             "VPACKSSDWZ256rr(b?)(k?)(z?)",
@@ -1045,7 +1041,8 @@ def: InstRW<[SKXWriteResGroup9], (instre
                                             "MOVDQArr",
                                             "MOVDQUrr",
                                             "MOVPQI2QIrr",
-                                            "MOVSSrr",
+                                            "MOVUPDrr",
+                                            "MOVUPSrr",
                                             "ORPDrr",
                                             "ORPSrr",
                                             "PADDBrr",
@@ -1124,13 +1121,16 @@ def: InstRW<[SKXWriteResGroup9], (instre
                                             "VMOVDQUrr",
                                             "VMOVPQI(2Q|Lo2PQ)IZrr(b?)(k?)(z?)",
                                             "VMOVPQI2QIrr",
-                                            "VMOVSSrr",
+                                            "VMOVUPDYrr",
                                             "VMOVUPDZ128rr(b?)(k?)(z?)",
                                             "VMOVUPDZ256rr(b?)(k?)(z?)",
                                             "VMOVUPDZrr(b?)(k?)(z?)",
+                                            "VMOVUPDrr",
                                             "VMOVUPSZ128rr(b?)(k?)(z?)",
                                             "VMOVUPSZ256rr(b?)(k?)(z?)",
                                             "VMOVUPSZrr(b?)(k?)(z?)",
+                                            "VMOVUPSYrr",
+                                            "VMOVUPSrr",
                                             "VMOVZPQILo2PQIrr",
                                             "VORPDYrr",
                                             "VORPDZ128rr(b?)(k?)(z?)",

Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=328465&r1=328464&r2=328465&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Sun Mar 25 16:40:56 2018
@@ -3449,7 +3449,7 @@ define <4 x float> @test_movss_reg(<4 x
 ;
 ; SKYLAKE-SSE-LABEL: test_movss_reg:
 ; SKYLAKE-SSE:       # %bb.0:
-; SKYLAKE-SSE-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.33]
+; SKYLAKE-SSE-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:1.00]
 ; SKYLAKE-SSE-NEXT:    retq # sched: [7:1.00]
 ;
 ; SKYLAKE-LABEL: test_movss_reg:
@@ -3459,7 +3459,7 @@ define <4 x float> @test_movss_reg(<4 x
 ;
 ; SKX-SSE-LABEL: test_movss_reg:
 ; SKX-SSE:       # %bb.0:
-; SKX-SSE-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:0.33]
+; SKX-SSE-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] sched: [1:1.00]
 ; SKX-SSE-NEXT:    retq # sched: [7:1.00]
 ;
 ; SKX-LABEL: test_movss_reg:




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