[llvm] r328446 - [X86] Add the ability to override memory folding latency to schedules and add 1uop for memory folds for Intel models
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 25 03:21:19 PDT 2018
Author: rksimon
Date: Sun Mar 25 03:21:19 2018
New Revision: 328446
URL: http://llvm.org/viewvc/llvm-project?rev=328446&view=rev
Log:
[X86] Add the ability to override memory folding latency to schedules and add 1uop for memory folds for Intel models
The Intel models need an extra 1uop for memory folded instructions, plus a lot of instructions take a non-default memory latency which should allow us to use the multiclass a lot more to tidy things up.
Differential Revision: https://reviews.llvm.org/D44840
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=328446&r1=328445&r2=328446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Mar 25 03:21:19 2018
@@ -80,7 +80,8 @@ def : ReadAdvance<ReadAfterLd, 5>;
// folded loads.
multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
- int Lat, list<int> Res = [1], int UOps = 1> {
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 5> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -88,12 +89,12 @@ multiclass BWWriteResPair<X86FoldableSch
let NumMicroOps = UOps;
}
- // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
- // latency.
+ // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
+ // the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
- let Latency = !add(Lat, 5);
+ let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
- let NumMicroOps = UOps;
+ let NumMicroOps = !add(UOps, 1);
}
}
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=328446&r1=328445&r2=328446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Mar 25 03:21:19 2018
@@ -81,7 +81,8 @@ def : ReadAdvance<ReadAfterLd, 5>;
// folded loads.
multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
- int Lat, list<int> Res = [1], int UOps = 1> {
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 5> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -89,12 +90,12 @@ multiclass HWWriteResPair<X86FoldableSch
let NumMicroOps = UOps;
}
- // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
- // latency.
+ // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
+ // the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> {
- let Latency = !add(Lat, 5);
+ let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
- let NumMicroOps = UOps;
+ let NumMicroOps = !add(UOps, 1);
}
}
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=328446&r1=328445&r2=328446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Mar 25 03:21:19 2018
@@ -72,7 +72,8 @@ def : ReadAdvance<ReadAfterLd, 4>;
// folded loads.
multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
- int Lat, list<int> Res = [1], int UOps = 1> {
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 4> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -80,12 +81,12 @@ multiclass SBWriteResPair<X86FoldableSch
let NumMicroOps = UOps;
}
- // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
- // latency.
+ // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
+ // the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
- let Latency = !add(Lat, 4);
+ let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
- let NumMicroOps = UOps;
+ let NumMicroOps = !add(UOps, 1);
}
}
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=328446&r1=328445&r2=328446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Mar 25 03:21:19 2018
@@ -78,7 +78,8 @@ def : ReadAdvance<ReadAfterLd, 5>;
// folded loads.
multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
- int Lat, list<int> Res = [1], int UOps = 1> {
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 5> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -86,12 +87,12 @@ multiclass SKLWriteResPair<X86FoldableSc
let NumMicroOps = UOps;
}
- // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
- // latency.
+ // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
+ // the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
- let Latency = !add(Lat, 5);
+ let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
- let NumMicroOps = UOps;
+ let NumMicroOps = !add(UOps, 1);
}
}
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328446&r1=328445&r2=328446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Mar 25 03:21:19 2018
@@ -78,7 +78,8 @@ def : ReadAdvance<ReadAfterLd, 5>;
// folded loads.
multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
- int Lat, list<int> Res = [1], int UOps = 1> {
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 5> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -86,12 +87,12 @@ multiclass SKXWriteResPair<X86FoldableSc
let NumMicroOps = UOps;
}
- // Memory variant also uses a cycle on port 2/3 and adds 5 cycles to the
- // latency.
+ // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
+ // the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
- let Latency = !add(Lat, 5);
+ let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
- let NumMicroOps = UOps;
+ let NumMicroOps = !add(UOps, 1);
}
}
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=328446&r1=328445&r2=328446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Sun Mar 25 03:21:19 2018
@@ -57,7 +57,8 @@ def : ReadAdvance<ReadAfterLd, 3>;
// folded loads.
multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
- int Lat, list<int> Res = [1], int UOps = 1> {
+ int Lat, list<int> Res = [1], int UOps = 1,
+ int LoadLat = 3> {
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
@@ -65,10 +66,10 @@ multiclass SLMWriteResPair<X86FoldableSc
let NumMicroOps = UOps;
}
- // Memory variant also uses a cycle on MEC_RSV and adds 3 cycles to the
- // latency.
+ // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to
+ // the latency (default = 3).
def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
- let Latency = !add(Lat, 3);
+ let Latency = !add(Lat, LoadLat);
let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = UOps;
}
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