Author: rksimon
Date: Sat Mar 24 13:40:14 2018
New Revision: 328435
URL: http://llvm.org/viewvc/llvm-project?rev=328435&view=rev
Log:
[X86][SkylakeClient] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
Modified:
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=328435&r1=328434&r2=328435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Mar 24 13:40:14 2018
@@ -19,7 +19,7 @@ def SkylakeClientModel : SchedMachineMod
let MicroOpBufferSize = 224; // Based on the reorder buffer.
let LoadLatency = 5;
let MispredictPenalty = 14;
-
+
// Based on the LSD (loop-stream detector) queue size and benchmarking data.
let LoopMicroOpBufferSize = 50;
@@ -103,7 +103,7 @@ def : WriteRes<WriteRMW, [SKLPort4]>;
defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op.
defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication.
def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
-def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
+def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
def : WriteRes<WriteIDiv, [SKLPort0, SKLDivider]> { // Integer division.
let Latency = 25;
let ResourceCycles = [1, 10];
@@ -343,7 +343,6 @@ def SKLWriteResGroup3 : SchedWriteRes<[S
}
def: InstRW<[SKLWriteResGroup3], (instregex "COMP_FST0r",
"COM_FST0r",
- "INSERTPSrr",
"MMX_MOVD64rr",
"MMX_MOVD64to64rr",
"MMX_PALIGNRrri",
@@ -355,147 +354,64 @@ def: InstRW<[SKLWriteResGroup3], (instre
"MMX_PUNPCKLBWirr",
"MMX_PUNPCKLDQirr",
"MMX_PUNPCKLWDirr",
- "MOV64toPQIrr",
- "MOVDDUPrr",
- "MOVDI2PDIrr",
- "MOVHLPSrr",
- "MOVLHPSrr",
- "MOVSDrr",
- "MOVSHDUPrr",
- "MOVSLDUPrr",
- "MOVUPDrr",
- "MOVUPSrr",
- "PACKSSDWrr",
- "PACKSSWBrr",
- "PACKUSDWrr",
- "PACKUSWBrr",
- "PALIGNRrri",
- "PBLENDWrri",
- "PMOVSXBDrr",
- "PMOVSXBQrr",
- "PMOVSXBWrr",
- "PMOVSXDQrr",
- "PMOVSXWDrr",
- "PMOVSXWQrr",
- "PMOVZXBDrr",
- "PMOVZXBQrr",
- "PMOVZXBWrr",
- "PMOVZXDQrr",
- "PMOVZXWDrr",
- "PMOVZXWQrr",
- "PSHUFBrr",
- "PSHUFDri",
- "PSHUFHWri",
- "PSHUFLWri",
- "PSLLDQri",
- "PSRLDQri",
- "PUNPCKHBWrr",
- "PUNPCKHDQrr",
- "PUNPCKHQDQrr",
- "PUNPCKHWDrr",
- "PUNPCKLBWrr",
- "PUNPCKLDQrr",
- "PUNPCKLQDQrr",
- "PUNPCKLWDrr",
- "SHUFPDrri",
- "SHUFPSrri",
"UCOM_FPr",
"UCOM_Fr",
- "UNPCKHPDrr",
- "UNPCKHPSrr",
- "UNPCKLPDrr",
- "UNPCKLPSrr",
"VBROADCASTSSrr",
- "VINSERTPSrr",
- "VMOV64toPQIrr",
- "VMOVDDUPYrr",
- "VMOVDDUPrr",
- "VMOVDI2PDIrr",
- "VMOVHLPSrr",
- "VMOVLHPSrr",
- "VMOVSDrr",
- "VMOVSHDUPYrr",
- "VMOVSHDUPrr",
- "VMOVSLDUPYrr",
- "VMOVSLDUPrr",
- "VMOVUPDYrr",
- "VMOVUPDrr",
- "VMOVUPSYrr",
- "VMOVUPSrr",
- "VPACKSSDWYrr",
- "VPACKSSDWrr",
- "VPACKSSWBYrr",
- "VPACKSSWBrr",
- "VPACKUSDWYrr",
- "VPACKUSDWrr",
- "VPACKUSWBYrr",
- "VPACKUSWBrr",
- "VPALIGNRYrri",
- "VPALIGNRrri",
- "VPBLENDWYrri",
- "VPBLENDWrri",
+ "(V?)INSERTPSrr",
+ "(V?)MOV64toPQIrr",
+ "(V?)MOVDDUP(Y?)rr",
+ "(V?)MOVDI2PDIrr",
+ "(V?)MOVHLPSrr",
+ "(V?)MOVLHPSrr",
+ "(V?)MOVSDrr",
+ "(V?)MOVSHDUP(Y?)rr",
+ "(V?)MOVSLDUP(Y?)rr",
+ "(V?)MOVUPD(Y?)rr",
+ "(V?)MOVUPS(Y?)rr",
+ "(V?)PACKSSDW(Y?)rr",
+ "(V?)PACKSSWB(Y?)rr",
+ "(V?)PACKUSDW(Y?)rr",
+ "(V?)PACKUSWB(Y?)rr",
+ "(V?)PALIGNR(Y?)rri",
+ "(V?)PBLENDW(Y?)rri",
"VPBROADCASTDrr",
"VPBROADCASTQrr",
- "VPERMILPDYri",
- "VPERMILPDYrr",
- "VPERMILPDri",
- "VPERMILPDrr",
- "VPERMILPSYri",
- "VPERMILPSYrr",
- "VPERMILPSri",
- "VPERMILPSrr",
- "VPMOVSXBDrr",
- "VPMOVSXBQrr",
- "VPMOVSXBWrr",
- "VPMOVSXDQrr",
- "VPMOVSXWDrr",
- "VPMOVSXWQrr",
- "VPMOVZXBDrr",
- "VPMOVZXBQrr",
- "VPMOVZXBWrr",
- "VPMOVZXDQrr",
- "VPMOVZXWDrr",
- "VPMOVZXWQrr",
- "VPSHUFBYrr",
- "VPSHUFBrr",
- "VPSHUFDYri",
- "VPSHUFDri",
- "VPSHUFHWYri",
- "VPSHUFHWri",
- "VPSHUFLWYri",
- "VPSHUFLWri",
- "VPSLLDQYri",
- "VPSLLDQri",
- "VPSRLDQYri",
- "VPSRLDQri",
- "VPUNPCKHBWYrr",
- "VPUNPCKHBWrr",
- "VPUNPCKHDQYrr",
- "VPUNPCKHDQrr",
- "VPUNPCKHQDQYrr",
- "VPUNPCKHQDQrr",
- "VPUNPCKHWDYrr",
- "VPUNPCKHWDrr",
- "VPUNPCKLBWYrr",
- "VPUNPCKLBWrr",
- "VPUNPCKLDQYrr",
- "VPUNPCKLDQrr",
- "VPUNPCKLQDQYrr",
- "VPUNPCKLQDQrr",
- "VPUNPCKLWDYrr",
- "VPUNPCKLWDrr",
- "VSHUFPDYrri",
- "VSHUFPDrri",
- "VSHUFPSYrri",
- "VSHUFPSrri",
- "VUNPCKHPDYrr",
- "VUNPCKHPDrr",
- "VUNPCKHPSYrr",
- "VUNPCKHPSrr",
- "VUNPCKLPDYrr",
- "VUNPCKLPDrr",
- "VUNPCKLPSYrr",
- "VUNPCKLPSrr")>;
+ "VPERMILPD(Y?)ri",
+ "VPERMILPD(Y?)rr",
+ "VPERMILPS(Y?)ri",
+ "VPERMILPS(Y?)rr",
+ "(V?)PMOVSXBDrr",
+ "(V?)PMOVSXBQrr",
+ "(V?)PMOVSXBWrr",
+ "(V?)PMOVSXDQrr",
+ "(V?)PMOVSXWDrr",
+ "(V?)PMOVSXWQrr",
+ "(V?)PMOVZXBDrr",
+ "(V?)PMOVZXBQrr",
+ "(V?)PMOVZXBWrr",
+ "(V?)PMOVZXDQrr",
+ "(V?)PMOVZXWDrr",
+ "(V?)PMOVZXWQrr",
+ "(V?)PSHUFB(Y?)rr",
+ "(V?)PSHUFD(Y?)ri",
+ "(V?)PSHUFHW(Y?)ri",
+ "(V?)PSHUFLW(Y?)ri",
+ "(V?)PSLLDQ(Y?)ri",
+ "(V?)PSRLDQ(Y?)ri",
+ "(V?)PUNPCKHBW(Y?)rr",
+ "(V?)PUNPCKHDQ(Y?)rr",
+ "(V?)PUNPCKHQDQ(Y?)rr",
+ "(V?)PUNPCKHWD(Y?)rr",
+ "(V?)PUNPCKLBW(Y?)rr",
+ "(V?)PUNPCKLDQ(Y?)rr",
+ "(V?)PUNPCKLQDQ(Y?)rr",
+ "(V?)PUNPCKLWD(Y?)rr",
+ "(V?)SHUFPD(Y?)rri",
+ "(V?)SHUFPS(Y?)rri",
+ "(V?)UNPCKHPD(Y?)rr",
+ "(V?)UNPCKHPS(Y?)rr",
+ "(V?)UNPCKLPD(Y?)rr",
+ "(V?)UNPCKLPS(Y?)rr")>;
def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
let Latency = 1;
@@ -509,145 +425,54 @@ def SKLWriteResGroup5 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup5], (instregex "PABSBrr",
- "PABSDrr",
- "PABSWrr",
- "PADDSBrr",
- "PADDSWrr",
- "PADDUSBrr",
- "PADDUSWrr",
- "PAVGBrr",
- "PAVGWrr",
- "PCMPEQBrr",
- "PCMPEQDrr",
- "PCMPEQQrr",
- "PCMPEQWrr",
- "PCMPGTBrr",
- "PCMPGTDrr",
- "PCMPGTWrr",
- "PMAXSBrr",
- "PMAXSDrr",
- "PMAXSWrr",
- "PMAXUBrr",
- "PMAXUDrr",
- "PMAXUWrr",
- "PMINSBrr",
- "PMINSDrr",
- "PMINSWrr",
- "PMINUBrr",
- "PMINUDrr",
- "PMINUWrr",
- "PSIGNBrr",
- "PSIGNDrr",
- "PSIGNWrr",
- "PSLLDri",
- "PSLLQri",
- "PSLLWri",
- "PSRADri",
- "PSRAWri",
- "PSRLDri",
- "PSRLQri",
- "PSRLWri",
- "PSUBSBrr",
- "PSUBSWrr",
- "PSUBUSBrr",
- "PSUBUSWrr",
- "VPABSBYrr",
- "VPABSBrr",
- "VPABSDYrr",
- "VPABSDrr",
- "VPABSWYrr",
- "VPABSWrr",
- "VPADDSBYrr",
- "VPADDSBrr",
- "VPADDSWYrr",
- "VPADDSWrr",
- "VPADDUSBYrr",
- "VPADDUSBrr",
- "VPADDUSWYrr",
- "VPADDUSWrr",
- "VPAVGBYrr",
- "VPAVGBrr",
- "VPAVGWYrr",
- "VPAVGWrr",
- "VPCMPEQBYrr",
- "VPCMPEQBrr",
- "VPCMPEQDYrr",
- "VPCMPEQDrr",
- "VPCMPEQQYrr",
- "VPCMPEQQrr",
- "VPCMPEQWYrr",
- "VPCMPEQWrr",
- "VPCMPGTBYrr",
- "VPCMPGTBrr",
- "VPCMPGTDYrr",
- "VPCMPGTDrr",
- "VPCMPGTWYrr",
- "VPCMPGTWrr",
- "VPMAXSBYrr",
- "VPMAXSBrr",
- "VPMAXSDYrr",
- "VPMAXSDrr",
- "VPMAXSWYrr",
- "VPMAXSWrr",
- "VPMAXUBYrr",
- "VPMAXUBrr",
- "VPMAXUDYrr",
- "VPMAXUDrr",
- "VPMAXUWYrr",
- "VPMAXUWrr",
- "VPMINSBYrr",
- "VPMINSBrr",
- "VPMINSDYrr",
- "VPMINSDrr",
- "VPMINSWYrr",
- "VPMINSWrr",
- "VPMINUBYrr",
- "VPMINUBrr",
- "VPMINUDYrr",
- "VPMINUDrr",
- "VPMINUWYrr",
- "VPMINUWrr",
- "VPSIGNBYrr",
- "VPSIGNBrr",
- "VPSIGNDYrr",
- "VPSIGNDrr",
- "VPSIGNWYrr",
- "VPSIGNWrr",
- "VPSLLDYri",
- "VPSLLDri",
- "VPSLLQYri",
- "VPSLLQri",
- "VPSLLVDYrr",
- "VPSLLVDrr",
- "VPSLLVQYrr",
- "VPSLLVQrr",
- "VPSLLWYri",
- "VPSLLWri",
- "VPSRADYri",
- "VPSRADri",
- "VPSRAVDYrr",
- "VPSRAVDrr",
- "VPSRAWYri",
- "VPSRAWri",
- "VPSRLDYri",
- "VPSRLDri",
- "VPSRLQYri",
- "VPSRLQri",
- "VPSRLVDYrr",
- "VPSRLVDrr",
- "VPSRLVQYrr",
- "VPSRLVQrr",
- "VPSRLWYri",
- "VPSRLWri",
- "VPSUBSBYrr",
- "VPSUBSBrr",
- "VPSUBSWYrr",
- "VPSUBSWrr",
- "VPSUBUSBYrr",
- "VPSUBUSBrr",
- "VPSUBUSWYrr",
- "VPSUBUSWrr")>;
+def: InstRW<[SKLWriteResGroup5], (instregex "(V?)PABSB(Y?)rr",
+ "(V?)PABSD(Y?)rr",
+ "(V?)PABSW(Y?)rr",
+ "(V?)PADDSB(Y?)rr",
+ "(V?)PADDSW(Y?)rr",
+ "(V?)PADDUSB(Y?)rr",
+ "(V?)PADDUSW(Y?)rr",
+ "(V?)PAVGB(Y?)rr",
+ "(V?)PAVGW(Y?)rr",
+ "(V?)PCMPEQB(Y?)rr",
+ "(V?)PCMPEQD(Y?)rr",
+ "(V?)PCMPEQQ(Y?)rr",
+ "(V?)PCMPEQW(Y?)rr",
+ "(V?)PCMPGTB(Y?)rr",
+ "(V?)PCMPGTD(Y?)rr",
+ "(V?)PCMPGTW(Y?)rr",
+ "(V?)PMAXSB(Y?)rr",
+ "(V?)PMAXSD(Y?)rr",
+ "(V?)PMAXSW(Y?)rr",
+ "(V?)PMAXUB(Y?)rr",
+ "(V?)PMAXUD(Y?)rr",
+ "(V?)PMAXUW(Y?)rr",
+ "(V?)PMINSB(Y?)rr",
+ "(V?)PMINSD(Y?)rr",
+ "(V?)PMINSW(Y?)rr",
+ "(V?)PMINUB(Y?)rr",
+ "(V?)PMINUD(Y?)rr",
+ "(V?)PMINUW(Y?)rr",
+ "(V?)PSIGNB(Y?)rr",
+ "(V?)PSIGND(Y?)rr",
+ "(V?)PSIGNW(Y?)rr",
+ "(V?)PSLLD(Y?)ri",
+ "(V?)PSLLQ(Y?)ri",
+ "VPSLLVD(Y?)rr",
+ "VPSLLVQ(Y?)rr",
+ "(V?)PSLLW(Y?)ri",
+ "(V?)PSRAD(Y?)ri",
+ "VPSRAVD(Y?)rr",
+ "(V?)PSRAW(Y?)ri",
+ "(V?)PSRLD(Y?)ri",
+ "(V?)PSRLQ(Y?)ri",
+ "VPSRLVD(Y?)rr",
+ "VPSRLVQ(Y?)rr",
+ "(V?)PSRLW(Y?)ri",
+ "(V?)PSUBSB(Y?)rr",
+ "(V?)PSUBSW(Y?)rr",
+ "(V?)PSUBUSB(Y?)rr",
+ "(V?)PSUBUSW(Y?)rr")>;
def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
let Latency = 1;
@@ -735,91 +560,36 @@ def SKLWriteResGroup9 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup9], (instregex "ANDNPDrr",
- "ANDNPSrr",
- "ANDPDrr",
- "ANDPSrr",
- "BLENDPDrri",
- "BLENDPSrri",
- "MOVAPDrr",
- "MOVAPSrr",
- "MOVDQArr",
- "MOVDQUrr",
- "MOVPQI2QIrr",
- "MOVSSrr",
- "ORPDrr",
- "ORPSrr",
- "PADDBrr",
- "PADDDrr",
- "PADDQrr",
- "PADDWrr",
- "PANDNrr",
- "PANDrr",
- "PORrr",
- "PSUBBrr",
- "PSUBDrr",
- "PSUBQrr",
- "PSUBWrr",
- "PXORrr",
- "VANDNPDYrr",
- "VANDNPDrr",
- "VANDNPSYrr",
- "VANDNPSrr",
- "VANDPDYrr",
- "VANDPDrr",
- "VANDPSYrr",
- "VANDPSrr",
- "VBLENDPDYrri",
- "VBLENDPDrri",
- "VBLENDPSYrri",
- "VBLENDPSrri",
- "VMOVAPDYrr",
- "VMOVAPDrr",
- "VMOVAPSYrr",
- "VMOVAPSrr",
- "VMOVDQAYrr",
- "VMOVDQArr",
- "VMOVDQUYrr",
- "VMOVDQUrr",
- "VMOVPQI2QIrr",
- "VMOVSSrr",
- "VMOVZPQILo2PQIrr",
- "VORPDYrr",
- "VORPDrr",
- "VORPSYrr",
- "VORPSrr",
- "VPADDBYrr",
- "VPADDBrr",
- "VPADDDYrr",
- "VPADDDrr",
- "VPADDQYrr",
- "VPADDQrr",
- "VPADDWYrr",
- "VPADDWrr",
- "VPANDNYrr",
- "VPANDNrr",
- "VPANDYrr",
- "VPANDrr",
- "VPBLENDDYrri",
- "VPBLENDDrri",
- "VPORYrr",
- "VPORrr",
- "VPSUBBYrr",
- "VPSUBBrr",
- "VPSUBDYrr",
- "VPSUBDrr",
- "VPSUBQYrr",
- "VPSUBQrr",
- "VPSUBWYrr",
- "VPSUBWrr",
- "VPXORYrr",
- "VPXORrr",
- "VXORPDYrr",
- "VXORPDrr",
- "VXORPSYrr",
- "VXORPSrr",
- "XORPDrr",
- "XORPSrr")>;
+def: InstRW<[SKLWriteResGroup9], (instregex "(V?)ANDNPD(Y?)rr",
+ "(V?)ANDNPS(Y?)rr",
+ "(V?)ANDPD(Y?)rr",
+ "(V?)ANDPS(Y?)rr",
+ "(V?)BLENDPD(Y?)rri",
+ "(V?)BLENDPS(Y?)rri",
+ "(V?)MOVAPD(Y?)rr",
+ "(V?)MOVAPS(Y?)rr",
+ "(V?)MOVDQA(Y?)rr",
+ "(V?)MOVDQU(Y?)rr",
+ "(V?)MOVPQI2QIrr",
+ "(V?)MOVSSrr",
+ "(V?)MOVZPQILo2PQIrr",
+ "(V?)ORPD(Y?)rr",
+ "(V?)ORPS(Y?)rr",
+ "(V?)PADDB(Y?)rr",
+ "(V?)PADDD(Y?)rr",
+ "(V?)PADDQ(Y?)rr",
+ "(V?)PADDW(Y?)rr",
+ "(V?)PANDN(Y?)rr",
+ "(V?)PAND(Y?)rr",
+ "VPBLENDD(Y?)rri",
+ "(V?)POR(Y?)rr",
+ "(V?)PSUBB(Y?)rr",
+ "(V?)PSUBD(Y?)rr",
+ "(V?)PSUBQ(Y?)rr",
+ "(V?)PSUBW(Y?)rr",
+ "(V?)PXOR(Y?)rr",
+ "(V?)XORPD(Y?)rr"
+ "(V?)XORPS(Y?)rr")>;
def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let Latency = 1;
@@ -886,58 +656,31 @@ def: InstRW<[SKLWriteResGroup11], (instr
"MMX_MOVQ64mr",
"MOV(8|16|32|64)mr",
"MOV8mi",
- "MOVAPDmr",
- "MOVAPSmr",
- "MOVDQAmr",
- "MOVDQUmr",
- "MOVHPDmr",
- "MOVHPSmr",
- "MOVLPDmr",
- "MOVLPSmr",
- "MOVNTDQmr",
"MOVNTI_64mr",
"MOVNTImr",
- "MOVNTPDmr",
- "MOVNTPSmr",
- "MOVPDI2DImr",
- "MOVPQI2QImr",
- "MOVPQIto64mr",
- "MOVSDmr",
- "MOVSSmr",
- "MOVUPDmr",
- "MOVUPSmr",
"ST_FP32m",
"ST_FP64m",
"ST_FP80m",
"VEXTRACTF128mr",
"VEXTRACTI128mr",
- "VMOVAPDYmr",
- "VMOVAPDmr",
- "VMOVAPSYmr",
- "VMOVAPSmr",
- "VMOVDQAYmr",
- "VMOVDQAmr",
- "VMOVDQUYmr",
- "VMOVDQUmr",
- "VMOVHPDmr",
- "VMOVHPSmr",
- "VMOVLPDmr",
- "VMOVLPSmr",
- "VMOVNTDQYmr",
- "VMOVNTDQmr",
- "VMOVNTPDYmr",
- "VMOVNTPDmr",
- "VMOVNTPSYmr",
- "VMOVNTPSmr",
- "VMOVPDI2DImr",
- "VMOVPQI2QImr",
- "VMOVPQIto64mr",
- "VMOVSDmr",
- "VMOVSSmr",
- "VMOVUPDYmr",
- "VMOVUPDmr",
- "VMOVUPSYmr",
- "VMOVUPSmr",
+ "(Y?)MOVAPDYmr",
+ "(Y?)MOVAPS(Y?)mr",
+ "(Y?)MOVDQA(Y?)mr",
+ "(Y?)MOVDQU(Y?)mr",
+ "(Y?)MOVHPDmr",
+ "(Y?)MOVHPSmr",
+ "(Y?)MOVLPDmr",
+ "(Y?)MOVLPSmr",
+ "(Y?)MOVNTDQ(Y?)mr",
+ "(Y?)MOVNTPD(Y?)mr",
+ "(Y?)MOVNTPS(Y?)mr",
+ "(Y?)MOVPDI2DImr",
+ "(Y?)MOVPQI2QImr",
+ "(Y?)MOVPQIto64mr",
+ "(Y?)MOVSDmr",
+ "(Y?)MOVSSmr",
+ "(Y?)MOVUPD(Y?)mr",
+ "(Y?)MOVUPS(Y?)mr",
"VMPTRSTm")>;
def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
@@ -945,34 +688,20 @@ def SKLWriteResGroup12 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup12], (instregex "COMISDrr",
- "COMISSrr",
- "MMX_MOVD64from64rr",
+def: InstRW<[SKLWriteResGroup12], (instregex "MMX_MOVD64from64rr",
"MMX_MOVD64grr",
"MMX_PMOVMSKBrr",
- "MOVMSKPDrr",
- "MOVMSKPSrr",
- "MOVPDI2DIrr",
- "MOVPQIto64rr",
- "PMOVMSKBrr",
- "UCOMISDrr",
- "UCOMISSrr",
- "VCOMISDrr",
- "VCOMISSrr",
- "VMOVMSKPDYrr",
- "VMOVMSKPDrr",
- "VMOVMSKPSYrr",
- "VMOVMSKPSrr",
- "VMOVPDI2DIrr",
- "VMOVPQIto64rr",
- "VPMOVMSKBYrr",
- "VPMOVMSKBrr",
- "VTESTPDYrr",
- "VTESTPDrr",
- "VTESTPSYrr",
- "VTESTPSrr",
- "VUCOMISDrr",
- "VUCOMISSrr")>;
+ "(V?)COMISDrr",
+ "(V?)COMISSrr",
+ "(V?)MOVMSKPD(Y?)rr",
+ "(V?)MOVMSKPS(Y?)rr",
+ "(V?)MOVPDI2DIrr",
+ "(V?)MOVPQIto64rr",
+ "(V?)PMOVMSKB(Y?)rr",
+ "VTESTPD(Y?)rr",
+ "VTESTPS(Y?)rr",
+ "(V?)UCOMISDrr",
+ "(V?)UCOMISSrr")>;
def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
let Latency = 2;
@@ -981,14 +710,10 @@ def SKLWriteResGroup13 : SchedWriteRes<[
}
def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr",
"MMX_PINSRWrr",
- "PINSRBrr",
- "PINSRDrr",
- "PINSRQrr",
- "PINSRWrr",
- "VPINSRBrr",
- "VPINSRDrr",
- "VPINSRQrr",
- "VPINSRWrr")>;
+ "(V?)PINSRBrr",
+ "(V?)PINSRDrr",
+ "(V?)PINSRQrr",
+ "(V?)PINSRWrr")>;
def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
let Latency = 2;
@@ -1018,12 +743,9 @@ def SKLWriteResGroup16 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup16], (instregex "BLENDVPDrr0",
"BLENDVPSrr0",
"PBLENDVBrr0",
- "VBLENDVPDYrr",
- "VBLENDVPDrr",
- "VBLENDVPSYrr",
- "VBLENDVPSrr",
- "VPBLENDVBYrr",
- "VPBLENDVBrr")>;
+ "VBLENDVPD(Y?)rr",
+ "VBLENDVPS(Y?)rr",
+ "VPBLENDVB(Y?)rr")>;
def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
let Latency = 2;
@@ -1039,36 +761,24 @@ def SKLWriteResGroup18 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPDYmr",
- "VMASKMOVPDmr",
- "VMASKMOVPSYmr",
- "VMASKMOVPSmr",
- "VPMASKMOVDYmr",
- "VPMASKMOVDmr",
- "VPMASKMOVQYmr",
- "VPMASKMOVQmr")>;
+def: InstRW<[SKLWriteResGroup18], (instregex "VMASKMOVPD(Y?)mr",
+ "VMASKMOVPS(Y?)mr",
+ "VPMASKMOVD(Y?)mr",
+ "VPMASKMOVQ(Y?)mr")>;
def SKLWriteResGroup19 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 2;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup19], (instregex "PSLLDrr",
- "PSLLQrr",
- "PSLLWrr",
- "PSRADrr",
- "PSRAWrr",
- "PSRLDrr",
- "PSRLQrr",
- "PSRLWrr",
- "VPSLLDrr",
- "VPSLLQrr",
- "VPSLLWrr",
- "VPSRADrr",
- "VPSRAWrr",
- "VPSRLDrr",
- "VPSRLQrr",
- "VPSRLWrr")>;
+def: InstRW<[SKLWriteResGroup19], (instregex "(V?)PSLLDrr",
+ "(V?)PSLLQrr",
+ "(V?)PSLLWrr",
+ "(V?)PSRADrr",
+ "(V?)PSRAWrr",
+ "(V?)PSRLDrr",
+ "(V?)PSRLQrr",
+ "(V?)PSRLWrr")>;
def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 2;
@@ -1109,18 +819,12 @@ def SKLWriteResGroup24 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup24], (instregex "EXTRACTPSmr",
- "PEXTRBmr",
- "PEXTRDmr",
- "PEXTRQmr",
- "PEXTRWmr",
- "STMXCSR",
- "VEXTRACTPSmr",
- "VPEXTRBmr",
- "VPEXTRDmr",
- "VPEXTRQmr",
- "VPEXTRWmr",
- "VSTMXCSR")>;
+def: InstRW<[SKLWriteResGroup24], (instregex "(V?)EXTRACTPSmr",
+ "(V?)PEXTRBmr",
+ "(V?)PEXTRDmr",
+ "(V?)PEXTRQmr",
+ "(V?)PEXTRWmr",
+ "(V?)STMXCSR")>;
def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
let Latency = 2;
@@ -1189,8 +893,6 @@ def: InstRW<[SKLWriteResGroup30], (instr
"ADD_FST0r",
"ADD_FrST0",
"MMX_PSADBWirr",
- "PCMPGTQrr",
- "PSADBWrr",
"SUBR_FPrST0",
"SUBR_FST0r",
"SUBR_FrST0",
@@ -1203,14 +905,11 @@ def: InstRW<[SKLWriteResGroup30], (instr
"VEXTRACTI128rr",
"VINSERTF128rr",
"VINSERTI128rr",
- "VPBROADCASTBYrr",
- "VPBROADCASTBrr",
+ "VPBROADCASTB(Y?)rr",
"VPBROADCASTDYrr",
"VPBROADCASTQYrr",
- "VPBROADCASTWYrr",
- "VPBROADCASTWrr",
- "VPCMPGTQYrr",
- "VPCMPGTQrr",
+ "VPBROADCASTW(Y?)rr",
+ "(V?)PCMPGTQ(Y?)rr",
"VPERM2F128rr",
"VPERM2I128rr",
"VPERMDYrr",
@@ -1229,28 +928,20 @@ def: InstRW<[SKLWriteResGroup30], (instr
"VPMOVZXDQYrr",
"VPMOVZXWDYrr",
"VPMOVZXWQYrr",
- "VPSADBWYrr",
- "VPSADBWrr")>;
+ "(V?)PSADBW(Y?)rr")>;
def SKLWriteResGroup31 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 3;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup31], (instregex "EXTRACTPSrr",
- "MMX_PEXTRWrr",
- "PEXTRBrr",
- "PEXTRDrr",
- "PEXTRQrr",
- "PEXTRWrr",
- "PTESTrr",
- "VEXTRACTPSrr",
- "VPEXTRBrr",
- "VPEXTRDrr",
- "VPEXTRQrr",
- "VPEXTRWrr",
- "VPTESTYrr",
- "VPTESTrr")>;
+def: InstRW<[SKLWriteResGroup31], (instregex "MMX_PEXTRWrr",
+ "(V?)EXTRACTPSrr",
+ "(V?)PEXTRBrr",
+ "(V?)PEXTRDrr",
+ "(V?)PEXTRQrr",
+ "(V?)PEXTRWrr",
+ "(V?)PTEST(Y?)rr")>;
def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
let Latency = 3;
@@ -1291,12 +982,8 @@ def SKLWriteResGroup36 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup36], (instregex "PHADDSWrr",
- "PHSUBSWrr",
- "VPHADDSWrr",
- "VPHADDSWYrr",
- "VPHSUBSWrr",
- "VPHSUBSWYrr")>;
+def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
+ "(V?)PHSUBSW(Y?)rr")>;
def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {
let Latency = 3;
@@ -1313,18 +1000,10 @@ def SKLWriteResGroup38 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup38], (instregex "PHADDDrr",
- "PHADDWrr",
- "PHSUBDrr",
- "PHSUBWrr",
- "VPHADDDYrr",
- "VPHADDDrr",
- "VPHADDWYrr",
- "VPHADDWrr",
- "VPHSUBDYrr",
- "VPHSUBDrr",
- "VPHSUBWYrr",
- "VPHSUBWrr")>;
+def: InstRW<[SKLWriteResGroup38], (instregex "(V?)PHADDD(Y?)rr",
+ "(V?)PHADDW(Y?)rr",
+ "(V?)PHSUBD(Y?)rr",
+ "(V?)PHSUBW(Y?)rr")>;
def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
let Latency = 3;
@@ -1402,123 +1081,54 @@ def: InstRW<[SKLWriteResGroup47], (instr
"MUL_FPrST0",
"MUL_FST0r",
"MUL_FrST0",
- "RCPPSr",
- "RCPSSr",
- "RSQRTPSr",
- "RSQRTSSr",
- "VRCPPSYr",
- "VRCPPSr",
- "VRCPSSr",
- "VRSQRTPSYr",
- "VRSQRTPSr",
- "VRSQRTSSr")>;
+ "(V?)RCPPS(Y?)r",
+ "(V?)RCPSSr",
+ "(V?)RSQRTPS(Y?)r",
+ "(V?)RSQRTSSr")>;
def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
let Latency = 4;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup48], (instregex "ADDPDrr",
- "ADDPSrr",
- "ADDSDrr",
- "ADDSSrr",
- "ADDSUBPDrr",
- "ADDSUBPSrr",
- "CMPPDrri",
- "CMPPSrri",
- "CMPSDrr",
- "CMPSSrr",
- "CVTDQ2PSrr",
- "CVTPS2DQrr",
- "CVTTPS2DQrr",
- "MAX(C?)PDrr",
- "MAX(C?)PSrr",
- "MAX(C?)SDrr",
- "MAX(C?)SSrr",
- "MIN(C?)PDrr",
- "MIN(C?)PSrr",
- "MIN(C?)SDrr",
- "MIN(C?)SSrr",
- "MULPDrr",
- "MULPSrr",
- "MULSDrr",
- "MULSSrr",
- "PHMINPOSUWrr",
- "PMADDUBSWrr",
- "PMADDWDrr",
- "PMULDQrr",
- "PMULHRSWrr",
- "PMULHUWrr",
- "PMULHWrr",
- "PMULLWrr",
- "PMULUDQrr",
- "SUBPDrr",
- "SUBPSrr",
- "SUBSDrr",
- "SUBSSrr",
- "VADDPDYrr",
- "VADDPDrr",
- "VADDPSYrr",
- "VADDPSrr",
- "VADDSDrr",
- "VADDSSrr",
- "VADDSUBPDYrr",
- "VADDSUBPDrr",
- "VADDSUBPSYrr",
- "VADDSUBPSrr",
- "VCMPPDYrri",
- "VCMPPDrri",
- "VCMPPSYrri",
- "VCMPPSrri",
- "VCMPSDrr",
- "VCMPSSrr",
- "VCVTDQ2PSYrr",
- "VCVTDQ2PSrr",
- "VCVTPS2DQYrr",
- "VCVTPS2DQrr",
- "VCVTTPS2DQYrr",
- "VCVTTPS2DQrr",
- "VMAX(C?)PDYrr",
- "VMAX(C?)PDrr",
- "VMAX(C?)PSYrr",
- "VMAX(C?)PSrr",
- "VMAX(C?)SDrr",
- "VMAX(C?)SSrr",
- "VMIN(C?)PDYrr",
- "VMIN(C?)PDrr",
- "VMIN(C?)PSYrr",
- "VMIN(C?)PSrr",
- "VMIN(C?)SDrr",
- "VMIN(C?)SSrr",
- "VMULPDYrr",
- "VMULPDrr",
- "VMULPSYrr",
- "VMULPSrr",
- "VMULSDrr",
- "VMULSSrr",
- "VPHMINPOSUWrr",
- "VPMADDUBSWYrr",
- "VPMADDUBSWrr",
- "VPMADDWDYrr",
- "VPMADDWDrr",
- "VPMULDQYrr",
- "VPMULDQrr",
- "VPMULHRSWYrr",
- "VPMULHRSWrr",
- "VPMULHUWYrr",
- "VPMULHUWrr",
- "VPMULHWYrr",
- "VPMULHWrr",
- "VPMULLWYrr",
- "VPMULLWrr",
- "VPMULUDQYrr",
- "VPMULUDQrr",
- "VSUBPDYrr",
- "VSUBPDrr",
- "VSUBPSYrr",
- "VSUBPSrr",
- "VSUBSDrr",
- "VSUBSSrr")>;
+def: InstRW<[SKLWriteResGroup48], (instregex "(V?)ADDPD(Y?)rr",
+ "(V?)ADDPS(Y?)rr",
+ "(V?)ADDSDrr",
+ "(V?)ADDSSrr",
+ "(V?)ADDSUBPD(Y?)rr",
+ "(V?)ADDSUBPS(Y?)rr",
+ "(V?)CMPPD(Y?)rri",
+ "(V?)CMPPS(Y?)rri",
+ "(V?)CMPSDrr",
+ "(V?)CMPSSrr",
+ "(V?)CVTDQ2PS(Y?)rr",
+ "(V?)CVTPS2DQ(Y?)rr",
+ "(V?)CVTTPS2DQ(Y?)rr",
+ "(V?)MAX(C?)PD(Y?)rr",
+ "(V?)MAX(C?)PS(Y?)rr",
+ "(V?)MAX(C?)SDrr",
+ "(V?)MAX(C?)SSrr",
+ "(V?)MIN(C?)PD(Y?)rr",
+ "(V?)MIN(C?)PS(Y?)rr",
+ "(V?)MIN(C?)SDrr",
+ "(V?)MIN(C?)SSrr",
+ "(V?)MULPD(Y?)rr",
+ "(V?)MULPS(Y?)rr",
+ "(V?)MULSDrr",
+ "(V?)MULSSrr",
+ "(V?)PHMINPOSUWrr",
+ "(V?)PMADDUBSW(Y?)rr",
+ "(V?)PMADDWD(Y?)rr",
+ "(V?)PMULDQ(Y?)rr",
+ "(V?)PMULHRSW(Y?)rr",
+ "(V?)PMULHUW(Y?)rr",
+ "(V?)PMULHW(Y?)rr",
+ "(V?)PMULLW(Y?)rr",
+ "(V?)PMULUDQ(Y?)rr",
+ "(V?)SUBPD(Y?)rr",
+ "(V?)SUBPS(Y?)rr",
+ "(V?)SUBSDrr",
+ "(V?)SUBSSrr")>;
def: InstRW<[SKLWriteResGroup48],
(instregex
"VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
@@ -1529,9 +1139,7 @@ def SKLWriteResGroup50 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup50], (instregex "MPSADBWrri",
- "VMPSADBWYrri",
- "VMPSADBWrri")>;
+def: InstRW<[SKLWriteResGroup50], (instregex "(V?)MPSADBW(Y?)rri")>;
def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
let Latency = 4;
@@ -1612,12 +1220,6 @@ def: InstRW<[SKLWriteResGroup58], (instr
"MMX_MOVD64to64rm",
"MMX_MOVQ64rm",
"MOV(8|16|32|64)rm",
- "MOV64toPQIrm",
- "MOVDDUPrm",
- "MOVDI2PDIrm",
- "MOVQI2PQIrm",
- "MOVSDrm",
- "MOVSSrm",
"MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
@@ -1627,51 +1229,41 @@ def: InstRW<[SKLWriteResGroup58], (instr
"PREFETCHT0",
"PREFETCHT1",
"PREFETCHT2",
- "VMOV64toPQIrm",
- "VMOVDDUPrm",
- "VMOVDI2PDIrm",
- "VMOVQI2PQIrm",
- "VMOVSDrm",
- "VMOVSSrm")>;
+ "(V?)MOV64toPQIrm",
+ "(V?)MOVDDUPrm",
+ "(V?)MOVDI2PDIrm",
+ "(V?)MOVQI2PQIrm",
+ "(V?)MOVSDrm",
+ "(V?)MOVSSrm")>;
def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup59], (instregex "CVTDQ2PDrr",
- "MMX_CVTPI2PDirr",
- "VCVTDQ2PDrr")>;
+def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr",
+ "(V?)CVTDQ2PDrr")>;
def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 5;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup60], (instregex "CVTPD2DQrr",
- "CVTPD2PSrr",
- "CVTPS2PDrr",
- "CVTSD2SSrr",
- "CVTSI642SDrr",
- "CVTSI2SDrr",
- "CVTSI2SSrr",
- "CVTSS2SDrr",
- "CVTTPD2DQrr",
- "MMX_CVTPD2PIirr",
+def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVTPD2PIirr",
"MMX_CVTPS2PIirr",
"MMX_CVTTPD2PIirr",
"MMX_CVTTPS2PIirr",
- "VCVTPD2DQrr",
- "VCVTPD2PSrr",
+ "(V?)CVTPD2DQrr",
+ "(V?)CVTPD2PSrr",
"VCVTPH2PSrr",
- "VCVTPS2PDrr",
+ "(V?)CVTPS2PDrr",
"VCVTPS2PHrr",
- "VCVTSD2SSrr",
- "VCVTSI642SDrr",
- "VCVTSI2SDrr",
- "VCVTSI2SSrr",
- "VCVTSS2SDrr",
- "VCVTTPD2DQrr")>;
+ "(V?)CVTSD2SSrr",
+ "(V?)CVTSI642SDrr",
+ "(V?)CVTSI2SDrr",
+ "(V?)CVTSI2SSrr",
+ "(V?)CVTSS2SDrr",
+ "(V?)CVTTPD2DQrr")>;
def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
let Latency = 5;
@@ -1714,27 +1306,17 @@ def SKLWriteResGroup67 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup67], (instregex "LDDQUrm",
- "MOVAPDrm",
- "MOVAPSrm",
- "MOVDQArm",
- "MOVDQUrm",
- "MOVNTDQArm",
- "MOVSHDUPrm",
- "MOVSLDUPrm",
- "MOVUPDrm",
- "MOVUPSrm",
- "VBROADCASTSSrm",
- "VLDDQUrm",
- "VMOVAPDrm",
- "VMOVAPSrm",
- "VMOVDQArm",
- "VMOVDQUrm",
- "VMOVNTDQArm",
- "VMOVSHDUPrm",
- "VMOVSLDUPrm",
- "VMOVUPDrm",
- "VMOVUPSrm",
+def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm",
+ "(V?)LDDQUrm",
+ "(V?)MOVAPDrm",
+ "(V?)MOVAPSrm",
+ "(V?)MOVDQArm",
+ "(V?)MOVDQUrm",
+ "(V?)MOVNTDQArm",
+ "(V?)MOVSHDUPrm",
+ "(V?)MOVSLDUPrm",
+ "(V?)MOVUPDrm",
+ "(V?)MOVUPSrm",
"VPBROADCASTDrm",
"VPBROADCASTQrm")>;
@@ -1784,18 +1366,12 @@ def SKLWriteResGroup70 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup70], (instregex "CVTSD2SI64rr",
- "CVTSD2SIrr",
- "CVTSS2SI64rr",
- "CVTSS2SIrr",
- "CVTTSD2SI64rr",
- "CVTTSD2SIrr",
- "VCVTSD2SI64rr",
- "VCVTSD2SIrr",
- "VCVTSS2SI64rr",
- "VCVTSS2SIrr",
- "VCVTTSD2SI64rr",
- "VCVTTSD2SIrr")>;
+def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSD2SI64rr",
+ "(V?)CVTSD2SIrr",
+ "(V?)CVTSS2SI64rr",
+ "(V?)CVTSS2SIrr",
+ "(V?)CVTTSD2SI64rr",
+ "(V?)CVTTSD2SIrr")>;
def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 6;
@@ -1812,46 +1388,26 @@ def: InstRW<[SKLWriteResGroup71], (instr
"MMX_PUNPCKLBWirm",
"MMX_PUNPCKLDQirm",
"MMX_PUNPCKLWDirm",
- "MOVHPDrm",
- "MOVHPSrm",
- "MOVLPDrm",
- "MOVLPSrm",
- "PINSRBrm",
- "PINSRDrm",
- "PINSRQrm",
- "PINSRWrm",
- "PMOVSXBDrm",
- "PMOVSXBQrm",
- "PMOVSXBWrm",
- "PMOVSXDQrm",
- "PMOVSXWDrm",
- "PMOVSXWQrm",
- "PMOVZXBDrm",
- "PMOVZXBQrm",
- "PMOVZXBWrm",
- "PMOVZXDQrm",
- "PMOVZXWDrm",
- "PMOVZXWQrm",
- "VMOVHPDrm",
- "VMOVHPSrm",
- "VMOVLPDrm",
- "VMOVLPSrm",
- "VPINSRBrm",
- "VPINSRDrm",
- "VPINSRQrm",
- "VPINSRWrm",
- "VPMOVSXBDrm",
- "VPMOVSXBQrm",
- "VPMOVSXBWrm",
- "VPMOVSXDQrm",
- "VPMOVSXWDrm",
- "VPMOVSXWQrm",
- "VPMOVZXBDrm",
- "VPMOVZXBQrm",
- "VPMOVZXBWrm",
- "VPMOVZXDQrm",
- "VPMOVZXWDrm",
- "VPMOVZXWQrm")>;
+ "(V?)MOVHPDrm",
+ "(V?)MOVHPSrm",
+ "(V?)MOVLPDrm",
+ "(V?)MOVLPSrm",
+ "(V?)PINSRBrm",
+ "(V?)PINSRDrm",
+ "(V?)PINSRQrm",
+ "(V?)PINSRWrm",
+ "(V?)PMOVSXBDrm",
+ "(V?)PMOVSXBQrm",
+ "(V?)PMOVSXBWrm",
+ "(V?)PMOVSXDQrm",
+ "(V?)PMOVSXWDrm",
+ "(V?)PMOVSXWQrm",
+ "(V?)PMOVZXBDrm",
+ "(V?)PMOVZXBQrm",
+ "(V?)PMOVZXBWrm",
+ "(V?)PMOVZXDQrm",
+ "(V?)PMOVZXWDrm",
+ "(V?)PMOVZXWQrm")>;
def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
let Latency = 6;
@@ -1936,18 +1492,10 @@ def SKLWriteResGroup77 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup77], (instregex "HADDPDrr",
- "HADDPSrr",
- "HSUBPDrr",
- "HSUBPSrr",
- "VHADDPDYrr",
- "VHADDPDrr",
- "VHADDPSYrr",
- "VHADDPSrr",
- "VHSUBPDYrr",
- "VHSUBPDrr",
- "VHSUBPSYrr",
- "VHSUBPSrr")>;
+def: InstRW<[SKLWriteResGroup77], (instregex "(V?)HADDPD(Y?)rr",
+ "(V?)HADDPS(Y?)rr",
+ "(V?)HSUBPD(Y?)rr",
+ "(V?)HSUBPS(Y?)rr")>;
def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 6;
@@ -2060,76 +1608,47 @@ def SKLWriteResGroup87 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup87], (instregex "COMISDrm",
- "COMISSrm",
- "UCOMISDrm",
- "UCOMISSrm",
- "VCOMISDrm",
- "VCOMISSrm",
- "VUCOMISDrm",
- "VUCOMISSrm")>;
+def: InstRW<[SKLWriteResGroup87], (instregex "(V?)COMISDrm",
+ "(V?)COMISSrm",
+ "(V?)UCOMISDrm",
+ "(V?)UCOMISSrm")>;
def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup88], (instregex "INSERTPSrm",
- "PACKSSDWrm",
- "PACKSSWBrm",
- "PACKUSDWrm",
- "PACKUSWBrm",
- "PALIGNRrmi",
- "PBLENDWrmi",
- "PSHUFBrm",
- "PSHUFDmi",
- "PSHUFHWmi",
- "PSHUFLWmi",
- "PUNPCKHBWrm",
- "PUNPCKHDQrm",
- "PUNPCKHQDQrm",
- "PUNPCKHWDrm",
- "PUNPCKLBWrm",
- "PUNPCKLDQrm",
- "PUNPCKLQDQrm",
- "PUNPCKLWDrm",
- "SHUFPDrmi",
- "SHUFPSrmi",
- "UNPCKHPDrm",
- "UNPCKHPSrm",
- "UNPCKLPDrm",
- "UNPCKLPSrm",
- "VINSERTPSrm",
- "VPACKSSDWrm",
- "VPACKSSWBrm",
- "VPACKUSDWrm",
- "VPACKUSWBrm",
- "VPALIGNRrmi",
- "VPBLENDWrmi",
+def: InstRW<[SKLWriteResGroup88], (instregex "(V?)INSERTPSrm",
+ "(V?)PACKSSDWrm",
+ "(V?)PACKSSWBrm",
+ "(V?)PACKUSDWrm",
+ "(V?)PACKUSWBrm",
+ "(V?)PALIGNRrmi",
+ "(V?)PBLENDWrmi",
"VPBROADCASTBrm",
"VPBROADCASTWrm",
"VPERMILPDmi",
"VPERMILPDrm",
"VPERMILPSmi",
"VPERMILPSrm",
- "VPSHUFBrm",
- "VPSHUFDmi",
- "VPSHUFHWmi",
- "VPSHUFLWmi",
- "VPUNPCKHBWrm",
- "VPUNPCKHDQrm",
- "VPUNPCKHQDQrm",
- "VPUNPCKHWDrm",
- "VPUNPCKLBWrm",
- "VPUNPCKLDQrm",
- "VPUNPCKLQDQrm",
- "VPUNPCKLWDrm",
- "VSHUFPDrmi",
- "VSHUFPSrmi",
- "VUNPCKHPDrm",
- "VUNPCKHPSrm",
- "VUNPCKLPDrm",
- "VUNPCKLPSrm")>;
+ "(V?)PSHUFBrm",
+ "(V?)PSHUFDmi",
+ "(V?)PSHUFHWmi",
+ "(V?)PSHUFLWmi",
+ "(V?)PUNPCKHBWrm",
+ "(V?)PUNPCKHDQrm",
+ "(V?)PUNPCKHQDQrm",
+ "(V?)PUNPCKHWDrm",
+ "(V?)PUNPCKLBWrm",
+ "(V?)PUNPCKLDQrm",
+ "(V?)PUNPCKLQDQrm",
+ "(V?)PUNPCKLWDrm",
+ "(V?)SHUFPDrmi",
+ "(V?)SHUFPSrmi",
+ "(V?)UNPCKHPDrm",
+ "(V?)UNPCKHPSrm",
+ "(V?)UNPCKLPDrm",
+ "(V?)UNPCKLPSrm")>;
def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 7;
@@ -2148,154 +1667,89 @@ def SKLWriteResGroup90 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup90], (instregex "PABSBrm",
- "PABSDrm",
- "PABSWrm",
- "PADDSBrm",
- "PADDSWrm",
- "PADDUSBrm",
- "PADDUSWrm",
- "PAVGBrm",
- "PAVGWrm",
- "PCMPEQBrm",
- "PCMPEQDrm",
- "PCMPEQQrm",
- "PCMPEQWrm",
- "PCMPGTBrm",
- "PCMPGTDrm",
- "PCMPGTWrm",
- "PMAXSBrm",
- "PMAXSDrm",
- "PMAXSWrm",
- "PMAXUBrm",
- "PMAXUDrm",
- "PMAXUWrm",
- "PMINSBrm",
- "PMINSDrm",
- "PMINSWrm",
- "PMINUBrm",
- "PMINUDrm",
- "PMINUWrm",
- "PSIGNBrm",
- "PSIGNDrm",
- "PSIGNWrm",
- "PSLLDrm",
- "PSLLQrm",
- "PSLLWrm",
- "PSRADrm",
- "PSRAWrm",
- "PSRLDrm",
- "PSRLQrm",
- "PSRLWrm",
- "PSUBSBrm",
- "PSUBSWrm",
- "PSUBUSBrm",
- "PSUBUSWrm",
- "VPABSBrm",
- "VPABSDrm",
- "VPABSWrm",
- "VPADDSBrm",
- "VPADDSWrm",
- "VPADDUSBrm",
- "VPADDUSWrm",
- "VPAVGBrm",
- "VPAVGWrm",
- "VPCMPEQBrm",
- "VPCMPEQDrm",
- "VPCMPEQQrm",
- "VPCMPEQWrm",
- "VPCMPGTBrm",
- "VPCMPGTDrm",
- "VPCMPGTWrm",
- "VPMAXSBrm",
- "VPMAXSDrm",
- "VPMAXSWrm",
- "VPMAXUBrm",
- "VPMAXUDrm",
- "VPMAXUWrm",
- "VPMINSBrm",
- "VPMINSDrm",
- "VPMINSWrm",
- "VPMINUBrm",
- "VPMINUDrm",
- "VPMINUWrm",
- "VPSIGNBrm",
- "VPSIGNDrm",
- "VPSIGNWrm",
- "VPSLLDrm",
- "VPSLLQrm",
+def: InstRW<[SKLWriteResGroup90], (instregex "(V?)PABSBrm",
+ "(V?)PABSDrm",
+ "(V?)PABSWrm",
+ "(V?)PADDSBrm",
+ "(V?)PADDSWrm",
+ "(V?)PADDUSBrm",
+ "(V?)PADDUSWrm",
+ "(V?)PAVGBrm",
+ "(V?)PAVGWrm",
+ "(V?)PCMPEQBrm",
+ "(V?)PCMPEQDrm",
+ "(V?)PCMPEQQrm",
+ "(V?)PCMPEQWrm",
+ "(V?)PCMPGTBrm",
+ "(V?)PCMPGTDrm",
+ "(V?)PCMPGTWrm",
+ "(V?)PMAXSBrm",
+ "(V?)PMAXSDrm",
+ "(V?)PMAXSWrm",
+ "(V?)PMAXUBrm",
+ "(V?)PMAXUDrm",
+ "(V?)PMAXUWrm",
+ "(V?)PMINSBrm",
+ "(V?)PMINSDrm",
+ "(V?)PMINSWrm",
+ "(V?)PMINUBrm",
+ "(V?)PMINUDrm",
+ "(V?)PMINUWrm",
+ "(V?)PSIGNBrm",
+ "(V?)PSIGNDrm",
+ "(V?)PSIGNWrm",
+ "(V?)PSLLDrm",
+ "(V?)PSLLQrm",
"VPSLLVDrm",
"VPSLLVQrm",
- "VPSLLWrm",
- "VPSRADrm",
+ "(V?)PSLLWrm",
+ "(V?)PSRADrm",
"VPSRAVDrm",
- "VPSRAWrm",
- "VPSRLDrm",
- "VPSRLQrm",
- "VPSRLVDrm",
+ "(V?)PSRAWrm",
+ "(V?)PSRLDrm",
+ "(V?)PSRLQrm",
+ "(V?)PSRLVDrm",
"VPSRLVQrm",
- "VPSRLWrm",
- "VPSUBSBrm",
- "VPSUBSWrm",
- "VPSUBUSBrm",
- "VPSUBUSWrm")>;
+ "(V?)PSRLWrm",
+ "(V?)PSUBSBrm",
+ "(V?)PSUBSWrm",
+ "(V?)PSUBUSBrm",
+ "(V?)PSUBUSWrm")>;
def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let Latency = 7;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup91], (instregex "ANDNPDrm",
- "ANDNPSrm",
- "ANDPDrm",
- "ANDPSrm",
- "BLENDPDrmi",
- "BLENDPSrmi",
- "ORPDrm",
- "ORPSrm",
- "PADDBrm",
- "PADDDrm",
- "PADDQrm",
- "PADDWrm",
- "PANDNrm",
- "PANDrm",
- "PORrm",
- "PSUBBrm",
- "PSUBDrm",
- "PSUBQrm",
- "PSUBWrm",
- "PXORrm",
- "VANDNPDrm",
- "VANDNPSrm",
- "VANDPDrm",
- "VANDPSrm",
- "VBLENDPDrmi",
- "VBLENDPSrmi",
- "VINSERTF128rm",
- "VINSERTI128rm",
- "VMASKMOVPDrm",
- "VMASKMOVPSrm",
- "VORPDrm",
- "VORPSrm",
- "VPADDBrm",
- "VPADDDrm",
- "VPADDQrm",
- "VPADDWrm",
- "VPANDNrm",
- "VPANDrm",
- "VPBLENDDrmi",
- "VPMASKMOVDrm",
- "VPMASKMOVQrm",
- "VPORrm",
- "VPSUBBrm",
- "VPSUBDrm",
- "VPSUBQrm",
- "VPSUBWrm",
- "VPXORrm",
- "VXORPDrm",
- "VXORPSrm",
- "XORPDrm",
- "XORPSrm")>;
+def: InstRW<[SKLWriteResGroup91], (instregex "(V?)ANDNPDrm",
+ "(V?)ANDNPSrm",
+ "(V?)ANDPDrm",
+ "(V?)ANDPSrm",
+ "(V?)BLENDPDrmi",
+ "(V?)BLENDPSrmi",
+ "(V?)INSERTF128rm",
+ "(V?)INSERTI128rm",
+ "(V?)MASKMOVPDrm",
+ "(V?)MASKMOVPSrm",
+ "(V?)ORPDrm",
+ "(V?)ORPSrm",
+ "(V?)PADDBrm",
+ "(V?)PADDDrm",
+ "(V?)PADDQrm",
+ "(V?)PADDWrm",
+ "(V?)PANDNrm",
+ "(V?)PANDrm",
+ "(V?)PBLENDDrmi",
+ "(V?)PMASKMOVDrm",
+ "(V?)PMASKMOVQrm",
+ "(V?)PORrm",
+ "(V?)PSUBBrm",
+ "(V?)PSUBDrm",
+ "(V?)PSUBQrm",
+ "(V?)PSUBWrm",
+ "(V?)PXORrm",
+ "(V?)XORPDrm",
+ "(V?)XORPSrm")>;
def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 7;
@@ -2398,25 +1852,17 @@ def SKLWriteResGroup105 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr",
- "ROUNDPSr",
- "ROUNDSDr",
- "ROUNDSSr",
- "VROUNDPDr",
- "VROUNDPSr",
- "VROUNDSDr",
- "VROUNDSSr",
- "VROUNDPDYr",
- "VROUNDPSYr")>;
+def: InstRW<[SKLWriteResGroup105], (instregex "(V?)ROUNDPD(Y?)r",
+ "(V?)ROUNDPS(Y?)r",
+ "(V?)ROUNDSDr",
+ "(V?)ROUNDSSr")>;
def SKLWriteResGroup105_2 : SchedWriteRes<[SKLPort01]> {
let Latency = 10;
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup105_2], (instregex "PMULLDrr",
- "VPMULLDYrr",
- "VPMULLDrr")>;
+def: InstRW<[SKLWriteResGroup105_2], (instregex "(V?)PMULLD(Y?)rr")>;
def SKLWriteResGroup106 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 8;
@@ -2444,7 +1890,7 @@ def: InstRW<[SKLWriteResGroup107], (inst
def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
let Latency = 8;
let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
+ let ResourceCycles = [1,1,1];
}
def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
@@ -2595,8 +2041,7 @@ def: InstRW<[SKLWriteResGroup111], (inst
"PBLENDVBrm0",
"VBLENDVPDrm",
"VBLENDVPSrm",
- "VPBLENDVBYrm",
- "VPBLENDVBrm")>;
+ "VPBLENDVB(Y?)rm")>;
def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 8;
@@ -2680,10 +2125,8 @@ def: InstRW<[SKLWriteResGroup120], (inst
"MMX_PMULHWirm",
"MMX_PMULLWirm",
"MMX_PMULUDQirm",
- "RCPSSm",
- "RSQRTSSm",
- "VRCPSSm",
- "VRSQRTSSm",
+ "(V?)RCPSSm",
+ "(V?)RSQRTSSm",
"VTESTPDYrm",
"VTESTPSYrm")>;
@@ -2692,44 +2135,30 @@ def SKLWriteResGroup121 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup121], (instregex "PCMPGTQrm",
- "PSADBWrm",
- "VPCMPGTQrm",
+def: InstRW<[SKLWriteResGroup121], (instregex "(V?)PCMPGTQrm",
"VPMOVSXBWYrm",
"VPMOVSXDQYrm",
"VPMOVSXWDYrm",
"VPMOVZXWDYrm",
- "VPSADBWrm")>;
+ "(V?)PSADBWrm")>;
def SKLWriteResGroup122 : SchedWriteRes<[SKLPort01,SKLPort23]> {
let Latency = 9;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup122], (instregex "ADDSDrm",
- "ADDSSrm",
- "CMPSDrm",
- "CMPSSrm",
- "MAX(C?)SDrm",
- "MAX(C?)SSrm",
- "MIN(C?)SDrm",
- "MIN(C?)SSrm",
- "MULSDrm",
- "MULSSrm",
- "SUBSDrm",
- "SUBSSrm",
- "VADDSDrm",
- "VADDSSrm",
- "VCMPSDrm",
- "VCMPSSrm",
- "VMAX(C?)SDrm",
- "VMAX(C?)SSrm",
- "VMIN(C?)SDrm",
- "VMIN(C?)SSrm",
- "VMULSDrm",
- "VMULSSrm",
- "VSUBSDrm",
- "VSUBSSrm")>;
+def: InstRW<[SKLWriteResGroup122], (instregex "(V?)ADDSDrm",
+ "(V?)ADDSSrm",
+ "(V?)CMPSDrm",
+ "(V?)CMPSSrm",
+ "(V?)MAX(C?)SDrm",
+ "(V?)MAX(C?)SSrm",
+ "(V?)MIN(C?)SDrm",
+ "(V?)MIN(C?)SSrm",
+ "(V?)MULSDrm",
+ "(V?)MULSSrm",
+ "(V?)SUBSDrm",
+ "(V?)SUBSSrm")>;
def: InstRW<[SKLWriteResGroup122],
(instregex "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
@@ -2738,11 +2167,10 @@ def SKLWriteResGroup123 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup123], (instregex "CVTPS2PDrm",
- "MMX_CVTPS2PIirm",
+def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVTPS2PIirm",
"MMX_CVTTPS2PIirm",
"VCVTPH2PSrm",
- "VCVTPS2PDrm")>;
+ "(V?)CVTPS2PDrm")>;
def SKLWriteResGroup124 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 9;
@@ -2848,61 +2276,34 @@ def SKLWriteResGroup134 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup134], (instregex "ADDPDrm",
- "ADDPSrm",
- "ADDSUBPDrm",
- "ADDSUBPSrm",
- "CMPPDrmi",
- "CMPPSrmi",
- "CVTDQ2PSrm",
- "CVTPS2DQrm",
- "CVTSS2SDrm",
- "CVTTPS2DQrm",
- "MAX(C?)PDrm",
- "MAX(C?)PSrm",
- "MIN(C?)PDrm",
- "MIN(C?)PSrm",
- "MULPDrm",
- "MULPSrm",
- "PHMINPOSUWrm",
- "PMADDUBSWrm",
- "PMADDWDrm",
- "PMULDQrm",
- "PMULHRSWrm",
- "PMULHUWrm",
- "PMULHWrm",
- "PMULLWrm",
- "PMULUDQrm",
- "SUBPDrm",
- "SUBPSrm",
- "VADDPDrm",
- "VADDPSrm",
- "VADDSUBPDrm",
- "VADDSUBPSrm",
- "VCMPPDrmi",
- "VCMPPSrmi",
- "VCVTDQ2PSrm",
- "VCVTPH2PSYrm",
- "VCVTPS2DQrm",
- "VCVTSS2SDrm",
- "VCVTTPS2DQrm",
- "VMAX(C?)PDrm",
- "VMAX(C?)PSrm",
- "VMIN(C?)PDrm",
- "VMIN(C?)PSrm",
- "VMULPDrm",
- "VMULPSrm",
- "VPHMINPOSUWrm",
- "VPMADDUBSWrm",
- "VPMADDWDrm",
- "VPMULDQrm",
- "VPMULHRSWrm",
- "VPMULHUWrm",
- "VPMULHWrm",
- "VPMULLWrm",
- "VPMULUDQrm",
- "VSUBPDrm",
- "VSUBPSrm")>;
+def: InstRW<[SKLWriteResGroup134], (instregex "(V?)ADDPDrm",
+ "(V?)ADDPSrm",
+ "(V?)ADDSUBPDrm",
+ "(V?)ADDSUBPSrm",
+ "(V?)CMPPDrmi",
+ "(V?)CMPPSrmi",
+ "(V?)CVTDQ2PSrm",
+ "(V?)CVTPH2PSYrm",
+ "(V?)CVTPS2DQrm",
+ "(V?)CVTSS2SDrm",
+ "(V?)CVTTPS2DQrm",
+ "(V?)MAX(C?)PDrm",
+ "(V?)MAX(C?)PSrm",
+ "(V?)MIN(C?)PDrm",
+ "(V?)MIN(C?)PSrm",
+ "(V?)MULPDrm",
+ "(V?)MULPSrm",
+ "(V?)PHMINPOSUWrm",
+ "(V?)PMADDUBSWrm",
+ "(V?)PMADDWDrm",
+ "(V?)PMULDQrm",
+ "(V?)PMULHRSWrm",
+ "(V?)PMULHUWrm",
+ "(V?)PMULHWrm",
+ "(V?)PMULLWrm",
+ "(V?)PMULUDQrm",
+ "(V?)SUBPDrm",
+ "(V?)SUBPSrm")>;
def: InstRW<[SKLWriteResGroup134],
(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m")>;
@@ -2972,11 +2373,8 @@ def SKLWriteResGroup145 : SchedWriteRes<
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup145], (instregex "DIVPSrr",
- "DIVSSrr",
- "VDIVPSYrr",
- "VDIVPSrr",
- "VDIVSSrr")>;
+def: InstRW<[SKLWriteResGroup145], (instregex "(V?)DIVPS(Y?)rr",
+ "(V?)DIVSSrr")>;
def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 11;
@@ -3045,21 +2443,14 @@ def SKLWriteResGroup151 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup151], (instregex "CVTSD2SI64rm",
- "CVTSD2SIrm",
- "CVTSS2SI64rm",
- "CVTSS2SIrm",
- "CVTTSD2SI64rm",
- "CVTTSD2SIrm",
- "CVTTSS2SIrm",
- "VCVTSD2SI64rm",
- "VCVTSD2SIrm",
- "VCVTSS2SI64rm",
- "VCVTSS2SIrm",
- "VCVTTSD2SI64rm",
- "VCVTTSD2SIrm",
+def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSD2SI64rm",
+ "(V?)CVTSD2SIrm",
+ "(V?)CVTSS2SI64rm",
+ "(V?)CVTSS2SIrm",
+ "(V?)CVTTSD2SI64rm",
+ "(V?)CVTTSD2SIrm",
"VCVTTSS2SI64rm",
- "VCVTTSS2SIrm")>;
+ "(V?)CVTTSS2SIrm")>;
def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
let Latency = 11;
@@ -3107,8 +2498,7 @@ def SKLWriteResGroup157 : SchedWriteRes<
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPSYr",
- "VSQRTPSr",
+def: InstRW<[SKLWriteResGroup157], (instregex "VSQRTPS(Y?)r",
"VSQRTSSr")>;
def SKLWriteResGroup159 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
@@ -3160,9 +2550,7 @@ def SKLWriteResGroup164 : SchedWriteRes<
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SKLWriteResGroup164], (instregex "DPPSrri",
- "VDPPSYrri",
- "VDPPSrri")>;
+def: InstRW<[SKLWriteResGroup164], (instregex "(V?)DPPS(Y?)rri")>;
def SKLWriteResGroup165 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
let Latency = 13;
@@ -3179,11 +2567,8 @@ def SKLWriteResGroup166 : SchedWriteRes<
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup166], (instregex "DIVPDrr",
- "DIVSDrr",
- "VDIVPDYrr",
- "VDIVPDrr",
- "VDIVSDrr")>;
+def: InstRW<[SKLWriteResGroup166], (instregex "(V?)DIVPD(Y?)rr",
+ "(V?)DIVSDrr")>;
def SKLWriteResGroup168 : SchedWriteRes<[SKLPort23,SKLPort01]> {
let Latency = 14;
@@ -3296,8 +2681,7 @@ def SKLWriteResGroup181 : SchedWriteRes<
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPDYr",
- "VSQRTPDr",
+def: InstRW<[SKLWriteResGroup181], (instregex "VSQRTPD(Y?)r",
"VSQRTSDr")>;
def SKLWriteResGroup182 : SchedWriteRes<[SKLPort0,SKLPort23]> {
@@ -3328,9 +2712,8 @@ def SKLWriteResGroup186 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup186], (instregex "DIVSDrm",
- "SQRTPSm",
- "VDIVSDrm",
+def: InstRW<[SKLWriteResGroup186], (instregex "SQRTPSm",
+ "(V?)DIVSDrm",
"VSQRTPSYm")>;
def SKLWriteResGroup187 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {