[llvm] r328203 - [X86][SSE42] Use the default PCMPEST/PCMPIST scheduler classes directly. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 22 07:56:18 PDT 2018
Author: rksimon
Date: Thu Mar 22 07:56:18 2018
New Revision: 328203
URL: http://llvm.org/viewvc/llvm-project?rev=328203&view=rev
Log:
[X86][SSE42] Use the default PCMPEST/PCMPIST scheduler classes directly. NFCI.
Models were completely overriding all SSE42 strins instructions when the default classes could be used for exactly the same coverage.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=328203&r1=328202&r2=328203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Thu Mar 22 07:56:18 2018
@@ -170,42 +170,53 @@ defm : BWWriteResPair<WriteCvtI2F, [BWPo
defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
// Strings instructions.
+
// Packed Compare Implicit Length Strings, Return Mask
-// String instructions.
def : WriteRes<WritePCmpIStrM, [BWPort0]> {
- let Latency = 10;
+ let Latency = 11;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
- let Latency = 10;
- let ResourceCycles = [3, 1];
-}
+ let Latency = 16;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
+}
+
// Packed Compare Explicit Length Strings, Return Mask
-def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort16, BWPort5]> {
- let Latency = 10;
- let ResourceCycles = [3, 2, 4];
+def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
+ let Latency = 19;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
-def : WriteRes<WritePCmpEStrMLd, [BWPort05, BWPort16, BWPort23]> {
- let Latency = 10;
- let ResourceCycles = [6, 2, 1];
-}
- // Packed Compare Implicit Length Strings, Return Index
+def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
+ let Latency = 24;
+ let NumMicroOps = 10;
+ let ResourceCycles = [4,3,1,1,1];
+}
+
+// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [BWPort0]> {
let Latency = 11;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 1];
-}
+ let Latency = 16;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
+}
+
// Packed Compare Explicit Length Strings, Return Index
-def : WriteRes<WritePCmpEStrI, [BWPort05, BWPort16]> {
- let Latency = 11;
- let ResourceCycles = [6, 2];
+def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
+ let Latency = 18;
+ let NumMicroOps = 8;
+ let ResourceCycles = [4,3,1];
}
-def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort16, BWPort5, BWPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 2, 2, 1];
+def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
+ let Latency = 23;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
// AES instructions.
@@ -2931,16 +2942,6 @@ def BWWriteResGroup124 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup124],
(instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
-def BWWriteResGroup125 : SchedWriteRes<[BWPort0]> {
- let Latency = 11;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
-}
-def: InstRW<[BWWriteResGroup125], (instregex "PCMPISTRIrr",
- "PCMPISTRM128rr",
- "VPCMPISTRIrr",
- "VPCMPISTRM128rr")>;
-
def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
let Latency = 11;
let NumMicroOps = 3;
@@ -3142,14 +3143,6 @@ def BWWriteResGroup151 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
-def BWWriteResGroup152 : SchedWriteRes<[BWPort0,BWPort23]> {
- let Latency = 16;
- let NumMicroOps = 4;
- let ResourceCycles = [3,1];
-}
-def: InstRW<[BWWriteResGroup152], (instregex "(V?)PCMPISTRIrm",
- "(V?)PCMPISTRM128rm")>;
-
def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
let Latency = 16;
let NumMicroOps = 14;
@@ -3187,13 +3180,6 @@ def BWWriteResGroup157 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup157], (instregex "SQRTPSm",
"SQRTSSm")>;
-def BWWriteResGroup158 : SchedWriteRes<[BWPort0,BWPort5,BWPort0156]> {
- let Latency = 18;
- let NumMicroOps = 8;
- let ResourceCycles = [4,3,1];
-}
-def: InstRW<[BWWriteResGroup158], (instregex "(V?)PCMPESTRIrr")>;
-
def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
@@ -3228,13 +3214,6 @@ def BWWriteResGroup163 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
-def BWWriteResGroup164 : SchedWriteRes<[BWPort0,BWPort5,BWPort015,BWPort0156]> {
- let Latency = 19;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[BWWriteResGroup164], (instregex "(V?)PCMPESTRM128rr")>;
-
def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
let Latency = 20;
let NumMicroOps = 1;
@@ -3313,13 +3292,6 @@ def BWWriteResGroup174 : SchedWriteRes<[
}
def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
-def BWWriteResGroup175 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort0156]> {
- let Latency = 23;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[BWWriteResGroup175], (instregex "(V?)PCMPESTRIrm")>;
-
def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
let Latency = 23;
let NumMicroOps = 19;
@@ -3335,13 +3307,6 @@ def BWWriteResGroup177 : SchedWriteRes<[
def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
"DIV_FI32m")>;
-def BWWriteResGroup178 : SchedWriteRes<[BWPort0,BWPort5,BWPort23,BWPort015,BWPort0156]> {
- let Latency = 24;
- let NumMicroOps = 10;
- let ResourceCycles = [4,3,1,1,1];
-}
-def: InstRW<[BWWriteResGroup178], (instregex "(V?)PCMPESTRM128rm")>;
-
def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 25;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=328203&r1=328202&r2=328203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Thu Mar 22 07:56:18 2018
@@ -167,44 +167,53 @@ defm : HWWriteResPair<WriteVarVecShift,
defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 6, [1, 2]>;
// String instructions.
+
// Packed Compare Implicit Length Strings, Return Mask
def : WriteRes<WritePCmpIStrM, [HWPort0]> {
- let Latency = 10;
+ let Latency = 11;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
- let Latency = 10;
- let ResourceCycles = [3, 1];
+ let Latency = 17;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
-def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
- let Latency = 10;
- let ResourceCycles = [3, 2, 4];
+def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> {
+ let Latency = 19;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
-def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
- let Latency = 10;
- let ResourceCycles = [6, 2, 1];
+def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> {
+ let Latency = 25;
+ let NumMicroOps = 10;
+ let ResourceCycles = [4,3,1,1,1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [HWPort0]> {
let Latency = 11;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 1];
+ let Latency = 17;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
-def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
- let Latency = 11;
- let ResourceCycles = [6, 2];
+def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
+ let Latency = 18;
+ let NumMicroOps = 8;
+ let ResourceCycles = [4,3,1];
}
-def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 2, 2, 1];
+def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
+ let Latency = 24;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
// AES Instructions.
@@ -2941,14 +2950,6 @@ def HWWriteResGroup122_1 : SchedWriteRes
}
def: InstRW<[HWWriteResGroup122_1], (instregex "DIVSSrm")>;
-def HWWriteResGroup123 : SchedWriteRes<[HWPort0]> {
- let Latency = 11;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
-}
-def: InstRW<[HWWriteResGroup123], (instregex "(V?)PCMPISTRIrr",
- "(V?)PCMPISTRM128rr")>;
-
def HWWriteResGroup125 : SchedWriteRes<[HWPort0,HWPort015]> {
let Latency = 11;
let NumMicroOps = 3;
@@ -2957,14 +2958,6 @@ def HWWriteResGroup125 : SchedWriteRes<[
def: InstRW<[HWWriteResGroup125], (instregex "VRCPPSYr",
"VRSQRTPSYr")>;
-def HWWriteResGroup126 : SchedWriteRes<[HWPort0,HWPort23]> {
- let Latency = 17;
- let NumMicroOps = 4;
- let ResourceCycles = [3,1];
-}
-def: InstRW<[HWWriteResGroup126], (instregex "(V?)PCMPISTRIrm",
- "(V?)PCMPISTRM128rm")>;
-
def HWWriteResGroup128 : SchedWriteRes<[HWPort0,HWPort23,HWPort015]> {
let Latency = 18;
let NumMicroOps = 4;
@@ -3112,13 +3105,6 @@ def HWWriteResGroup147 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup147], (instregex "XCH_F")>;
-def HWWriteResGroup148 : SchedWriteRes<[HWPort0,HWPort5,HWPort0156]> {
- let Latency = 18;
- let NumMicroOps = 8;
- let ResourceCycles = [4,3,1];
-}
-def: InstRW<[HWWriteResGroup148], (instregex "(V?)PCMPESTRIrr")>;
-
def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
@@ -3127,13 +3113,6 @@ def HWWriteResGroup149 : SchedWriteRes<[
def: InstRW<[HWWriteResGroup149], (instregex "CPUID")>;
def: InstRW<[HWWriteResGroup149], (instrs RDTSC)>;
-def HWWriteResGroup150 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort0156]> {
- let Latency = 24;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[HWWriteResGroup150], (instregex "(V?)PCMPESTRIrm")>;
-
def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
let Latency = 23;
let NumMicroOps = 19;
@@ -3141,20 +3120,6 @@ def HWWriteResGroup151 : SchedWriteRes<[
}
def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>;
-def HWWriteResGroup152 : SchedWriteRes<[HWPort0,HWPort5,HWPort015,HWPort0156]> {
- let Latency = 19;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[HWWriteResGroup152], (instregex "(V?)PCMPESTRM128rr")>;
-
-def HWWriteResGroup153 : SchedWriteRes<[HWPort0,HWPort5,HWPort23,HWPort015,HWPort0156]> {
- let Latency = 25;
- let NumMicroOps = 10;
- let ResourceCycles = [4,3,1,1,1];
-}
-def: InstRW<[HWWriteResGroup153], (instregex "(V?)PCMPESTRM128rm")>;
-
def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> {
let Latency = 20;
let NumMicroOps = 1;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=328203&r1=328202&r2=328203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Thu Mar 22 07:56:18 2018
@@ -151,14 +151,17 @@ defm : SBWriteResPair<WriteFHAdd, [SBP
defm : SBWriteResPair<WritePHAdd, [SBPort15], 1>;
// String instructions.
+
// Packed Compare Implicit Length Strings, Return Mask
-def : WriteRes<WritePCmpIStrM, [SBPort015]> {
+def : WriteRes<WritePCmpIStrM, [SBPort0]> {
let Latency = 11;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
-def : WriteRes<WritePCmpIStrMLd, [SBPort015, SBPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 1];
+def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> {
+ let Latency = 17;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
@@ -1908,14 +1911,6 @@ def: InstRW<[SBWriteResGroup104], (instr
"(V?)RSQRTPSm",
"(V?)RSQRTSSm")>;
-def SBWriteResGroup105 : SchedWriteRes<[SBPort0]> {
- let Latency = 11;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
-}
-def: InstRW<[SBWriteResGroup105], (instregex "(V?)PCMPISTRIrr",
- "(V?)PCMPISTRM128rr")>;
-
def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 11;
let NumMicroOps = 3;
@@ -2032,14 +2027,6 @@ def SBWriteResGroup120 : SchedWriteRes<[
}
def: InstRW<[SBWriteResGroup120], (instregex "(V?)DPPDrmi")>;
-def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort23]> {
- let Latency = 17;
- let NumMicroOps = 4;
- let ResourceCycles = [3,1];
-}
-def: InstRW<[SBWriteResGroup121], (instregex "(V?)PCMPISTRIrm",
- "(V?)PCMPISTRM128rm")>;
-
def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 20;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=328203&r1=328202&r2=328203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Thu Mar 22 07:56:18 2018
@@ -173,42 +173,53 @@ defm : SKLWriteResPair<WriteCvtI2F, [SKL
defm : SKLWriteResPair<WriteCvtF2F, [SKLPort1], 3>; // Float -> Float size conversion.
// Strings instructions.
+
// Packed Compare Implicit Length Strings, Return Mask
-// String instructions.
def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
let Latency = 10;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
- let Latency = 10;
- let ResourceCycles = [3, 1];
-}
+ let Latency = 16;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
+}
+
// Packed Compare Explicit Length Strings, Return Mask
-def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort16, SKLPort5]> {
- let Latency = 10;
- let ResourceCycles = [3, 2, 4];
+def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
+ let Latency = 19;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
-def : WriteRes<WritePCmpEStrMLd, [SKLPort05, SKLPort16, SKLPort23]> {
- let Latency = 10;
- let ResourceCycles = [6, 2, 1];
-}
- // Packed Compare Implicit Length Strings, Return Index
+def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
+ let Latency = 25;
+ let NumMicroOps = 10;
+ let ResourceCycles = [4,3,1,1,1];
+}
+
+// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
- let Latency = 11;
+ let Latency = 10;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 1];
-}
+ let Latency = 16;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
+}
+
// Packed Compare Explicit Length Strings, Return Index
-def : WriteRes<WritePCmpEStrI, [SKLPort05, SKLPort16]> {
- let Latency = 11;
- let ResourceCycles = [6, 2];
+def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
+ let Latency = 18;
+ let NumMicroOps = 8;
+ let ResourceCycles = [4,3,1];
}
-def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort16, SKLPort5, SKLPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 2, 2, 1];
+def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
+ let Latency = 24;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
// AES instructions.
@@ -2916,14 +2927,6 @@ def: InstRW<[SKLWriteResGroup135], (inst
"VPMULLWrm",
"VPMULUDQrm")>;
-def SKLWriteResGroup136 : SchedWriteRes<[SKLPort0]> {
- let Latency = 10;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
-}
-def: InstRW<[SKLWriteResGroup136], (instregex "(V?)PCMPISTRIrr",
- "(V?)PCMPISTRM128rr")>;
-
def SKLWriteResGroup137 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 10;
let NumMicroOps = 3;
@@ -3286,14 +3289,6 @@ def SKLWriteResGroup175 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup175], (instregex "(V?)DIVSSrm")>;
-def SKLWriteResGroup176 : SchedWriteRes<[SKLPort0,SKLPort23]> {
- let Latency = 16;
- let NumMicroOps = 4;
- let ResourceCycles = [3,1];
-}
-def: InstRW<[SKLWriteResGroup176], (instregex "(V?)PCMPISTRIrm",
- "(V?)PCMPISTRM128rm")>;
-
def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 16;
let NumMicroOps = 14;
@@ -3341,13 +3336,6 @@ def: InstRW<[SKLWriteResGroup182], (inst
"VDIVPSYrm",
"VSQRTPSm")>;
-def SKLWriteResGroup183 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort0156]> {
- let Latency = 18;
- let NumMicroOps = 8;
- let ResourceCycles = [4,3,1];
-}
-def: InstRW<[SKLWriteResGroup183], (instregex "(V?)PCMPESTRIrr")>;
-
def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
@@ -3379,13 +3367,6 @@ def SKLWriteResGroup187 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup187], (instregex "(V?)DPPSrmi")>;
-def SKLWriteResGroup188 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort015,SKLPort0156]> {
- let Latency = 19;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[SKLWriteResGroup188], (instregex "(V?)PCMPESTRM128rr")>;
-
def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
let Latency = 20;
let NumMicroOps = 1;
@@ -3491,13 +3472,6 @@ def SKLWriteResGroup199 : SchedWriteRes<
}
def: InstRW<[SKLWriteResGroup199], (instregex "VSQRTPDm")>;
-def SKLWriteResGroup200 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
- let Latency = 24;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[SKLWriteResGroup200], (instregex "(V?)PCMPESTRIrm")>;
-
def SKLWriteResGroup201 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 25;
let NumMicroOps = 2;
@@ -3514,13 +3488,6 @@ def SKLWriteResGroup202 : SchedWriteRes<
def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI16m",
"DIV_FI32m")>;
-def SKLWriteResGroup203 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort015,SKLPort0156]> {
- let Latency = 25;
- let NumMicroOps = 10;
- let ResourceCycles = [4,3,1,1,1];
-}
-def: InstRW<[SKLWriteResGroup203], (instregex "(V?)PCMPESTRM128rm")>;
-
def SKLWriteResGroup205 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 26;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=328203&r1=328202&r2=328203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Thu Mar 22 07:56:18 2018
@@ -173,42 +173,53 @@ defm : SKXWriteResPair<WriteCvtI2F, [SKX
defm : SKXWriteResPair<WriteCvtF2F, [SKXPort1], 3>; // Float -> Float size conversion.
// Strings instructions.
+
// Packed Compare Implicit Length Strings, Return Mask
-// String instructions.
def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
let Latency = 10;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
- let Latency = 10;
- let ResourceCycles = [3, 1];
+ let Latency = 16;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
}
+
// Packed Compare Explicit Length Strings, Return Mask
-def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort16, SKXPort5]> {
- let Latency = 10;
- let ResourceCycles = [3, 2, 4];
+def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
+ let Latency = 19;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
-def : WriteRes<WritePCmpEStrMLd, [SKXPort05, SKXPort16, SKXPort23]> {
- let Latency = 10;
- let ResourceCycles = [6, 2, 1];
-}
- // Packed Compare Implicit Length Strings, Return Index
+def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
+ let Latency = 25;
+ let NumMicroOps = 10;
+ let ResourceCycles = [4,3,1,1,1];
+}
+
+// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
- let Latency = 11;
+ let Latency = 10;
+ let NumMicroOps = 3;
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 1];
-}
+ let Latency = 16;
+ let NumMicroOps = 4;
+ let ResourceCycles = [3,1];
+}
+
// Packed Compare Explicit Length Strings, Return Index
-def : WriteRes<WritePCmpEStrI, [SKXPort05, SKXPort16]> {
- let Latency = 11;
- let ResourceCycles = [6, 2];
+def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
+ let Latency = 18;
+ let NumMicroOps = 8;
+ let ResourceCycles = [4,3,1];
}
-def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort16, SKXPort5, SKXPort23]> {
- let Latency = 11;
- let ResourceCycles = [3, 2, 2, 1];
+def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
+ let Latency = 24;
+ let NumMicroOps = 9;
+ let ResourceCycles = [4,3,1,1];
}
// AES instructions.
@@ -5002,16 +5013,6 @@ def: InstRW<[SKXWriteResGroup149], (inst
"VSUBSDZrm(_Int)?(k?)(z?)",
"VSUBSSZrm(_Int)?(k?)(z?)")>;
-def SKXWriteResGroup150 : SchedWriteRes<[SKXPort0]> {
- let Latency = 10;
- let NumMicroOps = 3;
- let ResourceCycles = [3];
-}
-def: InstRW<[SKXWriteResGroup150], (instregex "PCMPISTRIrr",
- "PCMPISTRM128rr",
- "VPCMPISTRIrr",
- "VPCMPISTRM128rr")>;
-
def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 10;
let NumMicroOps = 3;
@@ -5605,16 +5606,6 @@ def SKXWriteResGroup196 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup196], (instregex "(V?)DIVSSrm")>;
-def SKXWriteResGroup197 : SchedWriteRes<[SKXPort0,SKXPort23]> {
- let Latency = 16;
- let NumMicroOps = 4;
- let ResourceCycles = [3,1];
-}
-def: InstRW<[SKXWriteResGroup197], (instregex "PCMPISTRIrm",
- "PCMPISTRM128rm",
- "VPCMPISTRIrm",
- "VPCMPISTRM128rm")>;
-
def SKXWriteResGroup198 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 16;
let NumMicroOps = 4;
@@ -5691,13 +5682,6 @@ def SKXWriteResGroup205 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)(k?)(z?)")>;
-def SKXWriteResGroup206 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort0156]> {
- let Latency = 18;
- let NumMicroOps = 8;
- let ResourceCycles = [4,3,1];
-}
-def: InstRW<[SKXWriteResGroup206], (instregex "(V?)PCMPESTRIrr")>;
-
def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
let Latency = 18;
let NumMicroOps = 8;
@@ -5744,13 +5728,6 @@ def SKXWriteResGroup212 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup212], (instregex "(V?)DPPSrmi")>;
-def SKXWriteResGroup213 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015,SKXPort0156]> {
- let Latency = 19;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[SKXWriteResGroup213], (instregex "(V?)PCMPESTRM128rr")>;
-
def SKXWriteResGroup214 : SchedWriteRes<[]> {
let Latency = 20;
let NumMicroOps = 0;
@@ -5925,13 +5902,6 @@ def SKXWriteResGroup230 : SchedWriteRes<
}
def: InstRW<[SKXWriteResGroup230], (instregex "VDIVPSZrm(b?)(k?)(z?)")>;
-def SKXWriteResGroup231 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156]> {
- let Latency = 24;
- let NumMicroOps = 9;
- let ResourceCycles = [4,3,1,1];
-}
-def: InstRW<[SKXWriteResGroup231], (instregex "(V?)PCMPESTRIrm")>;
-
def SKXWriteResGroup232 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 25;
let NumMicroOps = 2;
@@ -5959,13 +5929,6 @@ def: InstRW<[SKXWriteResGroup234], (inst
VPGATHERQDZrm,
VPGATHERQQZ256rm)>;
-def SKXWriteResGroup235 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015,SKXPort0156]> {
- let Latency = 25;
- let NumMicroOps = 10;
- let ResourceCycles = [4,3,1,1,1];
-}
-def: InstRW<[SKXWriteResGroup235], (instregex "(V?)PCMPESTRM128rm")>;
-
def SKXWriteResGroup237 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
let Latency = 26;
let NumMicroOps = 4;
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