[PATCH] D44654: [X86][SandyBridge] SBWriteResPair +5cy and +1uop Memory Folds

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

2 cycle latency for MOV64rm seems low to me. There's an address calculation and a TLB lookup before it can even start accessing the cache.

Table 2-20 of https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf shows the load latencies according to Intel.


Repository:
  rL LLVM

https://reviews.llvm.org/D44654