[PATCH] D44746: [Power9]Legalize and emit code for quad-precision convert from double-precision

[Lei Huang via Phabricator via llvm-commits]

lei updated this revision to Diff 139364.
lei added a comment.

fix checks in testcase.


https://reviews.llvm.org/D44746

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/f128-arith.ll


Index: test/CodeGen/PowerPC/f128-arith.ll
===================================================================
--- test/CodeGen/PowerPC/f128-arith.ll
+++ test/CodeGen/PowerPC/f128-arith.ll
@@ -131,3 +131,30 @@
 ; CHECK stxv
 ; CHECK blr
 }
+
+; Function Attrs: norecurse nounwind
+define void @dpConv2qp(double* nocapture readonly %a, fp128* nocapture %res) {
+entry:
+  %0 = load double, double* %a, align 8
+  %conv = fpext double %0 to fp128
+  store fp128 %conv, fp128* %res, align 16
+  ret void
+; CHECK-LABEL: dpConv2qp
+; CHECK-NOT: bl __extenddftf2
+; CHECK: lxsd
+; CHECK: xscvdpqp
+; CHECK: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @dpConv2qp_02(double %a, fp128* nocapture %res) {
+entry:
+  %conv = fpext double %a to fp128
+  store fp128 %conv, fp128* %res, align 16
+  ret void
+; CHECK-LABEL: dpConv2qp_02
+; CHECK-NOT: bl __extenddftf2
+; CHECK: xxlor
+; CHECK: xscvdpqp
+; CHECK: blr
+}
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -2470,6 +2470,7 @@
 
   // Convert DP -> QP
   def XSCVDPQP  : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, []>;
+  def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>;
 
   // Round & Convert QP -> DP (dword[1] is set to zero)
   def XSCVQPDP  : X_VT5_XO5_VB5   <63, 20, 836, "xscvqpdp" , []>;
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -791,6 +791,8 @@
       setOperationAction(ISD::FSUB, MVT::f128, Legal);
       setOperationAction(ISD::FDIV, MVT::f128, Legal);
       setOperationAction(ISD::FMUL, MVT::f128, Legal);
+      setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
+      setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
 
     }
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D44746.139364.patch
Type: text/x-patch
Size: 1949 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180321/660ffaef/attachment.bin>