[llvm] r328104 - [RISCV] Codegen support for RV32F floating point comparison operations
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 21 08:11:02 PDT 2018
Author: asb
Date: Wed Mar 21 08:11:02 2018
New Revision: 328104
URL: http://llvm.org/viewvc/llvm-project?rev=328104&view=rev
Log:
[RISCV] Codegen support for RV32F floating point comparison operations
This patch also includes extensive tests targeted at select and br+fcmp IR
inputs. A sequence of br+fcmp required support for FPR32 registers to be added
to RISCVInstrInfo::storeRegToStackSlot and
RISCVInstrInfo::loadRegFromStackSlot.
Added:
llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll
Modified:
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/trunk/test/CodeGen/RISCV/bare-select.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=328104&r1=328103&r2=328104&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Wed Mar 21 08:11:02 2018
@@ -109,6 +109,14 @@ RISCVTargetLowering::RISCVTargetLowering
if (Subtarget.hasStdExtF()) {
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
+ for (auto CC :
+ {ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
+ ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
+ ISD::SETGT, ISD::SETGE, ISD::SETNE})
+ setCondCodeAction(CC, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
+ setOperationAction(ISD::SELECT, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Expand);
}
setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
@@ -390,8 +398,13 @@ RISCVTargetLowering::EmitInstrWithCustom
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- assert(MI.getOpcode() == RISCV::Select_GPR_Using_CC_GPR &&
- "Unexpected instr type to insert");
+ switch (MI.getOpcode()) {
+ default:
+ llvm_unreachable("Unexpected instr type to insert");
+ case RISCV::Select_GPR_Using_CC_GPR:
+ case RISCV::Select_FPR32_Using_CC_GPR:
+ break;
+ }
// To "insert" a SELECT instruction, we actually have to insert the triangle
// control-flow pattern. The incoming instruction knows the destination vreg
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp?rev=328104&r1=328103&r2=328104&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp Wed Mar 21 08:11:02 2018
@@ -36,12 +36,21 @@ void RISCVInstrInfo::copyPhysReg(Machine
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, unsigned DstReg,
unsigned SrcReg, bool KillSrc) const {
- assert(RISCV::GPRRegClass.contains(DstReg, SrcReg) &&
- "Impossible reg-to-reg copy");
+ if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addImm(0);
+ return;
+ }
- BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc))
- .addImm(0);
+ if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::FSGNJ_S), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+
+ llvm_unreachable("Impossible reg-to-reg copy");
}
void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
@@ -53,13 +62,19 @@ void RISCVInstrInfo::storeRegToStackSlot
if (I != MBB.end())
DL = I->getDebugLoc();
+ unsigned Opcode;
+
if (RISCV::GPRRegClass.hasSubClassEq(RC))
- BuildMI(MBB, I, DL, get(RISCV::SW))
- .addReg(SrcReg, getKillRegState(IsKill))
- .addFrameIndex(FI)
- .addImm(0);
+ Opcode = RISCV::SW;
+ else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
+ Opcode = RISCV::FSW;
else
llvm_unreachable("Can't store this register to stack slot");
+
+ BuildMI(MBB, I, DL, get(Opcode))
+ .addReg(SrcReg, getKillRegState(IsKill))
+ .addFrameIndex(FI)
+ .addImm(0);
}
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -71,10 +86,16 @@ void RISCVInstrInfo::loadRegFromStackSlo
if (I != MBB.end())
DL = I->getDebugLoc();
+ unsigned Opcode;
+
if (RISCV::GPRRegClass.hasSubClassEq(RC))
- BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0);
+ Opcode = RISCV::LW;
+ else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
+ Opcode = RISCV::FLW;
else
llvm_unreachable("Can't load this register from stack slot");
+
+ BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
}
void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=328104&r1=328103&r2=328104&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Wed Mar 21 08:11:02 2018
@@ -536,11 +536,14 @@ def : Pat<(setge GPR:$rs1, GPR:$rs2), (X
def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
let usesCustomInserter = 1 in
-def Select_GPR_Using_CC_GPR
- : Pseudo<(outs GPR:$dst),
- (ins GPR:$lhs, GPR:$rhs, ixlenimm:$imm, GPR:$src, GPR:$src2),
- [(set XLenVT:$dst, (SelectCC GPR:$lhs, GPR:$rhs,
- (XLenVT imm:$imm), GPR:$src, GPR:$src2))]>;
+class SelectCC_rrirr<RegisterClass valty, RegisterClass cmpty>
+ : Pseudo<(outs valty:$dst),
+ (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm,
+ valty:$truev, valty:$falsev),
+ [(set valty:$dst, (SelectCC cmpty:$lhs, cmpty:$rhs,
+ (XLenVT imm:$imm), valty:$truev, valty:$falsev))]>;
+
+def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>;
/// Branches and jumps
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td?rev=328104&r1=328103&r2=328104&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td Wed Mar 21 08:11:02 2018
@@ -272,10 +272,26 @@ def : Pat<(fcopysign FPR32:$rs1, (fneg F
def : PatFpr32Fpr32<fminnum, FMIN_S>;
def : PatFpr32Fpr32<fmaxnum, FMAX_S>;
+/// Setcc
+
+def : PatFpr32Fpr32<seteq, FEQ_S>;
def : PatFpr32Fpr32<setoeq, FEQ_S>;
+def : PatFpr32Fpr32<setlt, FLT_S>;
def : PatFpr32Fpr32<setolt, FLT_S>;
+def : PatFpr32Fpr32<setle, FLE_S>;
def : PatFpr32Fpr32<setole, FLE_S>;
+// Define pattern expansions for setcc operations which aren't directly
+// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
+// Legalizer.
+
+def : Pat<(setuo FPR32:$rs1, FPR32:$rs2),
+ (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
+ (FEQ_S FPR32:$rs2, FPR32:$rs2)),
+ 1)>;
+
+def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
+
/// Loads
defm : LdPat<load, FLW>;
Modified: llvm/trunk/test/CodeGen/RISCV/bare-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/bare-select.ll?rev=328104&r1=328103&r2=328104&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/bare-select.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/bare-select.ll Wed Mar 21 08:11:02 2018
@@ -15,3 +15,17 @@ define i32 @bare_select(i1 %a, i32 %b, i
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
}
+
+define float @bare_select_float(i1 %a, float %b, float %c) {
+; RV32I-LABEL: bare_select_float:
+; RV32I: # %bb.0:
+; RV32I-NEXT: andi a0, a0, 1
+; RV32I-NEXT: bnez a0, .LBB1_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a1, a2
+; RV32I-NEXT: .LBB1_2:
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: ret
+ %1 = select i1 %a, float %b, float %c
+ ret float %1
+}
Added: llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll?rev=328104&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll Wed Mar 21 08:11:02 2018
@@ -0,0 +1,534 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
+
+declare void @abort()
+declare void @exit(i32)
+declare float @dummy(float)
+
+define void @br_fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_false:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: addi a0, zero, 1
+; RV32IF-NEXT: bnez a0, .LBB0_2
+; RV32IF-NEXT: # %bb.1: # %if.then
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB0_2: # %if.else
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp false float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.then:
+ ret void
+if.else:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oeq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB1_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB1_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp oeq float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+; TODO: generated code quality for this is very poor due to
+; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
+; expansion.
+define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oeq_alt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: beqz a0, .LBB2_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB2_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp oeq float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.then:
+ tail call void @abort()
+ unreachable
+if.else:
+ ret void
+}
+
+define void @br_fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ogt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB3_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB3_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp ogt float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB4_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB4_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp oge float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_olt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB5_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB5_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp olt float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ole:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB6_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB6_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp ole float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+; TODO: feq.s+sltiu+bne -> feq.s+beq
+define void @br_fcmp_one(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_one:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: feq.s a1, ft0, ft1
+; RV32IF-NEXT: not a1, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: bnez a0, .LBB7_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB7_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp one float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ord:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB8_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB8_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp ord float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ueq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: feq.s a2, ft1, ft1
+; RV32IF-NEXT: and a1, a2, a1
+; RV32IF-NEXT: seqz a1, a1
+; RV32IF-NEXT: or a0, a0, a1
+; RV32IF-NEXT: bnez a0, .LBB9_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB9_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp ueq float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ugt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB10_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB10_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp ugt float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_uge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB11_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB11_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp uge float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ult:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB12_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB12_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp ult float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ule:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB13_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB13_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp ule float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_une:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB14_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB14_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp une float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_uno(float %a, float %b) nounwind {
+; TODO: sltiu+bne -> beq
+; RV32IF-LABEL: br_fcmp_uno:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: bnez a0, .LBB15_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB15_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp uno float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+define void @br_fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_true:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: addi a0, zero, 1
+; RV32IF-NEXT: bnez a0, .LBB16_2
+; RV32IF-NEXT: # %bb.1: # %if.else
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB16_2: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+ %1 = fcmp true float %a, %b
+ br i1 %1, label %if.then, label %if.else
+if.else:
+ ret void
+if.then:
+ tail call void @abort()
+ unreachable
+}
+
+; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot
+; and RISCVInstrInfo::loadRegFromStackSlot
+define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
+; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw
+; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
+; RV32IF: # %bb.0: # %entry
+; RV32IF-NEXT: addi sp, sp, -16
+; RV32IF-NEXT: sw ra, 12(sp)
+; RV32IF-NEXT: sw s1, 8(sp)
+; RV32IF-NEXT: lui a0, %hi(dummy)
+; RV32IF-NEXT: addi s1, a0, %lo(dummy)
+; RV32IF-NEXT: mv a0, zero
+; RV32IF-NEXT: jalr s1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: lui a0, %hi(.LCPI17_0)
+; RV32IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
+; RV32IF-NEXT: flw ft1, 0(a0)
+; RV32IF-NEXT: fsw ft1, 4(sp)
+; RV32IF-NEXT: feq.s a0, ft0, ft1
+; RV32IF-NEXT: beqz a0, .LBB17_3
+; RV32IF-NEXT: # %bb.1: # %if.end
+; RV32IF-NEXT: mv a0, zero
+; RV32IF-NEXT: jalr s1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: flw ft1, 4(sp)
+; RV32IF-NEXT: feq.s a0, ft0, ft1
+; RV32IF-NEXT: beqz a0, .LBB17_3
+; RV32IF-NEXT: # %bb.2: # %if.end4
+; RV32IF-NEXT: mv a0, zero
+; RV32IF-NEXT: lw s1, 8(sp)
+; RV32IF-NEXT: lw ra, 12(sp)
+; RV32IF-NEXT: addi sp, sp, 16
+; RV32IF-NEXT: ret
+; RV32IF-NEXT: .LBB17_3: # %if.then
+; RV32IF-NEXT: lui a0, %hi(abort)
+; RV32IF-NEXT: addi a0, a0, %lo(abort)
+; RV32IF-NEXT: jalr a0
+entry:
+ %call = call float @dummy(float 0.000000e+00)
+ %cmp = fcmp une float %call, 0.000000e+00
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ call void @abort()
+ unreachable
+
+if.end:
+ %call1 = call float @dummy(float 0.000000e+00)
+ %cmp2 = fcmp une float %call1, 0.000000e+00
+ br i1 %cmp2, label %if.then3, label %if.end4
+
+if.then3:
+ call void @abort()
+ unreachable
+
+if.end4:
+ ret i32 0
+}
Added: llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll?rev=328104&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll Wed Mar 21 08:11:02 2018
@@ -0,0 +1,215 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
+
+define i32 @fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_false:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: mv a0, zero
+; RV32IF-NEXT: ret
+ %1 = fcmp false float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_oeq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp oeq float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ogt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ogt float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_oge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp oge float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_olt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp olt float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ole:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ole float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_one(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_one:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: feq.s a1, ft0, ft1
+; RV32IF-NEXT: not a1, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: ret
+ %1 = fcmp one float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ord:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: ret
+ %1 = fcmp ord float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ueq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: feq.s a2, ft1, ft1
+; RV32IF-NEXT: and a1, a2, a1
+; RV32IF-NEXT: seqz a1, a1
+; RV32IF-NEXT: or a0, a0, a1
+; RV32IF-NEXT: ret
+ %1 = fcmp ueq float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ugt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: ret
+ %1 = fcmp ugt float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_uge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: ret
+ %1 = fcmp uge float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ult:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: ret
+ %1 = fcmp ult float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ule:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: ret
+ %1 = fcmp ule float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_une:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: ret
+ %1 = fcmp une float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_uno(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_uno:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft0
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: ret
+ %1 = fcmp uno float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+define i32 @fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_true:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: addi a0, zero, 1
+; RV32IF-NEXT: ret
+ %1 = fcmp true float %a, %b
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
Added: llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll?rev=328104&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll Wed Mar 21 08:11:02 2018
@@ -0,0 +1,304 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32IF %s
+
+define float @select_fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_false:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: mv a0, a1
+; RV32IF-NEXT: ret
+ %1 = fcmp false float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_oeq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft1
+; RV32IF-NEXT: bnez a0, .LBB1_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB1_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp oeq float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ogt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB2_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB2_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ogt float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_oge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB3_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB3_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp oge float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_olt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: flt.s a0, ft0, ft1
+; RV32IF-NEXT: bnez a0, .LBB4_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB4_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp olt float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ole:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fle.s a0, ft0, ft1
+; RV32IF-NEXT: bnez a0, .LBB5_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB5_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ole float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_one(float %a, float %b) nounwind {
+; TODO: feq.s+sltiu+bne sequence could be optimised
+; RV32IF-LABEL: select_fcmp_one:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: feq.s a1, ft0, ft1
+; RV32IF-NEXT: not a1, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: bnez a0, .LBB6_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB6_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp one float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ord:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB7_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB7_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ord float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ueq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: feq.s a1, ft0, ft1
+; RV32IF-NEXT: or a0, a1, a0
+; RV32IF-NEXT: bnez a0, .LBB8_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB8_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ueq float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ugt:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fle.s a0, ft0, ft1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB9_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB9_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ugt float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_uge:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: flt.s a0, ft0, ft1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB10_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB10_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp uge float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ult:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fle.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB11_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB11_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ult float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ule:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: flt.s a0, ft1, ft0
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB12_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB12_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp ule float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_une:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: feq.s a0, ft0, ft1
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: bnez a0, .LBB13_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB13_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp une float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_uno(float %a, float %b) nounwind {
+; TODO: sltiu+bne could be optimized
+; RV32IF-LABEL: select_fcmp_uno:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a0
+; RV32IF-NEXT: fmv.w.x ft1, a1
+; RV32IF-NEXT: feq.s a0, ft1, ft1
+; RV32IF-NEXT: feq.s a1, ft0, ft0
+; RV32IF-NEXT: and a0, a1, a0
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: bnez a0, .LBB14_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: fmv.s ft0, ft1
+; RV32IF-NEXT: .LBB14_2:
+; RV32IF-NEXT: fmv.x.w a0, ft0
+; RV32IF-NEXT: ret
+ %1 = fcmp uno float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+define float @select_fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_true:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: ret
+ %1 = fcmp true float %a, %b
+ %2 = select i1 %1, float %a, float %b
+ ret float %2
+}
+
+; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
+define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
+; RV32IF-LABEL: i32_select_fcmp_oeq:
+; RV32IF: # %bb.0:
+; RV32IF-NEXT: fmv.w.x ft0, a1
+; RV32IF-NEXT: fmv.w.x ft1, a0
+; RV32IF-NEXT: feq.s a0, ft1, ft0
+; RV32IF-NEXT: bnez a0, .LBB16_2
+; RV32IF-NEXT: # %bb.1:
+; RV32IF-NEXT: mv a2, a3
+; RV32IF-NEXT: .LBB16_2:
+; RV32IF-NEXT: mv a0, a2
+; RV32IF-NEXT: ret
+ %1 = fcmp oeq float %a, %b
+ %2 = select i1 %1, i32 %c, i32 %d
+ ret i32 %2
+}
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