[PATCH] D44704: [GlobalISel][X86][ARM] Relaxing type constraints on G_SHL and friends

Roman Tereshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Mar 20 14:40:47 PDT 2018


rtereshin created this revision.
rtereshin added reviewers: qcolombet, dsanders, aditya_nandakumar, bogner, volkan, rovka.
Herald added subscribers: kristof.beyls, nhaehnle, arsenm.

Apparently, already written SelectionDAG ISel's selection patterns like the following X86-pattern

  // x << (32 - y) >> (32 - y)
  def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))),
                 (i8 (trunc (sub 32, GR32:$lz)))),
            (BZHI32rr GR32:$src, GR32:$lz)>;
  def : Pat<(srl (shl (loadi32 addr:$src), (i8 (trunc (sub 32, GR32:$lz)))),
                 (i8 (trunc (sub 32, GR32:$lz)))),
            (BZHI32rm addr:$src, GR32:$lz)>;

don't require shifts to have the same type for src/dst and the shift amount, which is not consistent with currently existing type constraints on the corresponding generic opcodes, which are, most likely, inspired by their LLVM IR counterparts.

As we import SelectionDAG ISel's rules (instructions and patterns) semi-automatically to GlobalISel, this discrepancy causes a few issues:

1. Testgen generates tests that don't really reflect the patterns as it utilizes broken type constraints (https://reviews.llvm.org/D43962)
2. MatchTable-optimizations remove too many type checks assuming the broken type constraints (https://reviews.llvm.org/D44700)

This patch relaxes the type constraints.


Repository:
  rL LLVM

https://reviews.llvm.org/D44704

Files:
  include/llvm/Target/GenericOpcodes.td
  lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp


Index: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -134,6 +134,7 @@
   setAction({G_SELECT, 1, S1}, Legal);
 
   setAction({G_SHL, S32}, Legal);
+  setAction({G_SHL, 1, S32}, Legal);
 
 
   // FIXME: When RegBankSelect inserts copies, it will only create new
Index: include/llvm/Target/GenericOpcodes.td
===================================================================
--- include/llvm/Target/GenericOpcodes.td
+++ include/llvm/Target/GenericOpcodes.td
@@ -213,21 +213,21 @@
 // Generic left-shift.
 def G_SHL : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src1, type0:$src2);
+  let InOperandList = (ins type0:$src1, type1:$src2);
   let hasSideEffects = 0;
 }
 
 // Generic logical right-shift.
 def G_LSHR : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src1, type0:$src2);
+  let InOperandList = (ins type0:$src1, type1:$src2);
   let hasSideEffects = 0;
 }
 
 // Generic arithmetic right-shift.
 def G_ASHR : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins type0:$src1, type0:$src2);
+  let InOperandList = (ins type0:$src1, type1:$src2);
   let hasSideEffects = 0;
 }
 


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