[PATCH] D44678: [ARM] Do not convert some vmov instructions

[Mikhail Maltsev via Phabricator via llvm-commits]

miyuki created this revision.
miyuki added reviewers: rengolin, olista01.
Herald added subscribers: kristof.beyls, javed.absar.

Patch https://reviews.llvm.org/D44467 implements conversion of invalid
vmov instructions into valid ones. It turned out that some valid
instructions also get converted, for example

  vmov.i64 d2, #0xff00ff00ff00ff00 ->
  vmov.i16 d2, #0xff00

Such behavior is incorrect because according to the ARM ARM section
https://reviews.llvm.org/F2.7.7 Modified immediate constants in T32 and A32 Advanced SIMD
instructions, "On assembly, the data type must be matched in the table
if possible."

This patch fixes the isNEONmovReplicate check so that the above
instruction is not modified any more.


https://reviews.llvm.org/D44678

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  test/MC/ARM/vmov-vmvn-replicate.s


Index: test/MC/ARM/vmov-vmvn-replicate.s
===================================================================
--- test/MC/ARM/vmov-vmvn-replicate.s
+++ test/MC/ARM/vmov-vmvn-replicate.s
@@ -23,6 +23,8 @@
 @ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
 @ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
 
+        vmov.i64        d2, #0xff00ff00ff00ff00
+        vmov.i64        q2, #0xff00ff00ff00ff00
         vmov.i64        d2, #0x00a500a500a500a5
         vmov.i64        q2, #0x00a500a500a500a5
         vmov.i32        d2, #0x00a500a5
@@ -32,6 +34,8 @@
         vmov.i32        d2, #0xa500a500
         vmov.i32        q2, #0xa500a500
 
+@ CHECK: vmov.i64 d2, #0xff00ff00ff00ff00 @ encoding: [0x3a,0x2e,0x82,0xf3]
+@ CHECK: vmov.i64 q2, #0xff00ff00ff00ff00 @ encoding: [0x7a,0x4e,0x82,0xf3]
 @ CHECK: vmov.i16 d2, #0xa5 @ encoding: [0x15,0x28,0x82,0xf3]
 @ CHECK: vmov.i16 q2, #0xa5 @ encoding: [0x55,0x48,0x82,0xf3]
 @ CHECK: vmov.i16 d2, #0xa5 @ encoding: [0x15,0x28,0x82,0xf3]
Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1868,8 +1868,7 @@
            ((Value & 0xffffffffff00ffff) == 0xffff);
   }
 
-  bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv,
-                       bool AllowMinusOne) const {
+  bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
     assert((Width == 8 || Width == 16 || Width == 32) &&
            "Invalid element width");
     assert(NumElems * Width <= 64 && "Invalid result width");
@@ -1888,8 +1887,6 @@
 
     uint64_t Mask = (1ull << Width) - 1;
     uint64_t Elem = Value & Mask;
-    if (!AllowMinusOne && Elem == Mask)
-      return false;
     if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
       return false;
     if (Width == 32 && !isValidNEONi32vmovImm(Elem))
@@ -1904,7 +1901,7 @@
   }
 
   bool isNEONByteReplicate(unsigned NumBytes) const {
-    return isNEONReplicate(8, NumBytes, false, true);
+    return isNEONReplicate(8, NumBytes, false);
   }
 
   static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
@@ -1918,14 +1915,15 @@
   template<unsigned FromW, unsigned ToW>
   bool isNEONmovReplicate() const {
     checkNeonReplicateArgs(FromW, ToW);
-    bool AllowMinusOne = ToW != 64;
-    return isNEONReplicate(FromW, ToW / FromW, false, AllowMinusOne);
+    if (ToW == 64 && isNEONi64splat())
+      return false;
+    return isNEONReplicate(FromW, ToW / FromW, false);
   }
 
   template<unsigned FromW, unsigned ToW>
   bool isNEONinvReplicate() const {
     checkNeonReplicateArgs(FromW, ToW);
-    return isNEONReplicate(FromW, ToW / FromW, true, true);
+    return isNEONReplicate(FromW, ToW / FromW, true);
   }
 
   bool isNEONi32vmov() const {


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