[llvm] r327874 - [X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 19 10:58:41 PDT 2018
Author: ctopper
Date: Mon Mar 19 10:58:41 2018
New Revision: 327874
URL: http://llvm.org/viewvc/llvm-project?rev=327874&view=rev
Log:
[X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=327874&r1=327873&r2=327874&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Mar 19 10:58:41 2018
@@ -840,8 +840,8 @@ def: InstRW<[BWWriteResGroup9], (instreg
def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
-def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)rr")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=327874&r1=327873&r2=327874&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Mar 19 10:58:41 2018
@@ -1256,8 +1256,8 @@ def: InstRW<[HWWriteResGroup10], (instre
def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
-def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
+def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=327874&r1=327873&r2=327874&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Mar 19 10:58:41 2018
@@ -649,8 +649,8 @@ def: InstRW<[SBWriteResGroup6], (instreg
def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "TEST8i8")>;
-def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
+def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=327874&r1=327873&r2=327874&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Mar 19 10:58:41 2018
@@ -846,8 +846,8 @@ def: InstRW<[SKLWriteResGroup10], (instr
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=327874&r1=327873&r2=327874&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Mar 19 10:58:41 2018
@@ -1276,8 +1276,8 @@ def: InstRW<[SKXWriteResGroup10], (instr
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)i")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)i")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
More information about the llvm-commits
mailing list