[llvm] r327872 - [X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. Correct SchedRW and itinerary for MOV32ri64.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Mon Mar 19 10:46:59 2018
New Revision: 327872

URL: http://llvm.org/viewvc/llvm-project?rev=327872&view=rev
Log:
[X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. Correct SchedRW and itinerary for MOV32ri64.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
    llvm/trunk/lib/Target/X86/X86SchedHaswell.td
    llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=327872&r1=327871&r2=327872&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Mon Mar 19 10:46:59 2018
@@ -318,9 +318,9 @@ def MOV64ImmSExti8 : I<0, Pseudo, (outs
 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
 // that would make it more difficult to rematerialize.
 let isReMaterializable = 1, isAsCheapAsAMove = 1,
-    isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteALU] in
+    isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
 def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", [],
-                  IIC_ALU_NONMEM>;
+                  IIC_MOV>;
 
 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
 // actually the zero-extension of a 32-bit constant and for labels in the

Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=327872&r1=327871&r2=327872&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Mar 19 10:46:59 2018
@@ -816,7 +816,7 @@ def: InstRW<[BWWriteResGroup9], (instreg
 def: InstRW<[BWWriteResGroup9], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[BWWriteResGroup9], (instregex "LAHF")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr8")>;

Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=327872&r1=327871&r2=327872&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Mar 19 10:46:59 2018
@@ -598,9 +598,8 @@ def HWWriteResGroup0_2 : SchedWriteRes<[
 def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64to64rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVQ64rm")>;
-def: InstRW<[HWWriteResGroup0_2], (instregex "MOV(16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup0_2], (instregex "MOV(8|16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOV64toPQIrm")>;
-def: InstRW<[HWWriteResGroup0_2], (instregex "MOV8rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVDDUPrm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVDI2PDIrm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVQI2PQIrm")>;
@@ -1233,7 +1232,7 @@ def: InstRW<[HWWriteResGroup10], (instre
 def: InstRW<[HWWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri")>;
+def: InstRW<[HWWriteResGroup10], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;

Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=327872&r1=327871&r2=327872&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Mar 19 10:46:59 2018
@@ -626,7 +626,7 @@ def: InstRW<[SBWriteResGroup6], (instreg
 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>;
+def: InstRW<[SBWriteResGroup6], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>;

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=327872&r1=327871&r2=327872&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Mar 19 10:46:59 2018
@@ -822,7 +822,7 @@ def: InstRW<[SKLWriteResGroup10], (instr
 def: InstRW<[SKLWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "LAHF")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=327872&r1=327871&r2=327872&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Mar 19 10:46:59 2018
@@ -1252,7 +1252,7 @@ def: InstRW<[SKXWriteResGroup10], (instr
 def: InstRW<[SKXWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "LAHF")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;