[PATCH] D44506: [Power9]Legalize and emit code for quad-precision add/div/mul/sub

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM. Please add the requested test case on the commit - no need for an additional review.



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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2898
   def : Pat<(v2f64 (int_ppc_vsx_lxvd2x xoaddr:$src)), (LXVX xoaddr:$src)>;
+  def : Pat<(f128  (nonQuadwOffsetLoad xoaddr:$src)),
+            (COPY_TO_REGCLASS (LXVX xoaddr:$src), VRRC)>;
----------------
Can you please add an additional test case for this. We want to make sure no future patches break it. Something along these lines should suffice:
```
define void @test(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
entry:
  %add.ptr = getelementptr inbounds i8, i8* %PtrC, i64 4
  %0 = bitcast i8* %add.ptr to fp128*
  %1 = load fp128, fp128* %0, align 16
  %2 = bitcast fp128* %PtrF to i8*
  %add.ptr1 = getelementptr inbounds i8, i8* %2, i64 8
  %3 = bitcast i8* %add.ptr1 to fp128*
  store fp128 %1, fp128* %3, align 16
  ret void
}
```

We need to make sure we emit `LXVX` and `STXVX` here rather than their D-Form analogs.


https://reviews.llvm.org/D44506