[llvm] r327726 - [AMDGPU] Supported ds_write_b128 generation.
Farhana Aleen via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 16 11:12:00 PDT 2018
Author: faaleen
Date: Fri Mar 16 11:12:00 2018
New Revision: 327726
URL: http://llvm.org/viewvc/llvm-project?rev=327726&view=rev
Log:
[AMDGPU] Supported ds_write_b128 generation.
Summary: This is a follow-on patch of https://reviews.llvm.org/D44210
Author: FarhanaAleen
Reviewed By: msearles
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44319
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/test/CodeGen/AMDGPU/load-local-f32.ll
llvm/trunk/test/CodeGen/AMDGPU/load-local-f64.ll
llvm/trunk/test/CodeGen/AMDGPU/load-local-i16.ll
llvm/trunk/test/CodeGen/AMDGPU/load-local-i32.ll
llvm/trunk/test/CodeGen/AMDGPU/load-local-i64.ll
llvm/trunk/test/CodeGen/AMDGPU/load-local-i8.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Fri Mar 16 11:12:00 2018
@@ -383,6 +383,9 @@ def store_align8_local : Aligned8Bytes <
(ops node:$val, node:$ptr), (store_local node:$val, node:$ptr)
>;
+def store_align16_local : Aligned16Bytes <
+ (ops node:$val, node:$ptr), (store_local node:$val, node:$ptr)
+>;
def load_flat : FlatLoad <load>;
def az_extloadi8_flat : FlatLoad <az_extloadi8>;
Modified: llvm/trunk/lib/Target/AMDGPU/DSInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/DSInstructions.td?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/DSInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/DSInstructions.td Fri Mar 16 11:12:00 2018
@@ -719,6 +719,8 @@ def : DS64Bit4ByteAlignedWritePat<DS_WRI
let AddedComplexity = 100 in {
defm : DSWritePat_mc <DS_WRITE_B64, v2i32, "store_align8_local">;
+defm : DSWritePat_mc <DS_WRITE_B128, v4i32, "store_align16_local">;
+
} // End AddedComplexity = 100
class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Fri Mar 16 11:12:00 2018
@@ -5833,14 +5833,14 @@ SDValue SITargetLowering::LowerSTORE(SDV
llvm_unreachable("unsupported private_element_size");
}
} else if (AS == AMDGPUASI.LOCAL_ADDRESS) {
+ // Use ds_write_b128 if possible.
+ if (Subtarget->useDS128(EnableDS128) && Store->getAlignment() >= 16 &&
+ VT.getStoreSize() == 16)
+ return SDValue();
+
if (NumElements > 2)
return SplitVectorStore(Op, DAG);
-
- if (NumElements == 2)
- return Op;
-
- // If properly aligned, if we split we might be able to use ds_write_b64.
- return SplitVectorStore(Op, DAG);
+ return SDValue();
} else {
llvm_unreachable("unhandled address space");
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Fri Mar 16 11:12:00 2018
@@ -457,11 +457,16 @@ def store_glue_align8 : Aligned8Bytes <
(ops node:$value, node:$ptr), (store_glue node:$value, node:$ptr)
>;
+def store_glue_align16 : Aligned16Bytes <
+ (ops node:$value, node:$ptr), (store_glue node:$value, node:$ptr)
+>;
+
def store_local_m0 : StoreFrag<store_glue>, LocalAddress;
def truncstorei8_local_m0 : StoreFrag<truncstorei8_glue>, LocalAddress;
def truncstorei16_local_m0 : StoreFrag<truncstorei16_glue>, LocalAddress;
def store_align8_local_m0 : StoreFrag<store_glue_align8>, LocalAddress;
+def store_align16_local_m0 : StoreFrag<store_glue_align16>, LocalAddress;
def si_setcc_uniform : PatFrag <
(ops node:$lhs, node:$rhs, node:$cond),
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-local-f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-local-f32.ll?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-local-f32.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-local-f32.ll Fri Mar 16 11:12:00 2018
@@ -2,7 +2,7 @@
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
-; Testing for ds_read_128
+; Testing for ds_read/write_128
; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-ds128 < %s | FileCheck -check-prefixes=SI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
@@ -127,17 +127,22 @@ entry:
ret void
}
-; Tests if ds_read_b128 gets generated for the 16 byte aligned load.
+; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
; FUNC-LABEL: {{^}}local_v4f32_to_128:
+
; SI-NOT: ds_read_b128
+; SI-NOT: ds_write_b128
+
; CIVI: ds_read_b128
+; CIVI: ds_write_b128
+
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
define amdgpu_kernel void @local_v4f32_to_128(<4 x float> addrspace(3)* %out, <4 x float> addrspace(3)* %in) {
%ld = load <4 x float>, <4 x float> addrspace(3)* %in, align 16
- store <4 x float> %ld, <4 x float> addrspace(3)* %out
+ store <4 x float> %ld, <4 x float> addrspace(3)* %out, align 16
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-local-f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-local-f64.ll?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-local-f64.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-local-f64.ll Fri Mar 16 11:12:00 2018
@@ -176,7 +176,10 @@ entry:
; Tests if ds_read_b128 gets generated for the 16 byte aligned load.
; FUNC-LABEL: {{^}}local_load_v2f64_to_128:
+
; CIVI: ds_read_b128
+; CIVI: ds_write_b128
+
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
@@ -184,7 +187,7 @@ entry:
define amdgpu_kernel void @local_load_v2f64_to_128(<2 x double> addrspace(3)* %out, <2 x double> addrspace(3)* %in) {
entry:
%ld = load <2 x double>, <2 x double> addrspace(3)* %in, align 16
- store <2 x double> %ld, <2 x double> addrspace(3)* %out
+ store <2 x double> %ld, <2 x double> addrspace(3)* %out, align 16
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-local-i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-local-i16.ll?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-local-i16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-local-i16.ll Fri Mar 16 11:12:00 2018
@@ -3,7 +3,7 @@
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GFX89,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; Testing for ds_read_b128
+; Testing for ds_read/write_b128
; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
@@ -939,17 +939,22 @@ define amdgpu_kernel void @local_sextloa
; ret void
; }
-; Tests if ds_read_b128 gets generated for the 16 byte aligned load.
+; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
; FUNC-LABEL: {{^}}local_v8i16_to_128:
+
; SI-NOT: ds_read_b128
+; SI-NOT: ds_write_b128
+
; CIVI: ds_read_b128
+; CIVI: ds_write_b128
+
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
define amdgpu_kernel void @local_v8i16_to_128(<8 x i16> addrspace(3)* %out, <8 x i16> addrspace(3)* %in) {
%ld = load <8 x i16>, <8 x i16> addrspace(3)* %in, align 16
- store <8 x i16> %ld, <8 x i16> addrspace(3)* %out
+ store <8 x i16> %ld, <8 x i16> addrspace(3)* %out, align 16
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-local-i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-local-i32.ll?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-local-i32.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-local-i32.ll Fri Mar 16 11:12:00 2018
@@ -3,7 +3,7 @@
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; Testing for ds_read_128
+; Testing for ds_read/write_128
; RUN: llc -march=amdgcn -mcpu=tahiti -amdgpu-ds128 < %s | FileCheck -check-prefixes=SI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
@@ -180,17 +180,22 @@ define amdgpu_kernel void @local_sextloa
ret void
}
-; Tests if ds_read_b128 gets generated for the 16 byte aligned load.
+; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
; FUNC-LABEL: {{^}}local_v4i32_to_128:
+
; SI-NOT: ds_read_b128
+; SI-NOT: ds_write_b128
+
; CIVI: ds_read_b128
+; CIVI: ds_write_b128
+
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
define amdgpu_kernel void @local_v4i32_to_128(<4 x i32> addrspace(3)* %out, <4 x i32> addrspace(3)* %in) {
%ld = load <4 x i32>, <4 x i32> addrspace(3)* %in, align 16
- store <4 x i32> %ld, <4 x i32> addrspace(3)* %out
+ store <4 x i32> %ld, <4 x i32> addrspace(3)* %out, align 16
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-local-i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-local-i64.ll?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-local-i64.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-local-i64.ll Fri Mar 16 11:12:00 2018
@@ -4,7 +4,7 @@
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s
-; Testing for ds_read_b128
+; Testing for ds_read/write_b128
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
@@ -40,13 +40,16 @@ entry:
ret void
}
-; Tests if ds_read_b128 gets generated for the 16 byte aligned load.
+; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
; FUNC-LABEL: {{^}}local_load_v2i64_to_128:
+
; CIVI: ds_read_b128
+; CIVI: ds_write_b128
+
define amdgpu_kernel void @local_load_v2i64_to_128(<2 x i64> addrspace(3)* %out, <2 x i64> addrspace(3)* %in) {
entry:
- %ld = load <2 x i64>, <2 x i64> addrspace(3)* %in
- store <2 x i64> %ld, <2 x i64> addrspace(3)* %out
+ %ld = load <2 x i64>, <2 x i64> addrspace(3)* %in, align 16
+ store <2 x i64> %ld, <2 x i64> addrspace(3)* %out, align 16
ret void
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-local-i8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-local-i8.ll?rev=327726&r1=327725&r2=327726&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-local-i8.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-local-i8.ll Fri Mar 16 11:12:00 2018
@@ -3,7 +3,7 @@
; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; Testing for ds_read_b128
+; Testing for ds_read/write_b128
; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
@@ -1024,17 +1024,22 @@ define amdgpu_kernel void @local_sextloa
; ret void
; }
-; Tests if ds_read_b128 gets generated for the 16 byte aligned load.
+; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
; FUNC-LABEL: {{^}}local_v16i8_to_128:
+
; SI-NOT: ds_read_b128
+; SI-NOT: ds_write_b128
+
; CIVI: ds_read_b128
+; CIVI: ds_write_b128
+
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
define amdgpu_kernel void @local_v16i8_to_128(<16 x i8> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) {
%ld = load <16 x i8>, <16 x i8> addrspace(3)* %in, align 16
- store <16 x i8> %ld, <16 x i8> addrspace(3)* %out
+ store <16 x i8> %ld, <16 x i8> addrspace(3)* %out, align 16
ret void
}
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