[llvm] r327706 - [X86][Btver2] Add correct lzcnt/tzcnt/popcnt schedule costs

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 16 06:43:55 PDT 2018


Author: rksimon
Date: Fri Mar 16 06:43:55 2018
New Revision: 327706

URL: http://llvm.org/viewvc/llvm-project?rev=327706&view=rev
Log:
[X86][Btver2] Add correct lzcnt/tzcnt/popcnt schedule costs

Don't use WriteIMul defaults

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
    llvm/trunk/test/CodeGen/X86/bmi-schedule.ll
    llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll
    llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=327706&r1=327705&r2=327706&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Fri Mar 16 06:43:55 2018
@@ -129,6 +129,29 @@ def  : WriteRes<WriteIMulH, [JALU1]> {
 // FIXME: SAGU 3-operand LEA
 def : WriteRes<WriteLEA, [JALU01]>;
 
+// FIXME: Why do bitcounts use WriteIMul?
+def JWriteLZCNT : SchedWriteRes<[JALU01]> {
+  let Latency = 1;
+}
+def JWriteLZCNTLd : SchedWriteRes<[JLAGU, JALU01]> {
+  let Latency = 4;
+}
+def : InstRW<[JWriteLZCNT], (instrs LZCNT16rr, LZCNT32rr, LZCNT64rr,
+                                    POPCNT16rr, POPCNT32rr, POPCNT64rr)>;
+def : InstRW<[JWriteLZCNTLd], (instrs LZCNT16rm, LZCNT32rm, LZCNT64rm,
+                                    POPCNT16rm, POPCNT32rm, POPCNT64rm)>;
+
+def JWriteTZCNT : SchedWriteRes<[JALU01]> {
+  let Latency = 2;
+  let ResourceCycles = [2];
+}
+def JWriteTZCNTLd : SchedWriteRes<[JLAGU, JALU01]> {
+  let Latency = 5;
+  let ResourceCycles = [1, 2];
+}
+def : InstRW<[JWriteTZCNT], (instrs TZCNT16rr, TZCNT32rr, TZCNT64rr)>;
+def : InstRW<[JWriteTZCNTLd], (instrs TZCNT16rm, TZCNT32rm, TZCNT64rm)>;
+
 def JWriteIDiv8 : SchedWriteRes<[JALU1, JDiv]> {
   let Latency = 12;
   let ResourceCycles = [1, 12];

Modified: llvm/trunk/test/CodeGen/X86/bmi-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi-schedule.ll?rev=327706&r1=327705&r2=327706&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi-schedule.ll Fri Mar 16 06:43:55 2018
@@ -610,8 +610,8 @@ define i16 @test_cttz_i16(i16 zeroext %a
 ;
 ; BTVER2-LABEL: test_cttz_i16:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    tzcntw (%rsi), %cx # sched: [6:1.00]
-; BTVER2-NEXT:    tzcntw %di, %ax # sched: [3:1.00]
+; BTVER2-NEXT:    tzcntw (%rsi), %cx # sched: [5:1.00]
+; BTVER2-NEXT:    tzcntw %di, %ax # sched: [2:1.00]
 ; BTVER2-NEXT:    orl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    # kill: def $ax killed $ax killed $eax
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
@@ -662,8 +662,8 @@ define i32 @test_cttz_i32(i32 %a0, i32 *
 ;
 ; BTVER2-LABEL: test_cttz_i32:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    tzcntl (%rsi), %ecx # sched: [6:1.00]
-; BTVER2-NEXT:    tzcntl %edi, %eax # sched: [3:1.00]
+; BTVER2-NEXT:    tzcntl (%rsi), %ecx # sched: [5:1.00]
+; BTVER2-NEXT:    tzcntl %edi, %eax # sched: [2:1.00]
 ; BTVER2-NEXT:    orl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
@@ -712,8 +712,8 @@ define i64 @test_cttz_i64(i64 %a0, i64 *
 ;
 ; BTVER2-LABEL: test_cttz_i64:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    tzcntq (%rsi), %rcx # sched: [6:1.00]
-; BTVER2-NEXT:    tzcntq %rdi, %rax # sched: [3:1.00]
+; BTVER2-NEXT:    tzcntq (%rsi), %rcx # sched: [5:1.00]
+; BTVER2-NEXT:    tzcntq %rdi, %rax # sched: [2:1.00]
 ; BTVER2-NEXT:    orq %rcx, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;

Modified: llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll?rev=327706&r1=327705&r2=327706&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lzcnt-schedule.ll Fri Mar 16 06:43:55 2018
@@ -42,8 +42,8 @@ define i16 @test_ctlz_i16(i16 zeroext %a
 ;
 ; BTVER2-LABEL: test_ctlz_i16:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    lzcntw (%rsi), %cx # sched: [6:1.00]
-; BTVER2-NEXT:    lzcntw %di, %ax # sched: [3:1.00]
+; BTVER2-NEXT:    lzcntw (%rsi), %cx # sched: [4:1.00]
+; BTVER2-NEXT:    lzcntw %di, %ax # sched: [1:0.50]
 ; BTVER2-NEXT:    orl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    # kill: def $ax killed $ax killed $eax
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
@@ -94,8 +94,8 @@ define i32 @test_ctlz_i32(i32 %a0, i32 *
 ;
 ; BTVER2-LABEL: test_ctlz_i32:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    lzcntl (%rsi), %ecx # sched: [6:1.00]
-; BTVER2-NEXT:    lzcntl %edi, %eax # sched: [3:1.00]
+; BTVER2-NEXT:    lzcntl (%rsi), %ecx # sched: [4:1.00]
+; BTVER2-NEXT:    lzcntl %edi, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    orl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
@@ -144,8 +144,8 @@ define i64 @test_ctlz_i64(i64 %a0, i64 *
 ;
 ; BTVER2-LABEL: test_ctlz_i64:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    lzcntq (%rsi), %rcx # sched: [6:1.00]
-; BTVER2-NEXT:    lzcntq %rdi, %rax # sched: [3:1.00]
+; BTVER2-NEXT:    lzcntq (%rsi), %rcx # sched: [4:1.00]
+; BTVER2-NEXT:    lzcntq %rdi, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    orq %rcx, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;

Modified: llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll?rev=327706&r1=327705&r2=327706&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/popcnt-schedule.ll Fri Mar 16 06:43:55 2018
@@ -62,8 +62,8 @@ define i16 @test_ctpop_i16(i16 zeroext %
 ;
 ; BTVER2-LABEL: test_ctpop_i16:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    popcntw (%rsi), %cx # sched: [8:1.00]
-; BTVER2-NEXT:    popcntw %di, %ax # sched: [3:1.00]
+; BTVER2-NEXT:    popcntw (%rsi), %cx # sched: [4:1.00]
+; BTVER2-NEXT:    popcntw %di, %ax # sched: [1:0.50]
 ; BTVER2-NEXT:    orl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    # kill: def $ax killed $ax killed $eax
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
@@ -128,8 +128,8 @@ define i32 @test_ctpop_i32(i32 %a0, i32
 ;
 ; BTVER2-LABEL: test_ctpop_i32:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    popcntl (%rsi), %ecx # sched: [8:1.00]
-; BTVER2-NEXT:    popcntl %edi, %eax # sched: [3:1.00]
+; BTVER2-NEXT:    popcntl (%rsi), %ecx # sched: [4:1.00]
+; BTVER2-NEXT:    popcntl %edi, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    orl %ecx, %eax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
@@ -192,8 +192,8 @@ define i64 @test_ctpop_i64(i64 %a0, i64
 ;
 ; BTVER2-LABEL: test_ctpop_i64:
 ; BTVER2:       # %bb.0:
-; BTVER2-NEXT:    popcntq (%rsi), %rcx # sched: [8:1.00]
-; BTVER2-NEXT:    popcntq %rdi, %rax # sched: [3:1.00]
+; BTVER2-NEXT:    popcntq (%rsi), %rcx # sched: [4:1.00]
+; BTVER2-NEXT:    popcntq %rdi, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    orq %rcx, %rax # sched: [1:0.50]
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;




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