[llvm] r327663 - [AArch64] Adjust the cost model for Exynos M3

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Thu Mar 15 13:37:32 2018
New Revision: 327663

URL: http://llvm.org/viewvc/llvm-project?rev=327663&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M3

Fix typo.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=327663&r1=327662&r2=327663&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Thu Mar 15 13:37:32 2018
@@ -112,8 +112,8 @@ def M3BranchLinkFastPred : SchedPredicat
 def M3ResetFastPred      : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
 def M3RotateFastPred     : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
                                              MI->getOpcode() == AArch64::EXTRXrri) &&
-                                            MI->getOperand(0).isReg() && MI->getOperand(1).isReg() &&
-                                            MI->getOperand(0).getReg() == MI->getOperand(1).getReg()}]>;
+                                            MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
+                                            MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
 def M3ShiftLeftFastPred  : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
 
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