[llvm] r327582 - [X86][Btver2] Add ResourceCycles and NumMicroOps overrides to scalar instructions. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Mar 14 14:55:54 2018
New Revision: 327582

URL: http://llvm.org/viewvc/llvm-project?rev=327582&view=rev
Log:
[X86][Btver2] Add ResourceCycles and NumMicroOps overrides to scalar instructions. NFCI.

Currently still use default values - this is setup for a future patch.

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=327582&r1=327581&r2=327582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Wed Mar 14 14:55:54 2018
@@ -76,14 +76,20 @@ def : ReadAdvance<ReadAfterLd, 3>;
 // folded loads.
 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
                             ProcResourceKind ExePort,
-                            int Lat> {
+                            int Lat, int Res = 1, int UOps = 1> {
   // Register variant is using a single cycle on ExePort.
-  def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
+  def : WriteRes<SchedRW, [ExePort]> {
+    let Latency = Lat;
+    let ResourceCycles = [Res];
+    let NumMicroOps = UOps;
+  }
 
   // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
   // latency.
   def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
     let Latency = !add(Lat, 3);
+    let ResourceCycles = [1, Res];
+    let NumMicroOps = UOps;
   }
 }