[PATCH] D44428: [X86][SSE] Treat (V)MOVAPD/(V)MOVUPD + (V)MOVAPS/(V)MOVUPS reg-reg instructions as moves not shuffles

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

I saw this on btver2 - MOVDQA is reported as using JALU0/JALU1 while MOVAPS/MOVAPD reports JFPU0/JFPU1. And it appears to be affecting a couple of other targets with non-exhaustive scheduler model overloads.

Note that this shouldn't t affect SB etc. as you've said it already has overloaded the schedules for reg-reg moves.

What we could do is start splitting vector/scalar moves/loads/stores but this patch was all that was necessary for the cases I saw.


Repository:
  rL LLVM

https://reviews.llvm.org/D44428