[llvm] r327403 - [mips] Fix the definitions of the EVA instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 13 07:39:44 PDT 2018
Author: sdardis
Date: Tue Mar 13 07:39:44 2018
New Revision: 327403
URL: http://llvm.org/viewvc/llvm-project?rev=327403&view=rev
Log:
[mips] Fix the definitions of the EVA instructions
Correct their availability to their respective ISAs.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D44209
Added:
llvm/trunk/test/MC/Mips/micromips-eva.s
llvm/trunk/test/MC/Mips/micromips32r6-eva.s
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/micromips-eva.mir
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
llvm/trunk/test/MC/Mips/micromips-control-instructions.s
llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s
llvm/trunk/test/MC/Mips/micromips/invalid.s
llvm/trunk/test/MC/Mips/micromips/valid.s
llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
llvm/trunk/test/MC/Mips/micromips32r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Tue Mar 13 07:39:44 2018
@@ -777,32 +777,50 @@ let DecoderNamespace = "MicroMips", Pred
def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
LW_FM_MM<0x3e>;
}
-
+}
+let DecoderNamespace = "MicroMips" in {
let DecoderMethod = "DecodeMemMMImm9" in {
def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
- POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
+ POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;
def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
- POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
- def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9,
- null_frag, II_LHE>,
- POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
- def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9,
- null_frag, II_LHUE>,
- POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
- def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9,
- null_frag, II_LWE>,
- POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
- def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9,
- null_frag, II_SBE>,
- POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
- def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9,
- null_frag, II_SHE>,
- POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
- def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9,
- null_frag, II_SWE>,
- POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
+ POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;
+ def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag,
+ II_LHE>,
+ POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA;
+ def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag,
+ II_LHUE>,
+ POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA;
+ def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag,
+ II_LWE>,
+ POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA;
+ def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag,
+ II_SBE>,
+ POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA;
+ def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag,
+ II_SHE>,
+ POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA;
+ def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,
+ II_SWE>,
+ POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA;
+ def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
+ II_LWLE>,
+ POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>,
+ ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
+ def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
+ II_LWRE>,
+ POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>,
+ ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
+ def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
+ II_SWLE>,
+ POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>,
+ ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
+ def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
+ II_SWRE>,
+ POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,
+ ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
}
-
+}
+let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
/// Load and Store Instructions - unaligned
@@ -814,18 +832,6 @@ let DecoderNamespace = "MicroMips", Pred
LWL_FM_MM<0x8>;
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>,
LWL_FM_MM<0x9>;
- let DecoderMethod = "DecodeMemMMImm9" in {
- def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
- II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
- def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
- II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
- def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
- II_SWLE>,
- POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
- def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
- II_SWRE>,
- POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
- }
/// Load and Store Instructions - multiple
def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>;
@@ -978,23 +984,30 @@ let DecoderNamespace = "MicroMips", Pred
/// Load-linked, Store-conditional
def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
-
- def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
- def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
-
+}
+let DecoderNamespace = "MicroMips" in {
+ def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
+ ISA_MICROMIPS, ASE_EVA;
+ def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
+ ISA_MICROMIPS, ASE_EVA;
+}
+let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
let DecoderMethod = "DecodeCacheOpMM" in {
def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
CACHE_PREF_FM_MM<0x08, 0x6>;
def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
CACHE_PREF_FM_MM<0x18, 0x2>;
}
-
+}
+let DecoderNamespace = "MicroMips" in {
let DecoderMethod = "DecodePrefeOpMM" in {
def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
- CACHE_PREFE_FM_MM<0x18, 0x2>;
+ CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
- CACHE_PREFE_FM_MM<0x18, 0x3>;
+ CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
}
+}
+let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>;
def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>;
def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>;
Modified: llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td Tue Mar 13 07:39:44 2018
@@ -95,6 +95,7 @@ class LOAD_LEFT_RIGHT_EVA_DESC_BASE<stri
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeMemEVA";
+ string BaseOpcode = instr_asm;
string Constraints = "$src = $rt";
bit canFoldAsLoad = 1;
InstrItinClass Itinerary = itin;
@@ -110,6 +111,7 @@ class STORE_LEFT_RIGHT_EVA_DESC_BASE<str
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeMemEVA";
+ string BaseOpcode = instr_asm;
InstrItinClass Itinerary = itin;
}
@@ -177,38 +179,32 @@ class PREFE_DESC : CACHEE_DESC_BASE<"p
//
//===----------------------------------------------------------------------===//
-/// Load and Store EVA Instructions
-def LBE : MMRel, LBE_ENC, LBE_DESC, ASE_EVA;
-def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ASE_EVA;
-def LHE : MMRel, LHE_ENC, LHE_DESC, ASE_EVA;
-def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ASE_EVA;
-let AdditionalPredicates = [NotInMicroMips] in {
-def LWE : MMRel, LWE_ENC, LWE_DESC, ASE_EVA;
-}
-def SBE : MMRel, SBE_ENC, SBE_DESC, ASE_EVA;
-def SHE : MMRel, SHE_ENC, SHE_DESC, ASE_EVA;
-let AdditionalPredicates = [NotInMicroMips] in {
-def SWE : MMRel, SWE_ENC, SWE_DESC, ASE_EVA;
-}
-
-/// load/store left/right EVA
let AdditionalPredicates = [NotInMicroMips] in {
-def LWLE : LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
-def LWRE : LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
-def SWLE : SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
-def SWRE : SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+ /// Load and Store EVA Instructions
+ def LBE : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def LHE : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def SBE : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def SHE : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def SWE : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA;
+
+ /// load/store left/right EVA
+ def LWLE : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+ def LWRE : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+ def SWLE : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+ def SWRE : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+
+ /// Load-linked EVA, Store-conditional EVA
+ def LLE : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def SCE : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA;
+
+ /// TLB invalidate instructions
+ def TLBINV : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA;
+ def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA;
+
+ /// EVA versions of cache and pref
+ def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA;
+ def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA;
}
-
-/// Load-linked EVA, Store-conditional EVA
-let AdditionalPredicates = [NotInMicroMips] in {
-def LLE : MMRel, LLE_ENC, LLE_DESC, ASE_EVA;
-def SCE : MMRel, SCE_ENC, SCE_DESC, ASE_EVA;
-}
-
-let AdditionalPredicates = [NotInMicroMips] in {
- def TLBINV : TLBINV_ENC, TLBINV_DESC, ASE_EVA;
- def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ASE_EVA;
-}
-
-def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ASE_EVA;
-def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ASE_EVA;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Mar 13 07:39:44 2018
@@ -235,7 +235,7 @@ def IsBE : Predicate<"!Subtar
def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
def HasEVA : Predicate<"Subtarget->hasEVA()">,
- AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
+ AssemblerPredicate<"FeatureEVA">;
def HasMSA : Predicate<"Subtarget->hasMSA()">,
AssemblerPredicate<"FeatureMSA">;
def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
Modified: llvm/trunk/test/CodeGen/Mips/micromips-eva.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-eva.mir?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-eva.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/micromips-eva.mir Tue Mar 13 07:39:44 2018
@@ -1,5 +1,5 @@
-# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips -start-after=expand-isel-pseudos \
-# RUN: -filetype obj %s -o - | llvm-objdump -d - | FileCheck %s
+# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \
+# RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
--- |
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Tue Mar 13 07:39:44 2018
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips \
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips,eva \
# RUN: | FileCheck %s
0xf9 0x4f # CHECK: addiusp -16
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Tue Mar 13 07:39:44 2018
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips \
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips,eva \
# RUN: | FileCheck %s
0x4f 0xf9 # CHECK: addiusp -16
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt Tue Mar 13 07:39:44 2018
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips,eva | FileCheck %s
0x6f 0x83 # CHECK: addiur1sp $7, 4
0x6f 0x7e # CHECK: addiur2 $6, $7, -1
Modified: llvm/trunk/test/MC/Mips/micromips-control-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-control-instructions.s?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-control-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-control-instructions.s Tue Mar 13 07:39:44 2018
@@ -39,15 +39,7 @@
# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
-# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
-# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
# CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
-# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
-# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
-# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
-# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
-# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c]
-# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -81,15 +73,7 @@
# CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c]
# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
-# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
-# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
# CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
-# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
-# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
-# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
-# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
-# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08]
-# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08]
sdbbp
sdbbp 34
@@ -118,12 +102,5 @@
tlbr
tlbwi
tlbwr
- prefe 1, 8($5)
- cachee 1, 8($5)
prefx 1, $3($5)
- swre $24, 5($3)
- swle $24, 5($3)
- lwre $24, 5($3)
- lwle $24, 2($4)
- lle $2, 8($4)
- sce $2, 8($4)
+
Added: llvm/trunk/test/MC/Mips/micromips-eva.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-eva.s?rev=327403&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-eva.s (added)
+++ llvm/trunk/test/MC/Mips/micromips-eva.s Tue Mar 13 07:39:44 2018
@@ -0,0 +1,96 @@
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mcpu=mips32r2 \
+# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EL %s
+# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mcpu=mips32r2 \
+# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EB %s
+# Check that the assembler can handle the documented syntax
+# for EVA instructions.
+#------------------------------------------------------------------------------
+# microMIPS EVA Instructions
+#------------------------------------------------------------------------------
+# Little endian
+#------------------------------------------------------------------------------
+# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWRE_MM
+# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWLE_MM
+# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWRE_MM
+# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWLE_MM
+# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHuE_M
+# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
+#------------------------------------------------------------------------------
+# Big endian
+#------------------------------------------------------------------------------
+# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWRE_MM
+# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWLE_MM
+# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWRE_MM
+# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWLE_MM
+# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHuE_MM
+# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
+
+ prefe 1, 8($5)
+ cachee 1, 8($5)
+ lle $2, 8($4)
+ sce $2, 8($4)
+ swre $24, 5($3)
+ swle $24, 5($3)
+ lwre $24, 5($3)
+ lwle $24, 2($4)
+ lhue $4, 8($2)
+ lbe $4, 8($2)
+ lbue $4, 8($2)
+ lhe $4, 8($2)
+ lwe $4, 8($2)
+ sbe $5, 8($4)
+ she $5, 8($4)
+ swe $5, 8($4)
+
Modified: llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-loadstore-instructions.s Tue Mar 13 07:39:44 2018
@@ -44,14 +44,6 @@
# CHECK-EL: swm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0xd0]
# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90]
# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
-# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
-# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
-# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
-# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
-# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
-# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
-# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
-# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -90,14 +82,6 @@
# CHECK-EB: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
-# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
-# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
-# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
-# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
-# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
-# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
-# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
-# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
lb $5, 8($4)
lbu $6, 8($4)
lh $2, 8($4)
@@ -133,11 +117,4 @@
swm $16, $17, 8($sp)
swp $16, 8($4)
lwp $16, 8($4)
- lhue $4, 8($2)
- lbe $4, 8($2)
- lbue $4, 8($2)
- lhe $4, 8($2)
- lwe $4, 8($2)
- sbe $5, 8($4)
- she $5, 8($4)
- swe $5, 8($4)
+
Modified: llvm/trunk/test/MC/Mips/micromips/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/invalid.s?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/invalid.s Tue Mar 13 07:39:44 2018
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
+# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips,eva 2>%t1
# RUN: FileCheck %s < %t1
addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
Modified: llvm/trunk/test/MC/Mips/micromips/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips/valid.s?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips/valid.s Tue Mar 13 07:39:44 2018
@@ -1,4 +1,4 @@
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips,eva | FileCheck %s
.set noat
addiusp -16 # CHECK: addiusp -16 # encoding: [0x4f,0xf9]
Added: llvm/trunk/test/MC/Mips/micromips32r6-eva.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6-eva.s?rev=327403&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6-eva.s (added)
+++ llvm/trunk/test/MC/Mips/micromips32r6-eva.s Tue Mar 13 07:39:44 2018
@@ -0,0 +1,76 @@
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mcpu=mips32r6 \
+# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EL %s
+# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mcpu=mips32r6 \
+# RUN: -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EB %s
+# Check that the assembler can handle the documented syntax
+# for EVA instructions.
+#------------------------------------------------------------------------------
+# microMIPS EVA Instructions
+#------------------------------------------------------------------------------
+# Little endian
+#------------------------------------------------------------------------------
+# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EL: lle $2, 8($4) # encoding: [0x44,0x60,0x08,0x6c]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EL: sce $2, 8($4) # encoding: [0x44,0x60,0x08,0xac]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EL: lhue $4, 8($2) # encoding: [0x82,0x60,0x08,0x62]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHuE_M
+# CHECK-EL: lbe $4, 8($2) # encoding: [0x82,0x60,0x08,0x68]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EL: lbue $4, 8($2) # encoding: [0x82,0x60,0x08,0x60]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EL: lhe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6a]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EL: lwe $4, 8($2) # encoding: [0x82,0x60,0x08,0x6e]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EL: sbe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xa8]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EL: she $5, 8($4) # encoding: [0xa4,0x60,0x08,0xaa]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EL: swe $5, 8($4) # encoding: [0xa4,0x60,0x08,0xae]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
+#------------------------------------------------------------------------------
+# Big endian
+#------------------------------------------------------------------------------
+# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EB: lle $2, 8($4) # encoding: [0x60,0x44,0x6c,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EB: sce $2, 8($4) # encoding: [0x60,0x44,0xac,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EB: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHuE_MM
+# CHECK-EB: lbe $4, 8($2) # encoding: [0x60,0x82,0x68,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EB: lbue $4, 8($2) # encoding: [0x60,0x82,0x60,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EB: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EB: lwe $4, 8($2) # encoding: [0x60,0x82,0x6e,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EB: sbe $5, 8($4) # encoding: [0x60,0xa4,0xa8,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EB: she $5, 8($4) # encoding: [0x60,0xa4,0xaa,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EB: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWE_MM
+
+ prefe 1, 8($5)
+ cachee 1, 8($5)
+ lle $2, 8($4)
+ sce $2, 8($4)
+ lhue $4, 8($2)
+ lbe $4, 8($2)
+ lbue $4, 8($2)
+ lhe $4, 8($2)
+ lwe $4, 8($2)
+ sbe $5, 8($4)
+ she $5, 8($4)
+ swe $5, 8($4)
+
Modified: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/invalid.s?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s Tue Mar 13 07:39:44 2018
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
+# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=+micromips,+eva 2>%t1
# RUN: FileCheck %s < %t1
addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
Modified: llvm/trunk/test/MC/Mips/micromips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=327403&r1=327402&r2=327403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/micromips32r6/valid.s Tue Mar 13 07:39:44 2018
@@ -68,9 +68,7 @@
lapc $7, 1048572 # CHECK: lapc $7, 1048572 # encoding: [0x78,0xe3,0xff,0xff]
lapc $7, -1048576 # CHECK: lapc $7, -1048576 # encoding: [0x78,0xe4,0x00,0x00]
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
- lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
- lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
@@ -148,7 +146,6 @@
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
- swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FADD_D64_MM
@@ -260,12 +257,7 @@
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
sb $4, 6($5) # CHECK: sb $4, 6($5) # encoding: [0x18,0x85,0x00,0x06]
- sbe $4, 6($5) # CHECK: sbe $4, 6($5) # encoding: [0x60,0x85,0xa8,0x06]
- sce $4, 6($5) # CHECK: sce $4, 6($5) # encoding: [0x60,0x85,0xac,0x06]
sh $4, 6($5) # CHECK: sh $4, 6($5) # encoding: [0x38,0x85,0x00,0x06]
- she $4, 6($5) # CHECK: she $4, 6($5) # encoding: [0x60,0x85,0xaa,0x06]
- lle $4, 6($5) # CHECK: lle $4, 6($5) # encoding: [0x60,0x85,0x6c,0x06]
- lwe $4, 6($5) # CHECK: lwe $4, 6($5) # encoding: [0x60,0x85,0x6e,0x06]
lw $4, 6($5) # CHECK: lw $4, 6($5) # encoding: [0xfc,0x85,0x00,0x06]
lui $6, 17767 # CHECK: lui $6, 17767 # encoding: [0x10,0xc0,0x45,0x67]
addu16 $6, $17, $4 # CHECK: addu16 $6, $17, $4 # encoding: [0x04,0xcc]
@@ -275,8 +267,6 @@
or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9]
sll16 $3, $6, 8 # CHECK: sll16 $3, $6, 8 # encoding: [0x25,0xe0]
srl16 $3, $6, 8 # CHECK: srl16 $3, $6, 8 # encoding: [0x25,0xe1]
- prefe 1, 8($5) # CHECK: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
- cachee 1, 8($5) # CHECK: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
teq $8, $9 # CHECK: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c]
teq $5, $7, 15 # CHECK: teq $5, $7, 15 # encoding: [0x00,0xe5,0xf0,0x3c]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x01,0x47,0x02,0x3c]
@@ -297,8 +287,6 @@
xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0xd8]
lb $4, 8($5) # CHECK: lb $4, 8($5) # encoding: [0x1c,0x85,0x00,0x08]
lbu $4, 8($5) # CHECK: lbu $4, 8($5) # encoding: [0x14,0x85,0x00,0x08]
- lbe $4, 8($5) # CHECK: lbe $4, 8($5) # encoding: [0x60,0x85,0x68,0x08]
- lbue $4, 8($5) # CHECK: lbue $4, 8($5) # encoding: [0x60,0x85,0x60,0x08]
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x54,0x82,0x00,0x20]
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