[PATCH] D44402: [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7463
+SDValue DAGCombiner::CombineZExtLogicopShiftLoad(SDNode *N) {
+  EVT VT = N->getValueType(0);
+
----------------
Assert that N is a zext?


================
Comment at: test/CodeGen/X86/zext-logicop-shift-load.ll:1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
----------------
You're missing test cases for SRL and OR, as well as non constant operand to the logic op. You could also test indexed and sext loads.


Repository:
  rL LLVM

https://reviews.llvm.org/D44402