[llvm] r327308 - [Hexagon] Counting leading/trailing bits is cheap

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Mon Mar 12 11:18:23 2018
New Revision: 327308

URL: http://llvm.org/viewvc/llvm-project?rev=327308&view=rev
Log:
[Hexagon] Counting leading/trailing bits is cheap

Added:
    llvm/trunk/test/CodeGen/Hexagon/countbits-basic.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=327308&r1=327307&r2=327308&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Mon Mar 12 11:18:23 2018
@@ -121,6 +121,10 @@ namespace HexagonISD {
     bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
     bool isTruncateFree(EVT VT1, EVT VT2) const override;
 
+    bool isCheapToSpeculateCttz() const override { return true; }
+    bool isCheapToSpeculateCtlz() const override { return true; }
+    bool isCtlzFast() const override { return true; }
+
     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 
     /// Return true if an FMA operation is faster than a pair of mul and add

Added: llvm/trunk/test/CodeGen/Hexagon/countbits-basic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/countbits-basic.ll?rev=327308&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/countbits-basic.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/countbits-basic.ll Mon Mar 12 11:18:23 2018
@@ -0,0 +1,75 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK: count_leading_0:
+; CHECK: cl0(r0)
+define i32 @count_leading_0(i32 %p) #0 {
+  %1 = call i32 @llvm.ctlz.i32(i32 %p, i1 false)
+  ret i32 %1
+}
+
+; CHECK: count_leading_0p:
+; CHECK: cl0(r1:0)
+define i32 @count_leading_0p(i64 %p) #0 {
+  %1 = call i64 @llvm.ctlz.i64(i64 %p, i1 false)
+  %2 = trunc i64 %1 to i32
+  ret i32 %2
+}
+
+; CHECK: count_leading_1:
+; CHECK: cl1(r0)
+define i32 @count_leading_1(i32 %p) #0 {
+  %1 = xor i32 %p, -1
+  %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false)
+  ret i32 %2
+}
+
+; CHECK: count_leading_1p:
+; CHECK: cl1(r1:0)
+define i32 @count_leading_1p(i64 %p) #0 {
+  %1 = xor i64 %p, -1
+  %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false)
+  %3 = trunc i64 %2 to i32
+  ret i32 %3
+}
+
+
+
+; CHECK: count_trailing_0:
+; CHECK: ct0(r0)
+define i32 @count_trailing_0(i32 %p) #0 {
+  %1 = call i32 @llvm.cttz.i32(i32 %p, i1 false)
+  ret i32 %1
+}
+
+; CHECK: count_trailing_0p:
+; CHECK: ct0(r1:0)
+define i32 @count_trailing_0p(i64 %p) #0 {
+  %1 = call i64 @llvm.cttz.i64(i64 %p, i1 false)
+  %2 = trunc i64 %1 to i32
+  ret i32 %2
+}
+
+; CHECK: count_trailing_1:
+; CHECK: ct1(r0)
+define i32 @count_trailing_1(i32 %p) #0 {
+  %1 = xor i32 %p, -1
+  %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false)
+  ret i32 %2
+}
+
+; CHECK: count_trailing_1p:
+; CHECK: ct1(r1:0)
+define i32 @count_trailing_1p(i64 %p) #0 {
+  %1 = xor i64 %p, -1
+  %2 = call i64 @llvm.cttz.i64(i64 %1, i1 false)
+  %3 = trunc i64 %2 to i32
+  ret i32 %3
+}
+
+declare i32 @llvm.ctlz.i32(i32, i1)
+declare i64 @llvm.ctlz.i64(i64, i1)
+declare i32 @llvm.cttz.i32(i32, i1)
+declare i64 @llvm.cttz.i64(i64, i1)
+
+attributes #0 = { nounwind "target-cpu"="hexagonva55" }
+