[llvm] r327306 - [X86][Btver2] FSqrt/FDiv reg-reg instructions don't use the AGU.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Mar 12 11:12:46 2018
New Revision: 327306

URL: http://llvm.org/viewvc/llvm-project?rev=327306&view=rev
Log:
[X86][Btver2] FSqrt/FDiv reg-reg instructions don't use the AGU.

I love you llvm-mca.

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=327306&r1=327305&r2=327306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Mon Mar 12 11:12:46 2018
@@ -211,18 +211,18 @@ defm : JWriteResFpuPair<WriteFBlend,
 defm : JWriteResFpuPair<WriteFVarBlend,  JFPU01,  2, 4, 3>;
 defm : JWriteResFpuPair<WriteFShuffle256, JFPU01, 1>;
 
-def : WriteRes<WriteFSqrt, [JFPU1, JLAGU, JFPM]> {
+def : WriteRes<WriteFSqrt, [JFPU1, JFPM]> {
   let Latency = 21;
-  let ResourceCycles = [1, 1, 21];
+  let ResourceCycles = [1, 21];
 }
 def : WriteRes<WriteFSqrtLd, [JFPU1, JLAGU, JFPM]> {
   let Latency = 26;
   let ResourceCycles = [1, 1, 21];
 }
 
-def : WriteRes<WriteFDiv, [JFPU1, JLAGU, JFPM]> {
+def : WriteRes<WriteFDiv, [JFPU1, JFPM]> {
   let Latency = 19;
-  let ResourceCycles = [1, 1, 19];
+  let ResourceCycles = [1, 19];
 }
 def : WriteRes<WriteFDivLd, [JFPU1, JLAGU, JFPM]> {
   let Latency = 24;