[llvm] r327299 - [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 12 10:29:24 PDT 2018
Author: dpreobra
Date: Mon Mar 12 10:29:24 2018
New Revision: 327299
URL: http://llvm.org/viewvc/llvm-project?rev=327299&view=rev
Log:
[AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction
See bug 36558: https://bugs.llvm.org/show_bug.cgi?id=36558
Differential Revision: https://reviews.llvm.org/D43950
Reviewers: artem.tamazov, arsenm
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
llvm/trunk/test/MC/AMDGPU/mubuf.s
llvm/trunk/test/MC/Disassembler/AMDGPU/mubuf_vi.txt
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=327299&r1=327298&r2=327299&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon Mar 12 10:29:24 2018
@@ -864,7 +864,7 @@ private:
unsigned& RegNum, unsigned& RegWidth,
unsigned *DwordRegIndex);
void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
- bool IsAtomic, bool IsAtomicReturn);
+ bool IsAtomic, bool IsAtomicReturn, bool IsLds = false);
void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
bool IsGdsHardcoded);
@@ -1093,6 +1093,7 @@ public:
void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
+ void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false, true); }
void cvtMtbuf(MCInst &Inst, const OperandVector &Operands);
AMDGPUOperand::Ptr defaultGLC() const;
@@ -4106,7 +4107,10 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defa
void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
const OperandVector &Operands,
- bool IsAtomic, bool IsAtomicReturn) {
+ bool IsAtomic,
+ bool IsAtomicReturn,
+ bool IsLds) {
+ bool IsLdsOpcode = IsLds;
bool HasLdsModifier = false;
OptionalImmIndexMap OptionalIdx;
assert(IsAtomicReturn ? IsAtomic : true);
@@ -4146,10 +4150,11 @@ void AMDGPUAsmParser::cvtMubufImpl(MCIns
// optional modifiers and llvm asm matcher regards this 'lds'
// modifier as an optional one. As a result, an lds version
// of opcode may be selected even if it has no 'lds' modifier.
- if (!HasLdsModifier) {
+ if (IsLdsOpcode && !HasLdsModifier) {
int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode());
if (NoLdsOpcode != -1) { // Got lds version - correct it.
Inst.setOpcode(NoLdsOpcode);
+ IsLdsOpcode = false;
}
}
@@ -4165,7 +4170,7 @@ void AMDGPUAsmParser::cvtMubufImpl(MCIns
}
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
- if (!HasLdsModifier) { // tfe is not legal with lds opcodes
+ if (!IsLdsOpcode) { // tfe is not legal with lds opcodes
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td?rev=327299&r1=327298&r2=327299&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/BUFInstructions.td Mon Mar 12 10:29:24 2018
@@ -449,6 +449,7 @@ class MUBUF_Load_Pseudo <string opName,
MUBUF_SetupAddr<addrKindCopy> {
let PseudoInstr = opName # !if(isLds, "_lds", "") #
"_" # getAddrName<addrKindCopy>.ret;
+ let AsmMatchConverter = !if(isLds, "cvtMubufLds", "cvtMubuf");
let Constraints = !if(HasTiedDest, "$vdata = $vdata_in", "");
let mayLoad = 1;
@@ -548,6 +549,23 @@ multiclass MUBUF_Pseudo_Stores<string op
}
}
+class MUBUF_Pseudo_Store_Lds<string opName>
+ : MUBUF_Pseudo<opName,
+ (outs),
+ (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, GLC:$glc, slc:$slc),
+ " $srsrc, $soffset$offset lds$glc$slc"> {
+ let mayLoad = 0;
+ let mayStore = 1;
+ let maybeAtomic = 1;
+
+ let has_vdata = 0;
+ let has_vaddr = 0;
+ let has_tfe = 0;
+ let lds = 1;
+
+ let Uses = [EXEC, M0];
+ let AsmMatchConverter = "cvtMubufLds";
+}
class getMUBUFAtomicInsDA<RegisterClass vdataClass, bit vdata_in,
list<RegisterClass> vaddrList=[]> {
@@ -877,6 +895,10 @@ defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Pseudo
"buffer_atomic_dec_x2", VReg_64, i64, atomic_dec_global
>;
+let SubtargetPredicate = isVI in {
+def BUFFER_STORE_LDS_DWORD : MUBUF_Pseudo_Store_Lds <"buffer_store_lds_dword">;
+}
+
let SubtargetPredicate = isSI in { // isn't on CI & VI
/*
defm BUFFER_ATOMIC_RSUB : MUBUF_Pseudo_Atomics <"buffer_atomic_rsub">;
@@ -1952,6 +1974,8 @@ defm BUFFER_ATOMIC_XOR_X2 : MUBUF_
defm BUFFER_ATOMIC_INC_X2 : MUBUF_Real_Atomic_vi <0x6b>;
defm BUFFER_ATOMIC_DEC_X2 : MUBUF_Real_Atomic_vi <0x6c>;
+def BUFFER_STORE_LDS_DWORD_vi : MUBUF_Real_vi <0x3d, BUFFER_STORE_LDS_DWORD>;
+
def BUFFER_WBINVL1_vi : MUBUF_Real_vi <0x3e, BUFFER_WBINVL1>;
def BUFFER_WBINVL1_VOL_vi : MUBUF_Real_vi <0x3f, BUFFER_WBINVL1_VOL>;
Modified: llvm/trunk/test/MC/AMDGPU/mubuf.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/mubuf.s?rev=327299&r1=327298&r2=327299&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/mubuf.s (original)
+++ llvm/trunk/test/MC/AMDGPU/mubuf.s Mon Mar 12 10:29:24 2018
@@ -2,8 +2,8 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=SICI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI -check-prefix=NOSICIVI %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOCI -check-prefix=NOSICIVI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=NOSI -check-prefix=NOSICIVI -check-prefix=NOSICI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefix=NOCI -check-prefix=NOSICIVI -check-prefix=NOSICI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=NOVI -check-prefix=NOSICIVI %s
//===----------------------------------------------------------------------===//
@@ -767,6 +767,18 @@ buffer_load_format_x v5, v[0:1], s[8:11]
// SICI: buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x01,0xe0,0x00,0x05,0x42,0x03]
// VI: buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03]
+buffer_store_lds_dword s[4:7], s0 lds
+// NOSICI: error: instruction not supported on this GPU
+// VI: buffer_store_lds_dword s[4:7], s0 lds ; encoding: [0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s0 offset:4095 lds
+// NOSICI: error: not a valid operand.
+// VI: buffer_store_lds_dword s[4:7], s0 offset:4095 lds ; encoding: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc
+// NOSICI: error: not a valid operand.
+// VI: buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc ; encoding: [0x04,0x40,0xf7,0xe0,0x00,0x00,0x01,0x08]
+
//===----------------------------------------------------------------------===//
// Errors handling
//===----------------------------------------------------------------------===//
@@ -776,3 +788,11 @@ buffer_load_sbyte v5, off, s[8:11], s3 l
buffer_load_dword v5, off, s[8:11], s3 tfe lds
// NOSICIVI: error: invalid operand for instruction
+
+buffer_store_lds_dword s[4:7], s8 offset:4 lds tfe
+// NOSICI: error: not a valid operand.
+// NOVI: error: invalid operand for instruction
+
+buffer_store_lds_dword s[4:7], s8 offset:4 tfe lds
+// NOSICI: error: not a valid operand.
+// NOVI: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/mubuf_vi.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/mubuf_vi.txt?rev=327299&r1=327298&r2=327299&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/mubuf_vi.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/mubuf_vi.txt Mon Mar 12 10:29:24 2018
@@ -402,3 +402,12 @@
# VI: buffer_load_format_x v5, v[0:1], s[8:11], s3 idxen offen offset:4095 glc slc lds ; encoding: [0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03]
0xff,0x7f,0x03,0xe0,0x00,0x05,0x02,0x03
+
+# VI: buffer_store_lds_dword s[4:7], s0 lds ; encoding: [0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00
+
+# VI: buffer_store_lds_dword s[4:7], s0 offset:4095 lds ; encoding: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x00]
+0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x00
+
+# VI: buffer_store_lds_dword s[4:7], s8 offset:4 lds glc slc ; encoding: [0x04,0x40,0xf7,0xe0,0x00,0x00,0x01,0x08]
+0x04,0x40,0xf7,0xe0,0x00,0x00,0x01,0x08
More information about the llvm-commits
mailing list