[llvm] r327211 - [AMDGPU] fix tests to be independent of FP undef
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 10 08:39:59 PST 2018
Author: spatel
Date: Sat Mar 10 08:39:59 2018
New Revision: 327211
URL: http://llvm.org/viewvc/llvm-project?rev=327211&view=rev
Log:
[AMDGPU] fix tests to be independent of FP undef
Modified:
llvm/trunk/test/CodeGen/AMDGPU/madmk.ll
llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll
llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
Modified: llvm/trunk/test/CodeGen/AMDGPU/madmk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/madmk.ll?rev=327211&r1=327210&r2=327211&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/madmk.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/madmk.ll Sat Mar 10 08:39:59 2018
@@ -205,9 +205,8 @@ bb2:
br i1 %tmp5, label %bb1, label %bb6
bb6: ; preds = %bb2
- %tmp4 = fmul float %tmp, undef
- %tmp7 = fmul float %tmp4, 0x40E55DD180000000
- %tmp8 = fadd float %tmp7, undef
+ %tmp7 = fmul float %tmp, 0x40E55DD180000000
+ %tmp8 = fadd float %tmp7, %tmp
br label %bb2
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll?rev=327211&r1=327210&r2=327211&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll Sat Mar 10 08:39:59 2018
@@ -29,21 +29,21 @@ entry:
%i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #2
- %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
- %p87 = fmul float undef, %p2.i
- %p88 = fadd float %p87, undef
- %p93 = fadd float %p88, undef
- %p97 = fmul float %p93, undef
- %p102 = fsub float %p97, undef
- %p104 = fmul float %p102, undef
+ %p2 = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
+ %p87 = fmul float %p2, %p2
+ %p88 = fadd float %p87, %p87
+ %p93 = fadd float %p88, %p88
+ %p97 = fmul float %p93, %p93
+ %p102 = fsub float %p97, %p97
+ %p104 = fmul float %p102, %p102
%p106 = fadd float 0.000000e+00, %p104
- %p108 = fadd float undef, %p106
+ %p108 = fadd float %p106, %p106
%uniform.cond = icmp slt i32 %arg17, 0
br i1 %uniform.cond, label %ret.bb, label %else
else: ; preds = %main_body
%p124 = fmul float %p108, %p108
- %p125 = fsub float %p124, undef
+ %p125 = fsub float %p124, %p124
%divergent.cond = fcmp olt float %p125, 0.000000e+00
br i1 %divergent.cond, label %ret.bb, label %unreachable.bb
@@ -80,21 +80,21 @@ main_body:
%i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #2
- %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
- %p87 = fmul float undef, %p2.i
- %p88 = fadd float %p87, undef
- %p93 = fadd float %p88, undef
- %p97 = fmul float %p93, undef
- %p102 = fsub float %p97, undef
- %p104 = fmul float %p102, undef
+ %p2 = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
+ %p87 = fmul float %p2, %p2
+ %p88 = fadd float %p87, %p87
+ %p93 = fadd float %p88, %p88
+ %p97 = fmul float %p93, %p93
+ %p102 = fsub float %p97, %p97
+ %p104 = fmul float %p102, %p102
%p106 = fadd float 0.000000e+00, %p104
- %p108 = fadd float undef, %p106
+ %p108 = fadd float %p106, %p106
%uniform.cond = icmp slt i32 %arg18, 0
br i1 %uniform.cond, label %ret.bb, label %else
else: ; preds = %main_body
%p124 = fmul float %p108, %p108
- %p125 = fsub float %p124, undef
+ %p125 = fsub float %p124, %p124
%divergent.cond = fcmp olt float %p125, 0.000000e+00
br i1 %divergent.cond, label %ret.bb, label %unreachable.bb
Modified: llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll?rev=327211&r1=327210&r2=327211&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/unigine-liveness-crash.ll Sat Mar 10 08:39:59 2018
@@ -20,9 +20,9 @@ main_body:
%tmp23 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp24 = extractelement <4 x float> %tmp23, i32 3
- %tmp25 = fmul float %tmp24, undef
- %tmp26 = fmul float undef, %p2.i
- %tmp27 = fadd float %tmp26, undef
+ %tmp25 = fmul float %tmp24, %tmp24
+ %tmp26 = fmul float %p2.i, %p2.i
+ %tmp27 = fadd float %tmp26, %tmp26
%tmp28 = bitcast float %tmp27 to i32
%tmp29 = insertelement <4 x i32> undef, i32 %tmp28, i32 0
%tmp30 = insertelement <4 x i32> %tmp29, i32 0, i32 1
@@ -30,22 +30,22 @@ main_body:
%tmp31.cast = bitcast <4 x i32> %tmp31 to <4 x float>
%tmp32 = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v8i32(<4 x float> %tmp31.cast, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp33 = extractelement <4 x float> %tmp32, i32 0
- %tmp34 = fadd float undef, %tmp33
- %tmp35 = fadd float %tmp34, undef
- %tmp36 = fadd float %tmp35, undef
- %tmp37 = fadd float %tmp36, undef
- %tmp38 = fadd float %tmp37, undef
+ %tmp34 = fadd float %tmp33, %tmp33
+ %tmp35 = fadd float %tmp34, %tmp34
+ %tmp36 = fadd float %tmp35, %tmp35
+ %tmp37 = fadd float %tmp36, %tmp36
+ %tmp38 = fadd float %tmp37, %tmp37
%tmp39 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp40 = extractelement <4 x float> %tmp39, i32 0
%tmp41 = extractelement <4 x float> %tmp39, i32 1
%tmp42 = extractelement <4 x float> %tmp39, i32 2
%tmp43 = extractelement <4 x float> %tmp39, i32 3
- %tmp44 = fmul float %tmp40, undef
- %tmp45 = fmul float %tmp41, undef
- %tmp46 = fmul float %tmp42, undef
- %tmp47 = fmul float %tmp43, undef
- %tmp48 = fadd float undef, %tmp44
- %tmp49 = fadd float undef, %tmp45
+ %tmp44 = fmul float %tmp40, %tmp40
+ %tmp45 = fmul float %tmp41, %tmp41
+ %tmp46 = fmul float %tmp42, %tmp41
+ %tmp47 = fmul float %tmp43, %tmp43
+ %tmp48 = fadd float %tmp44, %tmp44
+ %tmp49 = fadd float %tmp45, %tmp45
%tmp50 = bitcast float %tmp27 to i32
%tmp51 = bitcast float %tmp48 to i32
%tmp52 = bitcast float %tmp49 to i32
@@ -56,8 +56,8 @@ main_body:
%tmp56 = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v8i32(<4 x float> %tmp55.cast, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp57 = extractelement <4 x float> %tmp56, i32 0
%tmp58 = fadd float %tmp38, %tmp57
- %tmp59 = fadd float undef, %tmp46
- %tmp60 = fadd float undef, %tmp47
+ %tmp59 = fadd float %tmp46, %tmp46
+ %tmp60 = fadd float %tmp47, %tmp47
%tmp61 = bitcast float %tmp59 to i32
%tmp62 = bitcast float %tmp60 to i32
%tmp63 = insertelement <4 x i32> undef, i32 %tmp61, i32 1
@@ -67,7 +67,7 @@ main_body:
%tmp66 = extractelement <4 x float> %tmp65, i32 0
%tmp67 = fadd float %tmp58, %tmp66
%tmp68 = fmul float %tmp67, 1.250000e-01
- %tmp69 = fmul float %tmp68, undef
+ %tmp69 = fmul float %tmp68, %tmp68
%tmp70 = fcmp une float %tmp69, 0.000000e+00
br i1 %tmp70, label %IF26, label %ENDIF25
@@ -78,12 +78,12 @@ IF26:
ENDIF25: ; preds = %IF29, %main_body
%.4 = phi float [ %tmp84, %IF29 ], [ %tmp68, %main_body ]
- %tmp73 = fadd float %.4, undef
+ %tmp73 = fadd float %.4, %.4
%max.0.i = call float @llvm.maxnum.f32(float %tmp73, float 0.000000e+00)
%clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
- %tmp75 = fmul float undef, %clamp.i
- %tmp76 = fmul float %tmp75, undef
- %tmp77 = fadd float %tmp76, undef
+ %tmp75 = fmul float %clamp.i, %clamp.i
+ %tmp76 = fmul float %tmp75, %tmp75
+ %tmp77 = fadd float %tmp76, %tmp76
%tmp78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, float %tmp77, 11
%tmp79 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp78, float undef, 12
%tmp80 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp79, float undef, 13
@@ -106,7 +106,7 @@ ENDIF28:
%tmp86.cast = bitcast <4 x i32> %tmp86 to <4 x float>
%tmp87 = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32.v4f32.v8i32(<4 x float> %tmp86.cast, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp88 = extractelement <4 x float> %tmp87, i32 0
- %tmp89 = fadd float undef, %tmp88
+ %tmp89 = fadd float %tmp88, %tmp88
br label %LOOP
}
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