[www-releases] r326992 - 6.0.0 files

Hans Wennborg via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 8 02:24:48 PST 2018


Author: hans
Date: Thu Mar  8 02:24:44 2018
New Revision: 326992

URL: http://llvm.org/viewvc/llvm-project?rev=326992&view=rev
Log:
6.0.0 files

Added:
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--- www-releases/trunk/6.0.0/LICENSE.TXT (added)
+++ www-releases/trunk/6.0.0/LICENSE.TXT Thu Mar  8 02:24:44 2018
@@ -0,0 +1,68 @@
+==============================================================================
+LLVM Release License
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2017 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+==============================================================================
+Copyrights and Licenses for Third Party Software Distributed with LLVM:
+==============================================================================
+The LLVM software contains code written by third parties.  Such software will
+have its own individual LICENSE.TXT file in the directory in which it appears.
+This file will describe the copyrights, license, and restrictions which apply
+to that code.
+
+The disclaimer of warranty in the University of Illinois Open Source License
+applies to all code in the LLVM Distribution, and nothing in any of the
+other licenses gives permission to use the names of the LLVM Team or the
+University of Illinois to endorse or promote products derived from this
+Software.
+
+The following pieces of software have additional or alternate copyrights,
+licenses, and/or restrictions:
+
+Program             Directory
+-------             ---------
+Google Test         llvm/utils/unittest/googletest
+OpenBSD regex       llvm/lib/Support/{reg*, COPYRIGHT.regex}
+pyyaml tests        llvm/test/YAMLParser/{*.data, LICENSE.TXT}
+ARM contributions   llvm/lib/Target/ARM/LICENSE.TXT
+md5 contributions   llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h

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+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+  "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+  <head>
+    <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+    
+    <title>User Guide for AMDGPU Backend — LLVM 6 documentation</title>
+    
+    <link rel="stylesheet" href="_static/llvm-theme.css" type="text/css" />
+    <link rel="stylesheet" href="_static/pygments.css" type="text/css" />
+    
+    <script type="text/javascript">
+      var DOCUMENTATION_OPTIONS = {
+        URL_ROOT:    './',
+        VERSION:     '6',
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+        FILE_SUFFIX: '.html',
+        HAS_SOURCE:  true,
+        SOURCELINK_SUFFIX: '.txt'
+      };
+    </script>
+    <script type="text/javascript" src="_static/jquery.js"></script>
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+    <script type="text/javascript" src="_static/doctools.js"></script>
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+    <div class="document">
+      <div class="documentwrapper">
+          <div class="body" role="main">
+            
+  <div class="section" id="user-guide-for-amdgpu-backend">
+<h1>User Guide for AMDGPU Backend<a class="headerlink" href="#user-guide-for-amdgpu-backend" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id38">Introduction</a></li>
+<li><a class="reference internal" href="#llvm" id="id39">LLVM</a><ul>
+<li><a class="reference internal" href="#target-triples" id="id40">Target Triples</a></li>
+<li><a class="reference internal" href="#processors" id="id41">Processors</a></li>
+<li><a class="reference internal" href="#target-features" id="id42">Target Features</a></li>
+<li><a class="reference internal" href="#address-spaces" id="id43">Address Spaces</a></li>
+<li><a class="reference internal" href="#memory-scopes" id="id44">Memory Scopes</a></li>
+<li><a class="reference internal" href="#amdgpu-intrinsics" id="id45">AMDGPU Intrinsics</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object" id="id46">Code Object</a><ul>
+<li><a class="reference internal" href="#header" id="id47">Header</a></li>
+<li><a class="reference internal" href="#sections" id="id48">Sections</a></li>
+<li><a class="reference internal" href="#note-records" id="id49">Note Records</a></li>
+<li><a class="reference internal" href="#symbols" id="id50">Symbols</a></li>
+<li><a class="reference internal" href="#relocation-records" id="id51">Relocation Records</a></li>
+<li><a class="reference internal" href="#dwarf" id="id52">DWARF</a><ul>
+<li><a class="reference internal" href="#address-space-mapping" id="id53">Address Space Mapping</a></li>
+<li><a class="reference internal" href="#register-mapping" id="id54">Register Mapping</a></li>
+<li><a class="reference internal" href="#source-text" id="id55">Source Text</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-conventions" id="id56">Code Conventions</a><ul>
+<li><a class="reference internal" href="#amdhsa" id="id57">AMDHSA</a><ul>
+<li><a class="reference internal" href="#code-object-metadata" id="id58">Code Object Metadata</a></li>
+<li><a class="reference internal" href="#kernel-dispatch" id="id59">Kernel Dispatch</a></li>
+<li><a class="reference internal" href="#memory-spaces" id="id60">Memory Spaces</a></li>
+<li><a class="reference internal" href="#image-and-samplers" id="id61">Image and Samplers</a></li>
+<li><a class="reference internal" href="#hsa-signals" id="id62">HSA Signals</a></li>
+<li><a class="reference internal" href="#hsa-aql-queue" id="id63">HSA AQL Queue</a></li>
+<li><a class="reference internal" href="#kernel-descriptor" id="id64">Kernel Descriptor</a><ul>
+<li><a class="reference internal" href="#kernel-descriptor-for-gfx6-gfx9" id="id65">Kernel Descriptor for GFX6-GFX9</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#initial-kernel-execution-state" id="id66">Initial Kernel Execution State</a></li>
+<li><a class="reference internal" href="#kernel-prolog" id="id67">Kernel Prolog</a><ul>
+<li><a class="reference internal" href="#m0" id="id68">M0</a></li>
+<li><a class="reference internal" href="#flat-scratch" id="id69">Flat Scratch</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#memory-model" id="id70">Memory Model</a></li>
+<li><a class="reference internal" href="#trap-handler-abi" id="id71">Trap Handler ABI</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#unspecified-os" id="id72">Unspecified OS</a><ul>
+<li><a class="reference internal" href="#id31" id="id73">Trap Handler ABI</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#source-languages" id="id74">Source Languages</a><ul>
+<li><a class="reference internal" href="#opencl" id="id75">OpenCL</a></li>
+<li><a class="reference internal" href="#hcc" id="id76">HCC</a></li>
+<li><a class="reference internal" href="#assembler" id="id77">Assembler</a><ul>
+<li><a class="reference internal" href="#operands" id="id78">Operands</a></li>
+<li><a class="reference internal" href="#instruction-examples" id="id79">Instruction Examples</a></li>
+<li><a class="reference internal" href="#ds" id="id80">DS</a><ul>
+<li><a class="reference internal" href="#flat" id="id81">FLAT</a></li>
+<li><a class="reference internal" href="#mubuf" id="id82">MUBUF</a></li>
+<li><a class="reference internal" href="#smrd-smem" id="id83">SMRD/SMEM</a></li>
+<li><a class="reference internal" href="#sop1" id="id84">SOP1</a></li>
+<li><a class="reference internal" href="#sop2" id="id85">SOP2</a></li>
+<li><a class="reference internal" href="#sopc" id="id86">SOPC</a></li>
+<li><a class="reference internal" href="#sopp" id="id87">SOPP</a></li>
+<li><a class="reference internal" href="#valu" id="id88">VALU</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#hsa-code-object-directives" id="id89">HSA Code Object Directives</a><ul>
+<li><a class="reference internal" href="#hsa-code-object-version-major-minor" id="id90">.hsa_code_object_version major, minor</a></li>
+<li><a class="reference internal" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" id="id91">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a></li>
+<li><a class="reference internal" href="#amdgpu-hsa-kernel-name" id="id92">.amdgpu_hsa_kernel (name)</a></li>
+<li><a class="reference internal" href="#amd-kernel-code-t" id="id93">.amd_kernel_code_t</a></li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#additional-documentation" id="id94">Additional Documentation</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id38">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the
+R600 family up until the current GCN families. It lives in the
+<code class="docutils literal"><span class="pre">lib/Target/AMDGPU</span></code> directory.</p>
+</div>
+<div class="section" id="llvm">
+<h2><a class="toc-backref" href="#id39">LLVM</a><a class="headerlink" href="#llvm" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="target-triples">
+<span id="amdgpu-target-triples"></span><h3><a class="toc-backref" href="#id40">Target Triples</a><a class="headerlink" href="#target-triples" title="Permalink to this headline">¶</a></h3>
+<p>Use the <code class="docutils literal"><span class="pre">clang</span> <span class="pre">-target</span> <span class="pre"><Architecture>-<Vendor>-<OS>-<Environment></span></code> option to
+specify the target triple:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-architecture-table">
+<caption><span class="caption-text">AMDGPU Architectures</span><a class="headerlink" href="#amdgpu-architecture-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Architecture</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>AMD GPUs GCN GFX6 onwards for graphics and compute shaders.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-vendor-table">
+<caption><span class="caption-text">AMDGPU Vendors</span><a class="headerlink" href="#amdgpu-vendor-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Vendor</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">amd</span></code></td>
+<td>Can be used for all AMD GPU usage.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">mesa3d</span></code></td>
+<td>Can be used if the OS is <code class="docutils literal"><span class="pre">mesa3d</span></code>.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-os-table">
+<caption><span class="caption-text">AMDGPU Operating Systems</span><a class="headerlink" href="#amdgpu-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="19%" />
+<col width="81%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">OS</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em><empty></em></td>
+<td>Defaults to the <em>unknown</em> OS.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">amdhsa</span></code></td>
+<td>Compute kernels executed on HSA <a class="reference internal" href="#hsa" id="id1">[HSA]</a> compatible runtimes
+such as AMD’s ROCm <a class="reference internal" href="#amd-rocm" id="id2">[AMD-ROCm]</a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">amdpal</span></code></td>
+<td>Graphic shaders and compute kernels executed on AMD PAL
+runtime.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">mesa3d</span></code></td>
+<td>Graphic shaders and compute kernels executed on Mesa 3D
+runtime.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-environment-table">
+<caption><span class="caption-text">AMDGPU Environments</span><a class="headerlink" href="#amdgpu-environment-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Environment</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em><empty></em></td>
+<td>Defaults to <code class="docutils literal"><span class="pre">opencl</span></code>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">opencl</span></code></td>
+<td>OpenCL compute kernel (see <a class="reference internal" href="#amdgpu-opencl"><span class="std std-ref">OpenCL</span></a>).</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">amdgizcl</span></code></td>
+<td>Same as <code class="docutils literal"><span class="pre">opencl</span></code> except a different address space mapping is
+used (see <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a>).</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">amdgiz</span></code></td>
+<td>Same as <code class="docutils literal"><span class="pre">opencl</span></code> except a different address space mapping is
+used (see <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a>).</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">hcc</span></code></td>
+<td>AMD HC language compute kernel (see <a class="reference internal" href="#amdgpu-hcc"><span class="std std-ref">HCC</span></a>).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="processors">
+<span id="amdgpu-processors"></span><h3><a class="toc-backref" href="#id41">Processors</a><a class="headerlink" href="#processors" title="Permalink to this headline">¶</a></h3>
+<p>Use the <code class="docutils literal"><span class="pre">clang</span> <span class="pre">-mcpu</span> <span class="pre"><Processor></span></code> option to specify the AMD GPU processor. The
+names from both the <em>Processor</em> and <em>Alternative Processor</em> can be used.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-processor-table">
+<caption><span class="caption-text">AMDGPU Processors</span><a class="headerlink" href="#amdgpu-processor-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="14%" />
+<col width="19%" />
+<col width="15%" />
+<col width="6%" />
+<col width="11%" />
+<col width="9%" />
+<col width="27%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Processor</th>
+<th class="head">Alternative
+Processor</th>
+<th class="head">Target
+Triple
+Architecture</th>
+<th class="head">dGPU/
+APU</th>
+<th class="head">Target
+Features
+Supported
+[Default]</th>
+<th class="head">ROCm
+Support</th>
+<th class="head">Example
+Products</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="7"><strong>Radeon HD 2000/3000 Series (R600)</strong> <a class="reference internal" href="#amd-radeon-hd-2000-3000" id="id3">[AMD-RADEON-HD-2000-3000]</a></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">r630</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">rs880</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">rv670</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 4000 Series (R700)</strong> <a class="reference internal" href="#amd-radeon-hd-4000" id="id4">[AMD-RADEON-HD-4000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">rv710</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">rv730</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">rv770</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 5000 Series (Evergreen)</strong> <a class="reference internal" href="#amd-radeon-hd-5000" id="id5">[AMD-RADEON-HD-5000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">cedar</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">redwood</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">sumo</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">juniper</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">cypress</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 6000 Series (Northern Islands)</strong> <a class="reference internal" href="#amd-radeon-hd-6000" id="id6">[AMD-RADEON-HD-6000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">barts</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">turks</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">caicos</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">cayman</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td colspan="7"><strong>GCN GFX6 (Southern Islands (SI))</strong> <a class="reference internal" href="#amd-gcn-gfx6" id="id7">[AMD-GCN-GFX6]</a></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">gfx600</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">tahiti</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx601</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">pitcairn</span></code></li>
+<li><code class="docutils literal"><span class="pre">verde</span></code></li>
+<li><code class="docutils literal"><span class="pre">oland</span></code></li>
+<li><code class="docutils literal"><span class="pre">hainan</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX7 (Sea Islands (CI))</strong> <a class="reference internal" href="#amd-gcn-gfx7" id="id8">[AMD-GCN-GFX7]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx700</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">kaveri</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A6-7000</li>
+<li>A6 Pro-7050B</li>
+<li>A8-7100</li>
+<li>A8 Pro-7150B</li>
+<li>A10-7300</li>
+<li>A10 Pro-7350B</li>
+<li>FX-7500</li>
+<li>A8-7200P</li>
+<li>A10-7400P</li>
+<li>FX-7600P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">gfx701</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">hawaii</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>FirePro W8100</li>
+<li>FirePro W9100</li>
+<li>FirePro S9150</li>
+<li>FirePro S9170</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx702</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon R9 290</li>
+<li>Radeon R9 290x</li>
+<li>Radeon R390</li>
+<li>Radeon R390x</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">gfx703</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">kabini</span></code></li>
+<li><code class="docutils literal"><span class="pre">mullins</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>E1-2100</li>
+<li>E1-2200</li>
+<li>E1-2500</li>
+<li>E2-3000</li>
+<li>E2-3800</li>
+<li>A4-5000</li>
+<li>A4-5100</li>
+<li>A6-5200</li>
+<li>A4 Pro-3340B</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx704</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">bonaire</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>Radeon HD 7790</li>
+<li>Radeon HD 8770</li>
+<li>R7 260</li>
+<li>R7 260X</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX8 (Volcanic Islands (VI))</strong> <a class="reference internal" href="#amd-gcn-gfx8" id="id9">[AMD-GCN-GFX8]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx801</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">carrizo</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A6-8500P</li>
+<li>Pro A6-8500B</li>
+<li>A8-8600P</li>
+<li>Pro A8-8600B</li>
+<li>FX-8800P</li>
+<li>Pro A12-8800B</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>A10-8700P</li>
+<li>Pro A10-8700B</li>
+<li>A10-8780P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A10-9600P</li>
+<li>A10-9630P</li>
+<li>A12-9700P</li>
+<li>A12-9730P</li>
+<li>FX-9800P</li>
+<li>FX-9830P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>E2-9010</li>
+<li>A6-9210</li>
+<li>A9-9410</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx802</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">tonga</span></code></li>
+<li><code class="docutils literal"><span class="pre">iceland</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>FirePro S7150</li>
+<li>FirePro S7100</li>
+<li>FirePro W7100</li>
+<li>Radeon R285</li>
+<li>Radeon R9 380</li>
+<li>Radeon R9 385</li>
+<li>Mobile FirePro
+M7170</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">gfx803</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">fiji</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon R9 Nano</li>
+<li>Radeon R9 Fury</li>
+<li>Radeon R9 FuryX</li>
+<li>Radeon Pro Duo</li>
+<li>FirePro S9300x2</li>
+<li>Radeon Instinct MI8</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">polaris10</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon RX 470</li>
+<li>Radeon RX 480</li>
+<li>Radeon Instinct MI6</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">polaris11</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon RX 460</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx810</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">stoney</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX9</strong> <a class="reference internal" href="#amd-gcn-gfx9" id="id10">[AMD-GCN-GFX9]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">gfx900</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon Vega
+Frontier Edition</li>
+<li>Radeon RX Vega 56</li>
+<li>Radeon RX Vega 64</li>
+<li>Radeon RX Vega 64
+Liquid</li>
+<li>Radeon Instinct MI25</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">gfx902</span></code></td>
+<td> </td>
+<td><code class="docutils literal"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="target-features">
+<span id="amdgpu-target-features"></span><h3><a class="toc-backref" href="#id42">Target Features</a><a class="headerlink" href="#target-features" title="Permalink to this headline">¶</a></h3>
+<p>Target features control how code is generated to support certain
+processor specific features. Not all target features are supported by
+all processors. The runtime must ensure that the features supported by
+the device used to execute the code match the features enabled when
+generating the code. A mismatch of features may result in incorrect
+execution, or a reduction in performance.</p>
+<p>The target features supported by each processor, and the default value
+used if not specified explicitly, is listed in
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</p>
+<p>Use the <code class="docutils literal"><span class="pre">clang</span> <span class="pre">-m[no-]<TargetFeature></span></code> option to specify the AMD GPU
+target features.</p>
+<p>For example:</p>
+<dl class="docutils">
+<dt><code class="docutils literal"><span class="pre">-mxnack</span></code></dt>
+<dd>Enable the <code class="docutils literal"><span class="pre">xnack</span></code> feature.</dd>
+<dt><code class="docutils literal"><span class="pre">-mno-xnack</span></code></dt>
+<dd><p class="first">Disable the <code class="docutils literal"><span class="pre">xnack</span></code> feature.</p>
+<table border="1" class="last docutils" id="amdgpu-target-feature-table">
+<caption><span class="caption-text">AMDGPU Target Features</span><a class="headerlink" href="#amdgpu-target-feature-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="22%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Target Feature</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>-m[no-]xnack</td>
+<td><p class="first">Enable/disable generating code that has
+memory clauses that are compatible with
+having XNACK replay enabled.</p>
+<p class="last">This is used for demand paging and page
+migration. If XNACK replay is enabled in
+the device, then if a page fault occurs
+the code may execute incorrectly if the
+<code class="docutils literal"><span class="pre">xnack</span></code> feature is not enabled. Executing
+code that has the feature enabled on a
+device that does not have XNACK replay
+enabled will execute correctly, but may
+be less performant than code with the
+feature disabled.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+</div>
+<div class="section" id="address-spaces">
+<span id="amdgpu-address-spaces"></span><h3><a class="toc-backref" href="#id43">Address Spaces</a><a class="headerlink" href="#address-spaces" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend uses the following address space mappings.</p>
+<p>The memory space names used in the table, aside from the region memory space, is
+from the OpenCL standard.</p>
+<p>LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-address-space-mapping-table">
+<caption><span class="caption-text">Address Space Mapping</span><a class="headerlink" href="#amdgpu-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="21%" />
+<col width="20%" />
+<col width="20%" />
+<col width="20%" />
+<col width="20%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Address Space</th>
+<th class="head" colspan="4">Memory Space</th>
+</tr>
+<tr class="row-even"><th class="head"></th>
+<th class="head">Current Default</th>
+<th class="head">amdgiz/amdgizcl</th>
+<th class="head">hcc</th>
+<th class="head">Future Default</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-odd"><td>0</td>
+<td>Private (Scratch)</td>
+<td>Generic (Flat)</td>
+<td>Generic (Flat)</td>
+<td>Generic (Flat)</td>
+</tr>
+<tr class="row-even"><td>1</td>
+<td>Global</td>
+<td>Global</td>
+<td>Global</td>
+<td>Global</td>
+</tr>
+<tr class="row-odd"><td>2</td>
+<td>Constant</td>
+<td>Constant</td>
+<td>Constant</td>
+<td>Region (GDS)</td>
+</tr>
+<tr class="row-even"><td>3</td>
+<td>Local (group/LDS)</td>
+<td>Local (group/LDS)</td>
+<td>Local (group/LDS)</td>
+<td>Local (group/LDS)</td>
+</tr>
+<tr class="row-odd"><td>4</td>
+<td>Generic (Flat)</td>
+<td>Region (GDS)</td>
+<td>Region (GDS)</td>
+<td>Constant</td>
+</tr>
+<tr class="row-even"><td>5</td>
+<td>Region (GDS)</td>
+<td>Private (Scratch)</td>
+<td>Private (Scratch)</td>
+<td>Private (Scratch)</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt>Current Default</dt>
+<dd>This is the current default address space mapping used for all languages
+except hcc. This will shortly be deprecated.</dd>
+<dt>amdgiz/amdgizcl</dt>
+<dd>This is the current address space mapping used when <code class="docutils literal"><span class="pre">amdgiz</span></code> or <code class="docutils literal"><span class="pre">amdgizcl</span></code>
+is specified as the target triple environment value.</dd>
+<dt>hcc</dt>
+<dd>This is the current address space mapping used when <code class="docutils literal"><span class="pre">hcc</span></code> is specified as
+the target triple environment value.This will shortly be deprecated.</dd>
+<dt>Future Default</dt>
+<dd>This will shortly be the only address space mapping for all languages using
+AMDGPU backend.</dd>
+</dl>
+</div>
+<div class="section" id="memory-scopes">
+<span id="amdgpu-memory-scopes"></span><h3><a class="toc-backref" href="#id44">Memory Scopes</a><a class="headerlink" href="#memory-scopes" title="Permalink to this headline">¶</a></h3>
+<p>This section provides LLVM memory synchronization scopes supported by the AMDGPU
+backend memory model when the target triple OS is <code class="docutils literal"><span class="pre">amdhsa</span></code> (see
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a> and <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<p>The memory model supported is based on the HSA memory model <a class="reference internal" href="#hsa" id="id11">[HSA]</a> which is
+based in turn on HRF-indirect with scope inclusion <a class="reference internal" href="#hrf" id="id12">[HRF]</a>. The happens-before
+relation is transitive over the synchonizes-with relation independent of scope,
+and synchonizes-with allows the memory scope instances to be inclusive (see
+table <a class="reference internal" href="#amdgpu-amdhsa-llvm-sync-scopes-table"><span class="std std-ref">AMDHSA LLVM Sync Scopes</span></a>).</p>
+<p>This is different to the OpenCL <a class="reference internal" href="#id37" id="id13">[OpenCL]</a> memory model which does not have scope
+inclusion and requires the memory scopes to exactly match. However, this
+is conservatively correct for OpenCL.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-llvm-sync-scopes-table">
+<caption><span class="caption-text">AMDHSA LLVM Sync Scopes</span><a class="headerlink" href="#amdgpu-amdhsa-llvm-sync-scopes-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="22%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Sync Scope</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>none</em></td>
+<td><p class="first">The default: <code class="docutils literal"><span class="pre">system</span></code>.</p>
+<p>Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operation’s sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal"><span class="pre">system</span></code>.</li>
+<li><code class="docutils literal"><span class="pre">agent</span></code> and executed by a thread on the same agent.</li>
+<li><code class="docutils literal"><span class="pre">workgroup</span></code> and executed by a thread in the same
+workgroup.</li>
+<li><code class="docutils literal"><span class="pre">wavefront</span></code> and executed by a thread in the same
+wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">agent</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operation’s sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal"><span class="pre">system</span></code> or <code class="docutils literal"><span class="pre">agent</span></code> and executed by a thread on the
+same agent.</li>
+<li><code class="docutils literal"><span class="pre">workgroup</span></code> and executed by a thread in the same
+workgroup.</li>
+<li><code class="docutils literal"><span class="pre">wavefront</span></code> and executed by a thread in the same
+wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">workgroup</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operation’s sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal"><span class="pre">system</span></code>, <code class="docutils literal"><span class="pre">agent</span></code> or <code class="docutils literal"><span class="pre">workgroup</span></code> and executed by a
+thread in the same workgroup.</li>
+<li><code class="docutils literal"><span class="pre">wavefront</span></code> and executed by a thread in the same
+wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">wavefront</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification and
+seq_cst total orderings with, other operations (except
+image operations) for all address spaces (except private,
+or generic that accesses private) provided the other
+operation’s sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal"><span class="pre">system</span></code>, <code class="docutils literal"><span class="pre">agent</span></code>, <code class="docutils literal"><span class="pre">workgroup</span></code> or <code class="docutils literal"><span class="pre">wavefront</span></code>
+and executed by a thread in the same wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">singlethread</span></code></td>
+<td>Only synchronizes with, and participates in modification
+and seq_cst total orderings with, other operations (except
+image operations) running in the same thread for all
+address spaces (for example, in signal handlers).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-intrinsics">
+<h3><a class="toc-backref" href="#id45">AMDGPU Intrinsics</a><a class="headerlink" href="#amdgpu-intrinsics" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend implements the following intrinsics.</p>
+<p><em>This section is WIP.</em></p>
+</div>
+</div>
+<div class="section" id="code-object">
+<h2><a class="toc-backref" href="#id46">Code Object</a><a class="headerlink" href="#code-object" title="Permalink to this headline">¶</a></h2>
+<p>The AMDGPU backend generates a standard ELF <a class="reference internal" href="#elf" id="id14">[ELF]</a> relocatable code object that
+can be linked by <code class="docutils literal"><span class="pre">lld</span></code> to produce a standard ELF shared code object which can
+be loaded and executed on an AMDGPU target.</p>
+<div class="section" id="header">
+<h3><a class="toc-backref" href="#id47">Header</a><a class="headerlink" href="#header" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend uses the following ELF header:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-header-table">
+<caption><span class="caption-text">AMDGPU ELF Header</span><a class="headerlink" href="#amdgpu-elf-header-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="38%" />
+<col width="62%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Field</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">e_ident[EI_CLASS]</span></code></td>
+<td><code class="docutils literal"><span class="pre">ELFCLASS64</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">e_ident[EI_DATA]</span></code></td>
+<td><code class="docutils literal"><span class="pre">ELFDATA2LSB</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">e_ident[EI_OSABI]</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">ELFOSABI_NONE</span></code></li>
+<li><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></li>
+<li><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></li>
+<li><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">e_ident[EI_ABIVERSION]</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></li>
+<li><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></li>
+<li><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">e_type</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">ET_REL</span></code></li>
+<li><code class="docutils literal"><span class="pre">ET_DYN</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">e_machine</span></code></td>
+<td><code class="docutils literal"><span class="pre">EM_AMDGPU</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">e_entry</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">e_flags</span></code></td>
+<td>See <a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-header-enumeration-values-table">
+<caption><span class="caption-text">AMDGPU ELF Header Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-header-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EM_AMDGPU</span></code></td>
+<td>224</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">ELFOSABI_NONE</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></td>
+<td>64</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></td>
+<td>65</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></td>
+<td>66</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></td>
+<td>1</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></td>
+<td>0</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal"><span class="pre">e_ident[EI_CLASS]</span></code></dt>
+<dd><p class="first">The ELF class is:</p>
+<ul class="last simple">
+<li><code class="docutils literal"><span class="pre">ELFCLASS32</span></code> for <code class="docutils literal"><span class="pre">r600</span></code> architecture.</li>
+<li><code class="docutils literal"><span class="pre">ELFCLASS64</span></code> for <code class="docutils literal"><span class="pre">amdgcn</span></code> architecture which only supports 64
+bit applications.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal"><span class="pre">e_ident[EI_DATA]</span></code></dt>
+<dd>All AMDGPU targets use <code class="docutils literal"><span class="pre">ELFDATA2LSB</span></code> for little-endian byte ordering.</dd>
+<dt><code class="docutils literal"><span class="pre">e_ident[EI_OSABI]</span></code></dt>
+<dd><p class="first">One of the following AMD GPU architecture specific OS ABIs
+(see <a class="reference internal" href="#amdgpu-os-table"><span class="std std-ref">AMDGPU Operating Systems</span></a>):</p>
+<ul class="last simple">
+<li><code class="docutils literal"><span class="pre">ELFOSABI_NONE</span></code> for <em>unknown</em> OS.</li>
+<li><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code> for <code class="docutils literal"><span class="pre">amdhsa</span></code> OS.</li>
+<li><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code> for <code class="docutils literal"><span class="pre">amdpal</span></code> OS.</li>
+<li><code class="docutils literal"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code> for <code class="docutils literal"><span class="pre">mesa3D</span></code> OS.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal"><span class="pre">e_ident[EI_ABIVERSION]</span></code></dt>
+<dd><p class="first">The ABI version of the AMD GPU architecture specific OS ABI to which the code
+object conforms:</p>
+<ul class="last simple">
+<li><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code> is used to specify the version of AMD HSA
+runtime ABI.</li>
+<li><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code> is used to specify the version of AMD PAL
+runtime ABI.</li>
+<li><code class="docutils literal"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code> is used to specify the version of AMD MESA
+3D runtime ABI.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal"><span class="pre">e_type</span></code></dt>
+<dd><p class="first">Can be one of the following values:</p>
+<dl class="docutils">
+<dt><code class="docutils literal"><span class="pre">ET_REL</span></code></dt>
+<dd>The type produced by the AMD GPU backend compiler as it is relocatable code
+object.</dd>
+<dt><code class="docutils literal"><span class="pre">ET_DYN</span></code></dt>
+<dd>The type produced by the linker as it is a shared code object.</dd>
+</dl>
+<p class="last">The AMD HSA runtime loader requires a <code class="docutils literal"><span class="pre">ET_DYN</span></code> code object.</p>
+</dd>
+<dt><code class="docutils literal"><span class="pre">e_machine</span></code></dt>
+<dd>The value <code class="docutils literal"><span class="pre">EM_AMDGPU</span></code> is used for the machine for all processors supported
+by the <code class="docutils literal"><span class="pre">r600</span></code> and <code class="docutils literal"><span class="pre">amdgcn</span></code> architectures (see
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>). The specific processor is specified in the
+<code class="docutils literal"><span class="pre">EF_AMDGPU_MACH</span></code> bit field of the <code class="docutils literal"><span class="pre">e_flags</span></code> (see
+<a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a>).</dd>
+<dt><code class="docutils literal"><span class="pre">e_entry</span></code></dt>
+<dd>The entry point is 0 as the entry points for individual kernels must be
+selected in order to invoke them through AQL packets.</dd>
+<dt><code class="docutils literal"><span class="pre">e_flags</span></code></dt>
+<dd><p class="first">The AMDGPU backend uses the following ELF header flags:</p>
+<table border="1" class="docutils" id="amdgpu-elf-header-e-flags-table">
+<caption><span class="caption-text">AMDGPU ELF Header <code class="docutils literal"><span class="pre">e_flags</span></code></span><a class="headerlink" href="#amdgpu-elf-header-e-flags-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="42%" />
+<col width="13%" />
+<col width="45%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="2"><strong>AMDGPU Processor Flag</strong></td>
+<td>See <a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH</span></code></td>
+<td>0x000000ff</td>
+<td>AMDGPU processor selection
+mask for
+<code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_xxx</span></code> values
+defined in
+<a class="reference internal" href="#amdgpu-ef-amdgpu-mach-table"><span class="std std-ref">AMDGPU EF_AMDGPU_MACH Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_XNACK</span></code></td>
+<td>0x00000100</td>
+<td>Indicates if the <code class="docutils literal"><span class="pre">xnack</span></code>
+target feature is
+enabled for all code
+contained in the code object.
+See
+<a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="last docutils" id="amdgpu-ef-amdgpu-mach-table">
+<caption><span class="caption-text">AMDGPU <code class="docutils literal"><span class="pre">EF_AMDGPU_MACH</span></code> Values</span><a class="headerlink" href="#amdgpu-ef-amdgpu-mach-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="45%" />
+<col width="14%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+<th class="head">Description (see
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>)</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_NONE</span></code></td>
+<td>0</td>
+<td><em>not specified</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_R600</span></code></td>
+<td>1</td>
+<td><code class="docutils literal"><span class="pre">r600</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_R630</span></code></td>
+<td>2</td>
+<td><code class="docutils literal"><span class="pre">r630</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_RS880</span></code></td>
+<td>3</td>
+<td><code class="docutils literal"><span class="pre">rs880</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_RV670</span></code></td>
+<td>4</td>
+<td><code class="docutils literal"><span class="pre">rv670</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_RV710</span></code></td>
+<td>5</td>
+<td><code class="docutils literal"><span class="pre">rv710</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_RV730</span></code></td>
+<td>6</td>
+<td><code class="docutils literal"><span class="pre">rv730</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_RV770</span></code></td>
+<td>7</td>
+<td><code class="docutils literal"><span class="pre">rv770</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_CEDAR</span></code></td>
+<td>8</td>
+<td><code class="docutils literal"><span class="pre">cedar</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_REDWOOD</span></code></td>
+<td>9</td>
+<td><code class="docutils literal"><span class="pre">redwood</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_SUMO</span></code></td>
+<td>10</td>
+<td><code class="docutils literal"><span class="pre">sumo</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_JUNIPER</span></code></td>
+<td>11</td>
+<td><code class="docutils literal"><span class="pre">juniper</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_CYPRESS</span></code></td>
+<td>12</td>
+<td><code class="docutils literal"><span class="pre">cypress</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_BARTS</span></code></td>
+<td>13</td>
+<td><code class="docutils literal"><span class="pre">barts</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_TURKS</span></code></td>
+<td>14</td>
+<td><code class="docutils literal"><span class="pre">turks</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_CAICOS</span></code></td>
+<td>15</td>
+<td><code class="docutils literal"><span class="pre">caicos</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_R600_CAYMAN</span></code></td>
+<td>16</td>
+<td><code class="docutils literal"><span class="pre">cayman</span></code></td>
+</tr>
+<tr class="row-odd"><td><em>reserved</em></td>
+<td>17-31</td>
+<td>Reserved for <code class="docutils literal"><span class="pre">r600</span></code>
+architecture processors.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX600</span></code></td>
+<td>32</td>
+<td><code class="docutils literal"><span class="pre">gfx600</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX601</span></code></td>
+<td>33</td>
+<td><code class="docutils literal"><span class="pre">gfx601</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX700</span></code></td>
+<td>34</td>
+<td><code class="docutils literal"><span class="pre">gfx700</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX701</span></code></td>
+<td>35</td>
+<td><code class="docutils literal"><span class="pre">gfx701</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX702</span></code></td>
+<td>36</td>
+<td><code class="docutils literal"><span class="pre">gfx702</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX703</span></code></td>
+<td>37</td>
+<td><code class="docutils literal"><span class="pre">gfx703</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX704</span></code></td>
+<td>38</td>
+<td><code class="docutils literal"><span class="pre">gfx704</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX801</span></code></td>
+<td>39</td>
+<td><code class="docutils literal"><span class="pre">gfx801</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX802</span></code></td>
+<td>40</td>
+<td><code class="docutils literal"><span class="pre">gfx802</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX803</span></code></td>
+<td>41</td>
+<td><code class="docutils literal"><span class="pre">gfx803</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX810</span></code></td>
+<td>42</td>
+<td><code class="docutils literal"><span class="pre">gfx810</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX900</span></code></td>
+<td>43</td>
+<td><code class="docutils literal"><span class="pre">gfx900</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX902</span></code></td>
+<td>44</td>
+<td><code class="docutils literal"><span class="pre">gfx902</span></code></td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+</div>
+<div class="section" id="sections">
+<h3><a class="toc-backref" href="#id48">Sections</a><a class="headerlink" href="#sections" title="Permalink to this headline">¶</a></h3>
+<p>An AMDGPU target ELF code object has the standard ELF sections which include:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-sections-table">
+<caption><span class="caption-text">AMDGPU ELF Sections</span><a class="headerlink" href="#amdgpu-elf-sections-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="27%" />
+<col width="24%" />
+<col width="49%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Attributes</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.bss</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_NOBITS</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.data</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.debug_</span></code><em>*</em></td>
+<td><code class="docutils literal"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.dynamic</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_DYNAMIC</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.dynstr</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.dynsym</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.got</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.hash</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_HASH</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.note</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_NOTE</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.rela</span></code><em>name</em></td>
+<td><code class="docutils literal"><span class="pre">SHT_RELA</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.rela.dyn</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_RELA</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.rodata</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.shstrtab</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_STRTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.strtab</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_STRTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">.symtab</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_SYMTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">.text</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal"><span class="pre">SHF_EXECINSTR</span></code></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>These sections have their standard meanings (see <a class="reference internal" href="#elf" id="id15">[ELF]</a>) and are only generated
+if needed.</p>
+<dl class="docutils">
+<dt><code class="docutils literal"><span class="pre">.debug</span></code><em>*</em></dt>
+<dd>The standard DWARF sections. See <a class="reference internal" href="#amdgpu-dwarf"><span class="std std-ref">DWARF</span></a> for information on the
+DWARF produced by the AMDGPU backend.</dd>
+<dt><code class="docutils literal"><span class="pre">.dynamic</span></code>, <code class="docutils literal"><span class="pre">.dynstr</span></code>, <code class="docutils literal"><span class="pre">.dynsym</span></code>, <code class="docutils literal"><span class="pre">.hash</span></code></dt>
+<dd>The standard sections used by a dynamic loader.</dd>
+<dt><code class="docutils literal"><span class="pre">.note</span></code></dt>
+<dd>See <a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a> for the note records supported by the AMDGPU
+backend.</dd>
+<dt><code class="docutils literal"><span class="pre">.rela</span></code><em>name</em>, <code class="docutils literal"><span class="pre">.rela.dyn</span></code></dt>
+<dd><p class="first">For relocatable code objects, <em>name</em> is the name of the section that the
+relocation records apply. For example, <code class="docutils literal"><span class="pre">.rela.text</span></code> is the section name for
+relocation records associated with the <code class="docutils literal"><span class="pre">.text</span></code> section.</p>
+<p>For linked shared code objects, <code class="docutils literal"><span class="pre">.rela.dyn</span></code> contains all the relocation
+records from each of the relocatable code object’s <code class="docutils literal"><span class="pre">.rela</span></code><em>name</em> sections.</p>
+<p class="last">See <a class="reference internal" href="#amdgpu-relocation-records"><span class="std std-ref">Relocation Records</span></a> for the relocation records supported by
+the AMDGPU backend.</p>
+</dd>
+<dt><code class="docutils literal"><span class="pre">.text</span></code></dt>
+<dd>The executable machine code for the kernels and functions they call. Generated
+as position independent code. See <a class="reference internal" href="#amdgpu-code-conventions"><span class="std std-ref">Code Conventions</span></a> for
+information on conventions used in the isa generation.</dd>
+</dl>
+</div>
+<div class="section" id="note-records">
+<span id="amdgpu-note-records"></span><h3><a class="toc-backref" href="#id49">Note Records</a><a class="headerlink" href="#note-records" title="Permalink to this headline">¶</a></h3>
+<p>As required by <code class="docutils literal"><span class="pre">ELFCLASS32</span></code> and <code class="docutils literal"><span class="pre">ELFCLASS64</span></code>, minimal zero byte padding must
+be generated after the <code class="docutils literal"><span class="pre">name</span></code> field to ensure the <code class="docutils literal"><span class="pre">desc</span></code> field is 4 byte
+aligned. In addition, minimal zero byte padding must be generated to ensure the
+<code class="docutils literal"><span class="pre">desc</span></code> field size is a multiple of 4 bytes. The <code class="docutils literal"><span class="pre">sh_addralign</span></code> field of the
+<code class="docutils literal"><span class="pre">.note</span></code> section must be at least 4 to indicate at least 8 byte alignment.</p>
+<p>The AMDGPU backend code object uses the following ELF note records in the
+<code class="docutils literal"><span class="pre">.note</span></code> section. The <em>Description</em> column specifies the layout of the note
+record’s <code class="docutils literal"><span class="pre">desc</span></code> field. All fields are consecutive bytes. Note records with
+variable size strings have a corresponding <code class="docutils literal"><span class="pre">*_size</span></code> field that specifies the
+number of bytes, including the terminating null character, in the string. The
+string(s) come immediately after the preceding fields.</p>
+<p>Additional note records can be present.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-records-table">
+<caption><span class="caption-text">AMDGPU ELF Note Records</span><a class="headerlink" href="#amdgpu-elf-note-records-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="7%" />
+<col width="41%" />
+<col width="52%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>“AMD”</td>
+<td><code class="docutils literal"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
+<td><metadata null terminated string></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-record-enumeration-values-table">
+<caption><span class="caption-text">AMDGPU ELF Note Record Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-note-record-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>reserved</em></td>
+<td>0-9</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
+<td>10</td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td>11</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></dt>
+<dd>Specifies extensible metadata associated with the code objects executed on HSA
+<a class="reference internal" href="#hsa" id="id16">[HSA]</a> compatible runtimes such as AMD’s ROCm <a class="reference internal" href="#amd-rocm" id="id17">[AMD-ROCm]</a>. It is required when
+the target triple OS is <code class="docutils literal"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). See
+<a class="reference internal" href="#amdgpu-amdhsa-hsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a> for the syntax of the code
+object metadata string.</dd>
+</dl>
+</div>
+<div class="section" id="symbols">
+<span id="amdgpu-symbols"></span><h3><a class="toc-backref" href="#id50">Symbols</a><a class="headerlink" href="#symbols" title="Permalink to this headline">¶</a></h3>
+<p>Symbols include the following:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-symbols-table">
+<caption><span class="caption-text">AMDGPU ELF Symbols</span><a class="headerlink" href="#amdgpu-elf-symbols-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="32%" />
+<col width="21%" />
+<col width="20%" />
+<col width="27%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Section</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>link-name</em></td>
+<td><code class="docutils literal"><span class="pre">STT_OBJECT</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">.data</span></code></li>
+<li><code class="docutils literal"><span class="pre">.rodata</span></code></li>
+<li><code class="docutils literal"><span class="pre">.bss</span></code></li>
+</ul>
+</td>
+<td>Global variable</td>
+</tr>
+<tr class="row-odd"><td><em>link-name</em><code class="docutils literal"><span class="pre">@kd</span></code></td>
+<td><code class="docutils literal"><span class="pre">STT_OBJECT</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">.rodata</span></code></li>
+</ul>
+</td>
+<td>Kernel descriptor</td>
+</tr>
+<tr class="row-even"><td><em>link-name</em></td>
+<td><code class="docutils literal"><span class="pre">STT_FUNC</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal"><span class="pre">.text</span></code></li>
+</ul>
+</td>
+<td>Kernel entry point</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt>Global variable</dt>
+<dd><p class="first">Global variables both used and defined by the compilation unit.</p>
+<p>If the symbol is defined in the compilation unit then it is allocated in the
+appropriate section according to if it has initialized data or is readonly.</p>
+<p>If the symbol is external then its section is <code class="docutils literal"><span class="pre">STN_UNDEF</span></code> and the loader
+will resolve relocations using the definition provided by another code object
+or explicitly defined by the runtime.</p>
+<p class="last">All global symbols, whether defined in the compilation unit or external, are
+accessed by the machine code indirectly through a GOT table entry. This
+allows them to be preemptable. The GOT table is only supported when the target
+triple OS is <code class="docutils literal"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+</dd>
+<dt>Kernel descriptor</dt>
+<dd>Every HSA kernel has an associated kernel descriptor. It is the address of the
+kernel descriptor that is used in the AQL dispatch packet used to invoke the
+kernel, not the kernel entry point. The layout of the HSA kernel descriptor is
+defined in <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>.</dd>
+<dt>Kernel entry point</dt>
+<dd>Every HSA kernel also has a symbol for its machine code entry point.</dd>
+</dl>
+</div>
+<div class="section" id="relocation-records">
+<span id="amdgpu-relocation-records"></span><h3><a class="toc-backref" href="#id51">Relocation Records</a><a class="headerlink" href="#relocation-records" title="Permalink to this headline">¶</a></h3>
+<p>AMDGPU backend generates <code class="docutils literal"><span class="pre">Elf64_Rela</span></code> relocation records. Supported
+relocatable fields are:</p>
+<dl class="docutils">
+<dt><code class="docutils literal"><span class="pre">word32</span></code></dt>
+<dd>This specifies a 32-bit field occupying 4 bytes with arbitrary byte
+alignment. These values use the same byte order as other word values in the
+AMD GPU architecture.</dd>
+<dt><code class="docutils literal"><span class="pre">word64</span></code></dt>
+<dd>This specifies a 64-bit field occupying 8 bytes with arbitrary byte
+alignment. These values use the same byte order as other word values in the
+AMD GPU architecture.</dd>
+</dl>
+<p>Following notations are used for specifying relocation calculations:</p>
+<dl class="docutils">
+<dt><strong>A</strong></dt>
+<dd>Represents the addend used to compute the value of the relocatable field.</dd>
+<dt><strong>G</strong></dt>
+<dd>Represents the offset into the global offset table at which the relocation
+entry’s symbol will reside during execution.</dd>
+<dt><strong>GOT</strong></dt>
+<dd>Represents the address of the global offset table.</dd>
+<dt><strong>P</strong></dt>
+<dd>Represents the place (section offset for <code class="docutils literal"><span class="pre">et_rel</span></code> or address for <code class="docutils literal"><span class="pre">et_dyn</span></code>)
+of the storage unit being relocated (computed using <code class="docutils literal"><span class="pre">r_offset</span></code>).</dd>
+<dt><strong>S</strong></dt>
+<dd>Represents the value of the symbol whose index resides in the relocation
+entry. Relocations not using this must specify a symbol index of <code class="docutils literal"><span class="pre">STN_UNDEF</span></code>.</dd>
+<dt><strong>B</strong></dt>
+<dd>Represents the base address of a loaded executable or shared object which is
+the difference between the ELF address and the actual load address. Relocations
+using this are only valid in executable or shared objects.</dd>
+</dl>
+<p>The following relocation types are supported:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-relocation-records-table">
+<caption><span class="caption-text">AMDGPU ELF Relocation Records</span><a class="headerlink" href="#amdgpu-elf-relocation-records-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="37%" />
+<col width="7%" />
+<col width="14%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Relocation Type</th>
+<th class="head">Value</th>
+<th class="head">Field</th>
+<th class="head">Calculation</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">R_AMDGPU_NONE</span></code></td>
+<td>0</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">R_AMDGPU_ABS32_LO</span></code></td>
+<td>1</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>(S + A) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">R_AMDGPU_ABS32_HI</span></code></td>
+<td>2</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>(S + A) >> 32</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">R_AMDGPU_ABS64</span></code></td>
+<td>3</td>
+<td><code class="docutils literal"><span class="pre">word64</span></code></td>
+<td>S + A</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">R_AMDGPU_REL32</span></code></td>
+<td>4</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>S + A - P</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">R_AMDGPU_REL64</span></code></td>
+<td>5</td>
+<td><code class="docutils literal"><span class="pre">word64</span></code></td>
+<td>S + A - P</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">R_AMDGPU_ABS32</span></code></td>
+<td>6</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>S + A</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">R_AMDGPU_GOTPCREL</span></code></td>
+<td>7</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>G + GOT + A - P</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">R_AMDGPU_GOTPCREL32_LO</span></code></td>
+<td>8</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>(G + GOT + A - P) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">R_AMDGPU_GOTPCREL32_HI</span></code></td>
+<td>9</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>(G + GOT + A - P) >> 32</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">R_AMDGPU_REL32_LO</span></code></td>
+<td>10</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>(S + A - P) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">R_AMDGPU_REL32_HI</span></code></td>
+<td>11</td>
+<td><code class="docutils literal"><span class="pre">word32</span></code></td>
+<td>(S + A - P) >> 32</td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td>12</td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">R_AMDGPU_RELATIVE64</span></code></td>
+<td>13</td>
+<td><code class="docutils literal"><span class="pre">word64</span></code></td>
+<td>B + A</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="dwarf">
+<span id="amdgpu-dwarf"></span><h3><a class="toc-backref" href="#id52">DWARF</a><a class="headerlink" href="#dwarf" title="Permalink to this headline">¶</a></h3>
+<p>Standard DWARF <a class="reference internal" href="#id36" id="id18">[DWARF]</a> Version 2 sections can be generated. These contain
+information that maps the code object executable code and data to the source
+language constructs. It can be used by tools such as debuggers and profilers.</p>
+<div class="section" id="address-space-mapping">
+<h4><a class="toc-backref" href="#id53">Address Space Mapping</a><a class="headerlink" href="#address-space-mapping" title="Permalink to this headline">¶</a></h4>
+<p>The following address space mapping is used:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-dwarf-address-space-mapping-table">
+<caption><span class="caption-text">AMDGPU DWARF Address Space Mapping</span><a class="headerlink" href="#amdgpu-dwarf-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="53%" />
+<col width="47%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">DWARF Address Space</th>
+<th class="head">Memory Space</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>1</td>
+<td>Private (Scratch)</td>
+</tr>
+<tr class="row-odd"><td>2</td>
+<td>Local (group/LDS)</td>
+</tr>
+<tr class="row-even"><td><em>omitted</em></td>
+<td>Global</td>
+</tr>
+<tr class="row-odd"><td><em>omitted</em></td>
+<td>Constant</td>
+</tr>
+<tr class="row-even"><td><em>omitted</em></td>
+<td>Generic (Flat)</td>
+</tr>
+<tr class="row-odd"><td><em>not supported</em></td>
+<td>Region (GDS)</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>See <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a> for information on the memory space terminology
+used in the table.</p>
+<p>An <code class="docutils literal"><span class="pre">address_class</span></code> attribute is generated on pointer type DIEs to specify the
+DWARF address space of the value of the pointer when it is in the <em>private</em> or
+<em>local</em> address space. Otherwise the attribute is omitted.</p>
+<p>An <code class="docutils literal"><span class="pre">XDEREF</span></code> operation is generated in location list expressions for variables
+that are allocated in the <em>private</em> and <em>local</em> address space. Otherwise no
+<code class="docutils literal"><span class="pre">XDREF</span></code> is omitted.</p>
+</div>
+<div class="section" id="register-mapping">
+<h4><a class="toc-backref" href="#id54">Register Mapping</a><a class="headerlink" href="#register-mapping" title="Permalink to this headline">¶</a></h4>
+<p><em>This section is WIP.</em></p>
+</div>
+<div class="section" id="source-text">
+<h4><a class="toc-backref" href="#id55">Source Text</a><a class="headerlink" href="#source-text" title="Permalink to this headline">¶</a></h4>
+<p><em>This section is WIP.</em></p>
+</div>
+</div>
+</div>
+<div class="section" id="code-conventions">
+<span id="amdgpu-code-conventions"></span><h2><a class="toc-backref" href="#id56">Code Conventions</a><a class="headerlink" href="#code-conventions" title="Permalink to this headline">¶</a></h2>
+<p>This section provides code conventions used for each supported target triple OS
+(see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="amdhsa">
+<h3><a class="toc-backref" href="#id57">AMDHSA</a><a class="headerlink" href="#amdhsa" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+<code class="docutils literal"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="code-object-metadata">
+<span id="amdgpu-amdhsa-hsa-code-object-metadata"></span><h4><a class="toc-backref" href="#id58">Code Object Metadata</a><a class="headerlink" href="#code-object-metadata" title="Permalink to this headline">¶</a></h4>
+<p>The code object metadata specifies extensible metadata associated with the code
+objects executed on HSA <a class="reference internal" href="#hsa" id="id19">[HSA]</a> compatible runtimes such as AMD’s ROCm
+<a class="reference internal" href="#amd-rocm" id="id20">[AMD-ROCm]</a>. It is specified by the <code class="docutils literal"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code> note record
+(see <a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a>) and is required when the target triple OS is
+<code class="docutils literal"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). It must contain the minimum
+information necessary to support the ROCM kernel queries. For example, the
+segment sizes needed in a dispatch packet. In addition, a high level language
+runtime may require other information to be included. For example, the AMD
+OpenCL runtime records kernel argument information.</p>
+<p>The metadata is specified as a YAML formatted string (see <a class="reference internal" href="#yaml" id="id21">[YAML]</a> and
+<a class="reference internal" href="YamlIO.html"><span class="doc">YAML I/O</span></a>).</p>
+<p>The metadata is represented as a single YAML document comprised of the mapping
+defined in table <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-mapping-table"><span class="std std-ref">AMDHSA Code Object Metadata Mapping</span></a> and
+referenced tables.</p>
+<p>For boolean values, the string values of <code class="docutils literal"><span class="pre">false</span></code> and <code class="docutils literal"><span class="pre">true</span></code> are used for
+false and true respectively.</p>
+<p>Additional information can be added to the mappings. To avoid conflicts, any
+non-AMD key names should be prefixed by “<em>vendor-name</em>.”.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-metadata-mapping-table">
+<caption><span class="caption-text">AMDHSA Code Object Metadata Mapping</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-metadata-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="11%" />
+<col width="15%" />
+<col width="9%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>“Version”</td>
+<td>sequence of
+2 integers</td>
+<td>Required</td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version. Currently 1.</li>
+<li>The second integer is the minor
+version. Currently 0.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>“Printf”</td>
+<td>sequence of
+strings</td>
+<td> </td>
+<td><p class="first">Each string is encoded information
+about a printf function call. The
+encoded information is organized as
+fields separated by colon (‘:’):</p>
+<p><code class="docutils literal"><span class="pre">ID:N:S[0]:S[1]:...:S[N-1]:FormatString</span></code></p>
+<p>where:</p>
+<dl class="last docutils">
+<dt><code class="docutils literal"><span class="pre">ID</span></code></dt>
+<dd>A 32 bit integer as a unique id for
+each printf function call</dd>
+<dt><code class="docutils literal"><span class="pre">N</span></code></dt>
+<dd>A 32 bit integer equal to the number
+of arguments of printf function call
+minus 1</dd>
+<dt><code class="docutils literal"><span class="pre">S[i]</span></code> (where i = 0, 1, ... , N-1)</dt>
+<dd>32 bit integers for the size in bytes
+of the i-th FormatString argument of
+the printf function call</dd>
+<dt>FormatString</dt>
+<dd>The format string passed to the
+printf function call.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>“Kernels”</td>
+<td>sequence of
+mapping</td>
+<td>Required</td>
+<td>Sequence of the mappings for each
+kernel in the code object. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-metadata-mapping-table"><span class="std std-ref">AMDHSA Code Object Kernel Metadata Mapping</span></a>
+for the definition of the mapping.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-metadata-mapping-table">
+<caption><span class="caption-text">AMDHSA Code Object Kernel Metadata Mapping</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-metadata-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="14%" />
+<col width="12%" />
+<col width="8%" />
+<col width="66%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>“Name”</td>
+<td>string</td>
+<td>Required</td>
+<td>Source name of the kernel.</td>
+</tr>
+<tr class="row-odd"><td>“SymbolName”</td>
+<td>string</td>
+<td>Required</td>
+<td>Name of the kernel
+descriptor ELF symbol.</td>
+</tr>
+<tr class="row-even"><td>“Language”</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Source language of the kernel.
+Values include:</p>
+<ul class="last simple">
+<li>“OpenCL C”</li>
+<li>“OpenCL C++”</li>
+<li>“HCC”</li>
+<li>“OpenMP”</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>“LanguageVersion”</td>
+<td>sequence of
+2 integers</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version.</li>
+<li>The second integer is the
+minor version.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>“Attrs”</td>
+<td>mapping</td>
+<td> </td>
+<td>Mapping of kernel attributes.
+See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-mapping-table"><span class="std std-ref">AMDHSA Code Object Kernel Attribute Metadata Mapping</span></a>
+for the mapping definition.</td>
+</tr>
+<tr class="row-odd"><td>“Args”</td>
+<td>sequence of
+mapping</td>
+<td> </td>
+<td>Sequence of mappings of the
+kernel arguments. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-mapping-table"><span class="std std-ref">AMDHSA Code Object Kernel Argument Metadata Mapping</span></a>
+for the definition of the mapping.</td>
+</tr>
+<tr class="row-even"><td>“CodeProps”</td>
+<td>mapping</td>
+<td> </td>
+<td>Mapping of properties related to
+the kernel code. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-mapping-table"><span class="std std-ref">AMDHSA Code Object Kernel Code Properties Metadata Mapping</span></a>
+for the mapping definition.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-attribute-metadata-mapping-table">
+<caption><span class="caption-text">AMDHSA Code Object Kernel Attribute Metadata Mapping</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="19%" />
+<col width="13%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>“ReqdWorkGroupSize”</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">The dispatch work-group size
+X, Y, Z must correspond to the
+specified values.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal"><span class="pre">reqd_work_group_size</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>“WorkGroupSizeHint”</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">The dispatch work-group size
+X, Y, Z is likely to be the
+specified values.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal"><span class="pre">work_group_size_hint</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-even"><td>“VecTypeHint”</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The name of a scalar or vector
+type.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal"><span class="pre">vec_type_hint</span></code> attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>“RuntimeHandle”</td>
+<td>string</td>
+<td> </td>
+<td>The external symbol name
+associated with a kernel.
+OpenCL runtime allocates a
+global buffer for the symbol
+and saves the kernel’s address
+to it, which is used for
+device side enqueueing. Only
+available for device side
+enqueued kernels.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-argument-metadata-mapping-table">
+<caption><span class="caption-text">AMDHSA Code Object Kernel Argument Metadata Mapping</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="22%" />
+<col width="18%" />
+<col width="12%" />
+<col width="49%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>“Name”</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument name.</td>
+</tr>
+<tr class="row-odd"><td>“TypeName”</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument type name.</td>
+</tr>
+<tr class="row-even"><td>“Size”</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument size in bytes.</td>
+</tr>
+<tr class="row-odd"><td>“Align”</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument alignment in
+bytes. Must be a power of two.</td>
+</tr>
+<tr class="row-even"><td>“ValueKind”</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument kind that
+specifies how to set up the
+corresponding argument.
+Values include:</p>
+<dl class="last docutils">
+<dt>“ByValue”</dt>
+<dd>The argument is copied
+directly into the kernarg.</dd>
+<dt>“GlobalBuffer”</dt>
+<dd>A global address space pointer
+to the buffer data is passed
+in the kernarg.</dd>
+<dt>“DynamicSharedPointer”</dt>
+<dd>A group address space pointer
+to dynamically allocated LDS
+is passed in the kernarg.</dd>
+<dt>“Sampler”</dt>
+<dd>A global address space
+pointer to a S# is passed in
+the kernarg.</dd>
+<dt>“Image”</dt>
+<dd>A global address space
+pointer to a T# is passed in
+the kernarg.</dd>
+<dt>“Pipe”</dt>
+<dd>A global address space pointer
+to an OpenCL pipe is passed in
+the kernarg.</dd>
+<dt>“Queue”</dt>
+<dd>A global address space pointer
+to an OpenCL device enqueue
+queue is passed in the
+kernarg.</dd>
+<dt>“HiddenGlobalOffsetX”</dt>
+<dd>The OpenCL grid dispatch
+global offset for the X
+dimension is passed in the
+kernarg.</dd>
+<dt>“HiddenGlobalOffsetY”</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Y
+dimension is passed in the
+kernarg.</dd>
+<dt>“HiddenGlobalOffsetZ”</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Z
+dimension is passed in the
+kernarg.</dd>
+<dt>“HiddenNone”</dt>
+<dd>An argument that is not used
+by the kernel. Space needs to
+be left for it, but it does
+not need to be set up.</dd>
+<dt>“HiddenPrintfBuffer”</dt>
+<dd>A global address space pointer
+to the runtime printf buffer
+is passed in kernarg.</dd>
+<dt>“HiddenDefaultQueue”</dt>
+<dd>A global address space pointer
+to the OpenCL device enqueue
+queue that should be used by
+the kernel by default is
+passed in the kernarg.</dd>
+<dt>“HiddenCompletionAction”</dt>
+<dd>A global address space pointer
+to help link enqueued kernels into
+the ancestor tree for determining
+when the parent kernel has finished.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>“ValueType”</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument value type. Only
+present if “ValueKind” is
+“ByValue”. For vector data
+types, the value is for the
+element type. Values include:</p>
+<ul class="last simple">
+<li>“Struct”</li>
+<li>“I8”</li>
+<li>“U8”</li>
+<li>“I16”</li>
+<li>“U16”</li>
+<li>“F16”</li>
+<li>“I32”</li>
+<li>“U32”</li>
+<li>“F32”</li>
+<li>“I64”</li>
+<li>“U64”</li>
+<li>“F64”</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>“PointeeAlign”</td>
+<td>integer</td>
+<td> </td>
+<td>Alignment in bytes of pointee
+type for pointer type kernel
+argument. Must be a power
+of 2. Only present if
+“ValueKind” is
+“DynamicSharedPointer”.</td>
+</tr>
+<tr class="row-odd"><td>“AddrSpaceQual”</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument address space
+qualifier. Only present if
+“ValueKind” is “GlobalBuffer” or
+“DynamicSharedPointer”. Values
+are:</p>
+<ul class="last simple">
+<li>“Private”</li>
+<li>“Global”</li>
+<li>“Constant”</li>
+<li>“Local”</li>
+<li>“Generic”</li>
+<li>“Region”</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>“AccQual”</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument access
+qualifier. Only present if
+“ValueKind” is “Image” or
+“Pipe”. Values
+are:</p>
+<ul class="last simple">
+<li>“ReadOnly”</li>
+<li>“WriteOnly”</li>
+<li>“ReadWrite”</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>“ActualAccQual”</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The actual memory accesses
+performed by the kernel on the
+kernel argument. Only present if
+“ValueKind” is “GlobalBuffer”,
+“Image”, or “Pipe”. This may be
+more restrictive than indicated
+by “AccQual” to reflect what the
+kernel actual does. If not
+present then the runtime must
+assume what is implied by
+“AccQual” and “IsConst”. Values
+are:</p>
+<ul class="last simple">
+<li>“ReadOnly”</li>
+<li>“WriteOnly”</li>
+<li>“ReadWrite”</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>“IsConst”</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is const qualified. Only present
+if “ValueKind” is
+“GlobalBuffer”.</td>
+</tr>
+<tr class="row-odd"><td>“IsRestrict”</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is restrict qualified. Only
+present if “ValueKind” is
+“GlobalBuffer”.</td>
+</tr>
+<tr class="row-even"><td>“IsVolatile”</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is volatile qualified. Only
+present if “ValueKind” is
+“GlobalBuffer”.</td>
+</tr>
+<tr class="row-odd"><td>“IsPipe”</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is pipe qualified. Only present
+if “ValueKind” is “Pipe”.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-code-properties-metadata-mapping-table">
+<caption><span class="caption-text">AMDHSA Code Object Kernel Code Properties Metadata Mapping</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="38%" />
+<col width="19%" />
+<col width="12%" />
+<col width="30%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>“KernargSegmentSize”</td>
+<td>integer</td>
+<td>Required</td>
+<td>The size in bytes of
+the kernarg segment
+that holds the values
+of the arguments to
+the kernel.</td>
+</tr>
+<tr class="row-odd"><td>“GroupSegmentFixedSize”</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of group
+segment memory
+required by a
+work-group in
+bytes. This does not
+include any
+dynamically allocated
+group segment memory
+that may be added
+when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-even"><td>“PrivateSegmentFixedSize”</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in
+bytes. If the kernel
+uses a dynamic call
+stack then additional
+space must be added
+to this value for the
+call stack.</td>
+</tr>
+<tr class="row-odd"><td>“KernargSegmentAlign”</td>
+<td>integer</td>
+<td>Required</td>
+<td>The maximum byte
+alignment of
+arguments in the
+kernarg segment. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-even"><td>“WavefrontSize”</td>
+<td>integer</td>
+<td>Required</td>
+<td>Wavefront size. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-odd"><td>“NumSGPRs”</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of scalar
+registers used by a
+wavefront for
+GFX6-GFX9. This
+includes the special
+SGPRs for VCC, Flat
+Scratch (GFX7-GFX9)
+and XNACK (for
+GFX8-GFX9). It does
+not include the 16
+SGPR added if a trap
+handler is
+enabled. It is not
+rounded up to the
+allocation
+granularity.</td>
+</tr>
+<tr class="row-even"><td>“NumVGPRs”</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of vector
+registers used by
+each work-item for
+GFX6-GFX9</td>
+</tr>
+<tr class="row-odd"><td>“MaxFlatWorkGroupSize”</td>
+<td>integer</td>
+<td>Required</td>
+<td>Maximum flat
+work-group size
+supported by the
+kernel in work-items.
+Must be >=1 and
+consistent with any
+non-0 values in
+FixedWorkGroupSize.</td>
+</tr>
+<tr class="row-even"><td>“FixedWorkGroupSize”</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td>Corresponds to the
+dispatch work-group
+size X, Y, Z. If
+omitted, defaults to
+0, 0, 0. If an
+element is non-0 then
+the kernel must only
+be launched with a
+matching corresponding
+work-group size.</td>
+</tr>
+<tr class="row-odd"><td>“NumSpilledSGPRs”</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a scalar register to
+a register allocator
+created spill
+location.</td>
+</tr>
+<tr class="row-even"><td>“NumSpilledVGPRs”</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a vector register to
+a register allocator
+created spill
+location.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="kernel-dispatch">
+<h4><a class="toc-backref" href="#id59">Kernel Dispatch</a><a class="headerlink" href="#kernel-dispatch" title="Permalink to this headline">¶</a></h4>
+<p>The HSA architected queuing language (AQL) defines a user space memory interface
+that can be used to control the dispatch of kernels, in an agent independent
+way. An agent can have zero or more AQL queues created for it using the ROCm
+runtime, in which AQL packets (all of which are 64 bytes) can be placed. See the
+<em>HSA Platform System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id22">[HSA]</a> for the AQL queue
+mechanics and packet layouts.</p>
+<p>The packet processor of a kernel agent is responsible for detecting and
+dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the
+packet processor is implemented by the hardware command processor (CP),
+asynchronous dispatch controller (ADC) and shader processor input controller
+(SPI).</p>
+<p>The ROCm runtime can be used to allocate an AQL queue object. It uses the kernel
+mode driver to initialize and register the AQL queue with CP.</p>
+<p>To dispatch a kernel the following actions are performed. This can occur in the
+CPU host program, or from an HSA kernel executing on a GPU.</p>
+<ol class="arabic simple">
+<li>A pointer to an AQL queue for the kernel agent on which the kernel is to be
+executed is obtained.</li>
+<li>A pointer to the kernel descriptor (see
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>) of the kernel to execute is
+obtained. It must be for a kernel that is contained in a code object that that
+was loaded by the ROCm runtime on the kernel agent with which the AQL queue is
+associated.</li>
+<li>Space is allocated for the kernel arguments using the ROCm runtime allocator
+for a memory region with the kernarg property for the kernel agent that will
+execute the kernel. It must be at least 16 byte aligned.</li>
+<li>Kernel argument values are assigned to the kernel argument memory
+allocation. The layout is defined in the <em>HSA Programmer’s Language Reference</em>
+<a class="reference internal" href="#hsa" id="id23">[HSA]</a>. For AMDGPU the kernel execution directly accesses the kernel argument
+memory in the same way constant memory is accessed. (Note that the HSA
+specification allows an implementation to copy the kernel argument contents to
+another location that is accessed by the kernel.)</li>
+<li>An AQL kernel dispatch packet is created on the AQL queue. The ROCm runtime
+api uses 64 bit atomic operations to reserve space in the AQL queue for the
+packet. The packet must be set up, and the final write must use an atomic
+store release to set the packet kind to ensure the packet contents are
+visible to the kernel agent. AQL defines a doorbell signal mechanism to
+notify the kernel agent that the AQL queue has been updated. These rules, and
+the layout of the AQL queue and kernel dispatch packet is defined in the <em>HSA
+System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id24">[HSA]</a>.</li>
+<li>A kernel dispatch packet includes information about the actual dispatch,
+such as grid and work-group size, together with information from the code
+object about the kernel, such as segment sizes. The ROCm runtime queries on
+the kernel symbol can be used to obtain the code object values which are
+recorded in the <a class="reference internal" href="#amdgpu-amdhsa-hsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>.</li>
+<li>CP executes micro-code and is responsible for detecting and setting up the
+GPU to execute the wavefronts of a kernel dispatch.</li>
+<li>CP ensures that when the a wavefront starts executing the kernel machine
+code, the scalar general purpose registers (SGPR) and vector general purpose
+registers (VGPR) are set up as required by the machine code. The required
+setup is defined in the <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>. The initial
+register state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>.</li>
+<li>The prolog of the kernel machine code (see
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-prolog"><span class="std std-ref">Kernel Prolog</span></a>) sets up the machine state as necessary
+before continuing executing the machine code that corresponds to the kernel.</li>
+<li>When the kernel dispatch has completed execution, CP signals the completion
+signal specified in the kernel dispatch packet if not 0.</li>
+</ol>
+</div>
+<div class="section" id="memory-spaces">
+<span id="amdgpu-amdhsa-memory-spaces"></span><h4><a class="toc-backref" href="#id60">Memory Spaces</a><a class="headerlink" href="#memory-spaces" title="Permalink to this headline">¶</a></h4>
+<p>The memory space properties are:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-spaces-table">
+<caption><span class="caption-text">AMDHSA Memory Spaces</span><a class="headerlink" href="#amdgpu-amdhsa-memory-spaces-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="28%" />
+<col width="18%" />
+<col width="13%" />
+<col width="11%" />
+<col width="30%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Memory Space Name</th>
+<th class="head">HSA Segment
+Name</th>
+<th class="head">Hardware
+Name</th>
+<th class="head">Address
+Size</th>
+<th class="head">NULL Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Private</td>
+<td>private</td>
+<td>scratch</td>
+<td>32</td>
+<td>0x00000000</td>
+</tr>
+<tr class="row-odd"><td>Local</td>
+<td>group</td>
+<td>LDS</td>
+<td>32</td>
+<td>0xFFFFFFFF</td>
+</tr>
+<tr class="row-even"><td>Global</td>
+<td>global</td>
+<td>global</td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-odd"><td>Constant</td>
+<td>constant</td>
+<td><em>same as
+global</em></td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-even"><td>Generic</td>
+<td>flat</td>
+<td>flat</td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-odd"><td>Region</td>
+<td>N/A</td>
+<td>GDS</td>
+<td>32</td>
+<td><em>not implemented
+for AMDHSA</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The global and constant memory spaces both use global virtual addresses, which
+are the same virtual address space used by the CPU. However, some virtual
+addresses may only be accessible to the CPU, some only accessible by the GPU,
+and some by both.</p>
+<p>Using the constant memory space indicates that the data will not change during
+the execution of the kernel. This allows scalar read instructions to be
+used. The vector and scalar L1 caches are invalidated of volatile data before
+each kernel dispatch execution to allow constant memory to change values between
+kernel dispatches.</p>
+<p>The local memory space uses the hardware Local Data Store (LDS) which is
+automatically allocated when the hardware creates work-groups of wavefronts, and
+freed when all the wavefronts of a work-group have terminated. The data store
+(DS) instructions can be used to access it.</p>
+<p>The private memory space uses the hardware scratch memory support. If the kernel
+uses scratch, then the hardware allocates memory that is accessed using
+wavefront lane dword (4 byte) interleaving. The mapping used from private
+address to physical address is:</p>
+<blockquote>
+<div><code class="docutils literal"><span class="pre">wavefront-scratch-base</span> <span class="pre">+</span>
+<span class="pre">(private-address</span> <span class="pre">*</span> <span class="pre">wavefront-size</span> <span class="pre">*</span> <span class="pre">4)</span> <span class="pre">+</span>
+<span class="pre">(wavefront-lane-id</span> <span class="pre">*</span> <span class="pre">4)</span></code></div></blockquote>
+<p>There are different ways that the wavefront scratch base address is determined
+by a wavefront (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). This
+memory can be accessed in an interleaved manner using buffer instruction with
+the scratch buffer descriptor and per wave scratch offset, by the scratch
+instructions, or by flat instructions. If each lane of a wavefront accesses the
+same private address, the interleaving results in adjacent dwords being accessed
+and hence requires fewer cache lines to be fetched. Multi-dword access is not
+supported except by flat and scratch instructions in GFX9.</p>
+<p>The generic address space uses the hardware flat address support available in
+GFX7-GFX9. This uses two fixed ranges of virtual addresses (the private and
+local appertures), that are outside the range of addressible global memory, to
+map from a flat address to a private or local address.</p>
+<p>FLAT instructions can take a flat address and access global, private (scratch)
+and group (LDS) memory depending in if the address is within one of the
+apperture ranges. Flat access to scratch requires hardware aperture setup and
+setup in the kernel prologue (see <a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>). Flat
+access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup
+(see <a class="reference internal" href="#amdgpu-amdhsa-m0"><span class="std std-ref">M0</span></a>).</p>
+<p>To convert between a segment address and a flat address the base address of the
+appertures address can be used. For GFX7-GFX8 these are available in the
+<a class="reference internal" href="#amdgpu-amdhsa-hsa-aql-queue"><span class="std std-ref">HSA AQL Queue</span></a> the address of which can be obtained with
+Queue Ptr SGPR (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). For
+GFX9 the appature base addresses are directly available as inline constant
+registers <code class="docutils literal"><span class="pre">SRC_SHARED_BASE/LIMIT</span></code> and <code class="docutils literal"><span class="pre">SRC_PRIVATE_BASE/LIMIT</span></code>. In 64 bit
+address mode the apperture sizes are 2^32 bytes and the base is aligned to 2^32
+which makes it easier to convert from flat to segment or segment to flat.</p>
+</div>
+<div class="section" id="image-and-samplers">
+<h4><a class="toc-backref" href="#id61">Image and Samplers</a><a class="headerlink" href="#image-and-samplers" title="Permalink to this headline">¶</a></h4>
+<p>Image and sample handles created by the ROCm runtime are 64 bit addresses of a
+hardware 32 byte V# and 48 byte S# object respectively. In order to support the
+HSA <code class="docutils literal"><span class="pre">query_sampler</span></code> operations two extra dwords are used to store the HSA BRIG
+enumeration values for the queries that are not trivially deducible from the S#
+representation.</p>
+</div>
+<div class="section" id="hsa-signals">
+<h4><a class="toc-backref" href="#id62">HSA Signals</a><a class="headerlink" href="#hsa-signals" title="Permalink to this headline">¶</a></h4>
+<p>HSA signal handles created by the ROCm runtime are 64 bit addresses of a
+structure allocated in memory accessible from both the CPU and GPU. The
+structure is defined by the ROCm runtime and subject to change between releases
+(see <a class="reference internal" href="#amd-rocm-github" id="id25">[AMD-ROCm-github]</a>).</p>
+</div>
+<div class="section" id="hsa-aql-queue">
+<span id="amdgpu-amdhsa-hsa-aql-queue"></span><h4><a class="toc-backref" href="#id63">HSA AQL Queue</a><a class="headerlink" href="#hsa-aql-queue" title="Permalink to this headline">¶</a></h4>
+<p>The HSA AQL queue structure is defined by the ROCm runtime and subject to change
+between releases (see <a class="reference internal" href="#amd-rocm-github" id="id26">[AMD-ROCm-github]</a>). For some processors it contains
+fields needed to implement certain language features such as the flat address
+aperture bases. It also contains fields used by CP such as managing the
+allocation of scratch memory.</p>
+</div>
+<div class="section" id="kernel-descriptor">
+<span id="amdgpu-amdhsa-kernel-descriptor"></span><h4><a class="toc-backref" href="#id64">Kernel Descriptor</a><a class="headerlink" href="#kernel-descriptor" title="Permalink to this headline">¶</a></h4>
+<p>A kernel descriptor consists of the information needed by CP to initiate the
+execution of a kernel, including the entry point address of the machine code
+that implements the kernel.</p>
+<div class="section" id="kernel-descriptor-for-gfx6-gfx9">
+<h5><a class="toc-backref" href="#id65">Kernel Descriptor for GFX6-GFX9</a><a class="headerlink" href="#kernel-descriptor-for-gfx6-gfx9" title="Permalink to this headline">¶</a></h5>
+<p>CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table">
+<caption><span class="caption-text">Kernel Descriptor for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="7%" />
+<col width="7%" />
+<col width="31%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>31:0</td>
+<td>4 bytes</td>
+<td>GroupSegmentFixedSize</td>
+<td>The amount of fixed local
+address space memory
+required for a work-group
+in bytes. This does not
+include any dynamically
+allocated local address
+space memory that may be
+added when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-odd"><td>63:32</td>
+<td>4 bytes</td>
+<td>PrivateSegmentFixedSize</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in bytes. If
+is_dynamic_callstack is 1
+then additional space must
+be added to this value for
+the call stack.</td>
+</tr>
+<tr class="row-even"><td>127:64</td>
+<td>8 bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>191:128</td>
+<td>8 bytes</td>
+<td>KernelCodeEntryByteOffset</td>
+<td>Byte offset (possibly
+negative) from base
+address of kernel
+descriptor to kernel’s
+entry point instruction
+which must be 256 byte
+aligned.</td>
+</tr>
+<tr class="row-even"><td>223:192</td>
+<td>4 bytes</td>
+<td>MaxFlatWorkGroupSize</td>
+<td>Maximum flat work-group
+size supported by the
+kernel in work-items. If
+an exact work-group size
+is required then must be
+omitted or 0 and
+ReqdWorkGroupSize* must
+be set to non-0.</td>
+</tr>
+<tr class="row-odd"><td>239:224</td>
+<td>2 bytes</td>
+<td>ReqdWorkGroupSizeX</td>
+<td>If present and non-0 then
+the kernel
+must be executed with the
+specified work-group size
+for X.</td>
+</tr>
+<tr class="row-even"><td>255:240</td>
+<td>2 bytes</td>
+<td>ReqdWorkGroupSizeY</td>
+<td>If present and non-0 then
+the kernel
+must be executed with the
+specified work-group size
+for Y.</td>
+</tr>
+<tr class="row-odd"><td>271:256</td>
+<td>2 bytes</td>
+<td>ReqdWorkGroupSizeZ</td>
+<td>If present and non-0 then
+the kernel
+must be executed with the
+specified work-group size
+for Z.</td>
+</tr>
+<tr class="row-even"><td>383:272</td>
+<td>14
+bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>415:384</td>
+<td>4 bytes</td>
+<td>ComputePgmRsrc1</td>
+<td>Compute Shader (CS)
+program settings used by
+CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1</span></code>
+configuration
+register. See
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-even"><td>447:416</td>
+<td>4 bytes</td>
+<td>ComputePgmRsrc2</td>
+<td>Compute Shader (CS)
+program settings used by
+CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2</span></code>
+configuration
+register. See
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX9</span></a>.</td>
+</tr>
+<tr class="row-odd"><td>448</td>
+<td>1 bit</td>
+<td>EnableSGPRPrivateSegmentBuffer</td>
+<td><p class="first">Enable the setup of the
+SGPR user data registers
+(see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">The total number of SGPR
+user data registers
+requested must not exceed
+16 and match value in
+<code class="docutils literal"><span class="pre">compute_pgm_rsrc2.user_sgpr.user_sgpr_count</span></code>.
+Any requests beyond 16
+will be ignored.</p>
+</td>
+</tr>
+<tr class="row-even"><td>449</td>
+<td>1 bit</td>
+<td>EnableSGPRDispatchPtr</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>450</td>
+<td>1 bit</td>
+<td>EnableSGPRQueuePtr</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>451</td>
+<td>1 bit</td>
+<td>EnableSGPRKernargSegmentPtr</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>452</td>
+<td>1 bit</td>
+<td>EnableSGPRDispatchID</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>453</td>
+<td>1 bit</td>
+<td>EnableSGPRFlatScratchInit</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>454</td>
+<td>1 bit</td>
+<td>EnableSGPRPrivateSegmentSize</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>455</td>
+<td>1 bit</td>
+<td>EnableSGPRGridWorkgroupCountX</td>
+<td>Not implemented in CP and
+should always be 0.</td>
+</tr>
+<tr class="row-odd"><td>456</td>
+<td>1 bit</td>
+<td>EnableSGPRGridWorkgroupCountY</td>
+<td>Not implemented in CP and
+should always be 0.</td>
+</tr>
+<tr class="row-even"><td>457</td>
+<td>1 bit</td>
+<td>EnableSGPRGridWorkgroupCountZ</td>
+<td>Not implemented in CP and
+should always be 0.</td>
+</tr>
+<tr class="row-odd"><td>463:458</td>
+<td>6 bits</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-even"><td>511:464</td>
+<td>6
+bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>512</td>
+<td colspan="3"><strong>Total size 64 bytes.</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table">
+<caption><span class="caption-text">compute_pgm_rsrc1 for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="6%" />
+<col width="6%" />
+<col width="26%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>5:0</td>
+<td>6 bits</td>
+<td>GRANULATED_WORKITEM_VGPR_COUNT</td>
+<td><p class="first">Number of vector registers
+used by each work-item,
+granularity is device
+specific:</p>
+<dl class="docutils">
+<dt>GFX6-GFX9</dt>
+<dd><ul class="first last simple">
+<li>max_vgpr 1..256</li>
+<li>roundup((max_vgpg + 1)
+/ 4) - 1</li>
+</ul>
+</dd>
+</dl>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.VGPRS</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>9:6</td>
+<td>4 bits</td>
+<td>GRANULATED_WAVEFRONT_SGPR_COUNT</td>
+<td><p class="first">Number of scalar registers
+used by a wavefront,
+granularity is device
+specific:</p>
+<dl class="docutils">
+<dt>GFX6-GFX8</dt>
+<dd><ul class="first last simple">
+<li>max_sgpr 1..112</li>
+<li>roundup((max_sgpg + 1)
+/ 8) - 1</li>
+</ul>
+</dd>
+<dt>GFX9</dt>
+<dd><ul class="first last simple">
+<li>max_sgpr 1..112</li>
+<li>roundup((max_sgpg + 1)
+/ 16) - 1</li>
+</ul>
+</dd>
+</dl>
+<p>Includes the special SGPRs
+for VCC, Flat Scratch (for
+GFX7 onwards) and XNACK
+(for GFX8 onwards). It does
+not include the 16 SGPR
+added if a trap handler is
+enabled.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.SGPRS</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>11:10</td>
+<td>2 bits</td>
+<td>PRIORITY</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+at the specified priority.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.PRIORITY</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>13:12</td>
+<td>2 bits</td>
+<td>FLOAT_ROUND_MODE_32</td>
+<td><p class="first">Wavefront starts execution
+with specified rounding
+mode for single (32
+bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point rounding
+mode values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>15:14</td>
+<td>2 bits</td>
+<td>FLOAT_ROUND_MODE_16_64</td>
+<td><p class="first">Wavefront starts execution
+with specified rounding
+denorm mode for half/double (16
+and 64 bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point rounding
+mode values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>17:16</td>
+<td>2 bits</td>
+<td>FLOAT_DENORM_MODE_32</td>
+<td><p class="first">Wavefront starts execution
+with specified denorm mode
+for single (32
+bit)  floating point
+precision floating point
+operations.</p>
+<p>Floating point denorm mode
+values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>19:18</td>
+<td>2 bits</td>
+<td>FLOAT_DENORM_MODE_16_64</td>
+<td><p class="first">Wavefront starts execution
+with specified denorm mode
+for half/double (16
+and 64 bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point denorm mode
+values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>20</td>
+<td>1 bit</td>
+<td>PRIV</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+in privilege trap handler
+mode.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.PRIV</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>21</td>
+<td>1 bit</td>
+<td>ENABLE_DX10_CLAMP</td>
+<td><p class="first">Wavefront starts execution
+with DX10 clamp mode
+enabled. Used by the vector
+ALU to force DX10 style
+treatment of NaN’s (when
+set, clamp NaN to zero,
+otherwise pass NaN
+through).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.DX10_CLAMP</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>22</td>
+<td>1 bit</td>
+<td>DEBUG_MODE</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+in single step mode.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.DEBUG_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>23</td>
+<td>1 bit</td>
+<td>ENABLE_IEEE_MODE</td>
+<td><p class="first">Wavefront starts execution
+with IEEE mode
+enabled. Floating point
+opcodes that support
+exception flag gathering
+will quiet and propagate
+signaling-NaN inputs per
+IEEE 754-2008. Min_dx10 and
+max_dx10 become IEEE
+754-2008 compliant due to
+signaling-NaN propagation
+and quieting.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.IEEE_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>24</td>
+<td>1 bit</td>
+<td>BULKY</td>
+<td><p class="first">Must be 0.</p>
+<p>Only one work-group allowed
+to execute on a compute
+unit.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.BULKY</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>25</td>
+<td>1 bit</td>
+<td>CDBG_USER</td>
+<td><p class="first">Must be 0.</p>
+<p>Flag that can be used to
+control debugging code.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.CDBG_USER</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>26</td>
+<td>1 bit</td>
+<td>FP16_OVFL</td>
+<td><dl class="first last docutils">
+<dt>GFX6-GFX8</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX9</dt>
+<dd><p class="first">Wavefront starts execution
+with specified fp16 overflow
+mode.</p>
+<ul class="simple">
+<li>If 0, fp16 overflow generates
++/-INF values.</li>
+<li>If 1, fp16 overflow that is the
+result of an +/-INF input value
+or divide by 0 produces a +/-INF,
+otherwise clamps computed
+overflow to +/-MAX_FP16 as
+appropriate.</li>
+</ul>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC1.FP16_OVFL</span></code>.</p>
+</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>31:27</td>
+<td>5 bits</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>32</td>
+<td colspan="3"><strong>Total size 4 bytes</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table">
+<caption><span class="caption-text">compute_pgm_rsrc2 for GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="6%" />
+<col width="6%" />
+<col width="26%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_PRIVATE_SEGMENT
+_WAVE_OFFSET</td>
+<td><p class="first">Enable the setup of the
+SGPR wave scratch offset
+system register (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.SCRATCH_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>5:1</td>
+<td>5 bits</td>
+<td>USER_SGPR_COUNT</td>
+<td><p class="first">The total number of SGPR
+user data registers
+requested. This number must
+match the number of user
+data registers enabled.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.USER_SGPR</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>6</td>
+<td>1 bit</td>
+<td>ENABLE_TRAP_HANDLER</td>
+<td><p class="first">Set to 1 if code contains a
+TRAP instruction which
+requires a trap handler to
+be enabled.</p>
+<p class="last">CP sets
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.TRAP_PRESENT</span></code>
+if the runtime has
+installed a trap handler
+regardless of the setting
+of this field.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>7</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_X</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the X
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.TGID_X_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>8</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_Y</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the Y
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Y_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>9</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_Z</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the Z
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Z_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>10</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_INFO</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+work-group information (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.TGID_SIZE_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>12:11</td>
+<td>2 bits</td>
+<td>ENABLE_VGPR_WORKITEM_ID</td>
+<td><p class="first">Enable the setup of the
+VGPR system registers used
+for the work-item ID.
+<a class="reference internal" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table"><span class="std std-ref">System VGPR Work-Item ID Enumeration Values</span></a>
+defines the values.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.TIDIG_CMP_CNT</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>13</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_ADDRESS_WATCH</td>
+<td><p class="first">Must be 0.</p>
+<p>Wavefront starts execution
+with address watch
+exceptions enabled which
+are generated when L1 has
+witnessed a thread access
+an <em>address of
+interest</em>.</p>
+<p class="last">CP is responsible for
+filling in the address
+watch bit in
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
+according to what the
+runtime requests.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>14</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_MEMORY</td>
+<td><p class="first">Must be 0.</p>
+<p>Wavefront starts execution
+with memory violation
+exceptions exceptions
+enabled which are generated
+when a memory violation has
+occurred for this wave from
+L1 or LDS
+(write-to-read-only-memory,
+mis-aligned atomic, LDS
+address out of range,
+illegal address, etc.).</p>
+<p class="last">CP sets the memory
+violation bit in
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
+according to what the
+runtime requests.</p>
+</td>
+</tr>
+<tr class="row-even"><td>23:15</td>
+<td>9 bits</td>
+<td>GRANULATED_LDS_SIZE</td>
+<td><p class="first">Must be 0.</p>
+<p>CP uses the rounded value
+from the dispatch packet,
+not this value, as the
+dispatch may contain
+dynamically allocated group
+segment memory. CP writes
+directly to
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.LDS_SIZE</span></code>.</p>
+<p>Amount of group segment
+(LDS) to allocate for each
+work-group. Granularity is
+device specific:</p>
+<dl class="last docutils">
+<dt>GFX6:</dt>
+<dd>roundup(lds-size / (64 * 4))</dd>
+<dt>GFX7-GFX9:</dt>
+<dd>roundup(lds-size / (128 * 4))</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>24</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_INVALID_OPERATION</td>
+<td><p class="first">Wavefront starts execution
+with specified exceptions
+enabled.</p>
+<p>Used by CP to set up
+<code class="docutils literal"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN</span></code>
+(set from bits 0..6).</p>
+<p class="last">IEEE 754 FP Invalid
+Operation</p>
+</td>
+</tr>
+<tr class="row-even"><td>25</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_FP_DENORMAL
+_SOURCE</td>
+<td>FP Denormal one or more
+input operands is a
+denormal number</td>
+</tr>
+<tr class="row-odd"><td>26</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_DIVISION_BY_ZERO</td>
+<td>IEEE 754 FP Division by
+Zero</td>
+</tr>
+<tr class="row-even"><td>27</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_OVERFLOW</td>
+<td>IEEE 754 FP FP Overflow</td>
+</tr>
+<tr class="row-odd"><td>28</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_UNDERFLOW</td>
+<td>IEEE 754 FP Underflow</td>
+</tr>
+<tr class="row-even"><td>29</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_INEXACT</td>
+<td>IEEE 754 FP Inexact</td>
+</tr>
+<tr class="row-odd"><td>30</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_INT_DIVIDE_BY
+_ZERO</td>
+<td>Integer Division by Zero
+(rcp_iflag_f32 instruction
+only)</td>
+</tr>
+<tr class="row-even"><td>31</td>
+<td>1 bit</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>32</td>
+<td colspan="3"><strong>Total size 4 bytes.</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table">
+<caption><span class="caption-text">Floating Point Rounding Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="52%" />
+<col width="7%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>AMDGPU_FLOAT_ROUND_MODE_NEAR_EVEN</td>
+<td>0</td>
+<td>Round Ties To Even</td>
+</tr>
+<tr class="row-odd"><td>AMDGPU_FLOAT_ROUND_MODE_PLUS_INFINITY</td>
+<td>1</td>
+<td>Round Toward +infinity</td>
+</tr>
+<tr class="row-even"><td>AMDGPU_FLOAT_ROUND_MODE_MINUS_INFINITY</td>
+<td>2</td>
+<td>Round Toward -infinity</td>
+</tr>
+<tr class="row-odd"><td>AMDGPU_FLOAT_ROUND_MODE_ZERO</td>
+<td>3</td>
+<td>Round Toward 0</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table">
+<caption><span class="caption-text">Floating Point Denorm Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="52%" />
+<col width="7%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>AMDGPU_FLOAT_DENORM_MODE_FLUSH_SRC_DST</td>
+<td>0</td>
+<td>Flush Source and Destination
+Denorms</td>
+</tr>
+<tr class="row-odd"><td>AMDGPU_FLOAT_DENORM_MODE_FLUSH_DST</td>
+<td>1</td>
+<td>Flush Output Denorms</td>
+</tr>
+<tr class="row-even"><td>AMDGPU_FLOAT_DENORM_MODE_FLUSH_SRC</td>
+<td>2</td>
+<td>Flush Source Denorms</td>
+</tr>
+<tr class="row-odd"><td>AMDGPU_FLOAT_DENORM_MODE_FLUSH_NONE</td>
+<td>3</td>
+<td>No Flush</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table">
+<caption><span class="caption-text">System VGPR Work-Item ID Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="55%" />
+<col width="7%" />
+<col width="38%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X</td>
+<td>0</td>
+<td>Set work-item X dimension
+ID.</td>
+</tr>
+<tr class="row-odd"><td>AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X_Y</td>
+<td>1</td>
+<td>Set work-item X and Y
+dimensions ID.</td>
+</tr>
+<tr class="row-even"><td>AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z</td>
+<td>2</td>
+<td>Set work-item X, Y and Z
+dimensions ID.</td>
+</tr>
+<tr class="row-odd"><td>AMDGPU_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED</td>
+<td>3</td>
+<td>Undefined.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="initial-kernel-execution-state">
+<span id="amdgpu-amdhsa-initial-kernel-execution-state"></span><h4><a class="toc-backref" href="#id66">Initial Kernel Execution State</a><a class="headerlink" href="#initial-kernel-execution-state" title="Permalink to this headline">¶</a></h4>
+<p>This section defines the register state that will be set up by the packet
+processor prior to the start of execution of every wavefront. This is limited by
+the constraints of the hardware controllers of CP/ADC/SPI.</p>
+<p>The order of the SGPR registers is defined, but the compiler can specify which
+ones are actually setup in the kernel descriptor using the <code class="docutils literal"><span class="pre">enable_sgpr_*</span></code> bit
+fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
+for enabled registers are dense starting at SGPR0: the first enabled register is
+SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have
+an SGPR number.</p>
+<p>The initial SGPRs comprise up to 16 User SRGPs that are set by CP and apply to
+all waves of the grid. It is possible to specify more than 16 User SGPRs using
+the <code class="docutils literal"><span class="pre">enable_sgpr_*</span></code> bit fields, in which case only the first 16 are actually
+initialized. These are then immediately followed by the System SGPRs that are
+set up by ADC/SPI and can have different values for each wave of the grid
+dispatch.</p>
+<p>SGPR register initial state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table"><span class="std std-ref">SGPR Register Set Up Order</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-sgpr-register-set-up-order-table">
+<caption><span class="caption-text">SGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="13%" />
+<col width="34%" />
+<col width="8%" />
+<col width="45%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">SGPR Order</th>
+<th class="head">Name
+(kernel descriptor enable
+field)</th>
+<th class="head">Number
+of
+SGPRs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>First</td>
+<td>Private Segment Buffer
+(enable_sgpr_private
+_segment_buffer)</td>
+<td>4</td>
+<td><p class="first">V# that can be used, together
+with Scratch Wave Offset as an
+offset, to access the private
+memory space using a segment
+address.</p>
+<p class="last">CP uses the value provided by
+the runtime.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Dispatch Ptr
+(enable_sgpr_dispatch_ptr)</td>
+<td>2</td>
+<td>64 bit address of AQL dispatch
+packet for kernel dispatch
+actually executing.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Queue Ptr
+(enable_sgpr_queue_ptr)</td>
+<td>2</td>
+<td>64 bit address of amd_queue_t
+object for AQL queue on which
+the dispatch packet was
+queued.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Kernarg Segment Ptr
+(enable_sgpr_kernarg
+_segment_ptr)</td>
+<td>2</td>
+<td><p class="first">64 bit address of Kernarg
+segment. This is directly
+copied from the
+kernarg_address in the kernel
+dispatch packet.</p>
+<p class="last">Having CP load it once avoids
+loading it at the beginning of
+every wavefront.</p>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Dispatch Id
+(enable_sgpr_dispatch_id)</td>
+<td>2</td>
+<td>64 bit Dispatch ID of the
+dispatch packet being
+executed.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Flat Scratch Init
+(enable_sgpr_flat_scratch
+_init)</td>
+<td>2</td>
+<td><p class="first">This is 2 SGPRs:</p>
+<dl class="last docutils">
+<dt>GFX6</dt>
+<dd>Not supported.</dd>
+<dt>GFX7-GFX8</dt>
+<dd><p class="first">The first SGPR is a 32 bit
+byte offset from
+<code class="docutils literal"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+to per SPI base of memory
+for scratch for the queue
+executing the kernel
+dispatch. CP obtains this
+from the runtime. (The
+Scratch Segment Buffer base
+address is
+<code class="docutils literal"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+plus this offset.) The value
+of Scratch Wave Offset must
+be added to this offset by
+the kernel machine code,
+right shifted by 8, and
+moved to the FLAT_SCRATCH_HI
+SGPR register.
+FLAT_SCRATCH_HI corresponds
+to SGPRn-4 on GFX7, and
+SGPRn-6 on GFX8 (where SGPRn
+is the highest numbered SGPR
+allocated to the wave).
+FLAT_SCRATCH_HI is
+multiplied by 256 (as it is
+in units of 256 bytes) and
+added to
+<code class="docutils literal"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+to calculate the per wave
+FLAT SCRATCH BASE in flat
+memory instructions that
+access the scratch
+apperture.</p>
+<p class="last">The second SGPR is 32 bit
+byte size of a single
+work-item’s scratch memory
+usage. CP obtains this from
+the runtime, and it is
+always a multiple of DWORD.
+CP checks that the value in
+the kernel dispatch packet
+Private Segment Byte Size is
+not larger, and requests the
+runtime to increase the
+queue’s scratch size if
+necessary. The kernel code
+must move it to
+FLAT_SCRATCH_LO which is
+SGPRn-3 on GFX7 and SGPRn-5
+on GFX8. FLAT_SCRATCH_LO is
+used as the FLAT SCRATCH
+SIZE in flat memory
+instructions. Having CP load
+it once avoids loading it at
+the beginning of every
+wavefront.</p>
+</dd>
+<dt>GFX9</dt>
+<dd>This is the
+64 bit base address of the
+per SPI scratch backing
+memory managed by SPI for
+the queue executing the
+kernel dispatch. CP obtains
+this from the runtime (and
+divides it if there are
+multiple Shader Arrays each
+with its own SPI). The value
+of Scratch Wave Offset must
+be added by the kernel
+machine code and the result
+moved to the FLAT_SCRATCH
+SGPR which is SGPRn-6 and
+SGPRn-5. It is used as the
+FLAT SCRATCH BASE in flat
+memory instructions.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Private Segment Size</td>
+<td>1</td>
+<td><p class="first">The 32 bit byte size of a
+(enable_sgpr_private single
+work-item’s
+scratch_segment_size) memory
+allocation. This is the
+value from the kernel
+dispatch packet Private
+Segment Byte Size rounded up
+by CP to a multiple of
+DWORD.</p>
+<p>Having CP load it once avoids
+loading it at the beginning of
+every wavefront.</p>
+<p class="last">This is not used for
+GFX7-GFX8 since it is the same
+value as the second SGPR of
+Flat Scratch Init. However, it
+may be needed for GFX9 which
+changes the meaning of the
+Flat Scratch Init value.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Grid Work-Group Count X
+(enable_sgpr_grid
+_workgroup_count_X)</td>
+<td>1</td>
+<td>32 bit count of the number of
+work-groups in the X dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.x +
+workgroup_size.x - 1) /
+workgroup_size.x).</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Grid Work-Group Count Y
+(enable_sgpr_grid
+_workgroup_count_Y &&
+less than 16 previous
+SGPRs)</td>
+<td>1</td>
+<td><p class="first">32 bit count of the number of
+work-groups in the Y dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.y +
+workgroup_size.y - 1) /
+workgroupSize.y).</p>
+<p class="last">Only initialized if <16
+previous SGPRs initialized.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Grid Work-Group Count Z
+(enable_sgpr_grid
+_workgroup_count_Z &&
+less than 16 previous
+SGPRs)</td>
+<td>1</td>
+<td><p class="first">32 bit count of the number of
+work-groups in the Z dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.z +
+workgroup_size.z - 1) /
+workgroupSize.z).</p>
+<p class="last">Only initialized if <16
+previous SGPRs initialized.</p>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Group Id X
+(enable_sgpr_workgroup_id
+_X)</td>
+<td>1</td>
+<td>32 bit work-group id in X
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Group Id Y
+(enable_sgpr_workgroup_id
+_Y)</td>
+<td>1</td>
+<td>32 bit work-group id in Y
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Group Id Z
+(enable_sgpr_workgroup_id
+_Z)</td>
+<td>1</td>
+<td>32 bit work-group id in Z
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Group Info
+(enable_sgpr_workgroup
+_info)</td>
+<td>1</td>
+<td>{first_wave, 14’b0000,
+ordered_append_term[10:0],
+threadgroup_size_in_waves[5:0]}</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Scratch Wave Offset
+(enable_sgpr_private
+_segment_wave_offset)</td>
+<td>1</td>
+<td>32 bit byte offset from base
+of scratch base of queue
+executing the kernel
+dispatch. Must be used as an
+offset with Private
+segment address when using
+Scratch Segment Buffer. It
+must be used to set up FLAT
+SCRATCH for flat addressing
+(see
+<a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The order of the VGPR registers is defined, but the compiler can specify which
+ones are actually setup in the kernel descriptor using the <code class="docutils literal"><span class="pre">enable_vgpr*</span></code> bit
+fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
+for enabled registers are dense starting at VGPR0: the first enabled register is
+VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
+VGPR number.</p>
+<p>VGPR register initial state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table"><span class="std std-ref">VGPR Register Set Up Order</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-vgpr-register-set-up-order-table">
+<caption><span class="caption-text">VGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="14%" />
+<col width="36%" />
+<col width="8%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">VGPR Order</th>
+<th class="head">Name
+(kernel descriptor enable
+field)</th>
+<th class="head">Number
+of
+VGPRs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>First</td>
+<td>Work-Item Id X
+(Always initialized)</td>
+<td>1</td>
+<td>32 bit work item id in X
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Item Id Y
+(enable_vgpr_workitem_id
+> 0)</td>
+<td>1</td>
+<td>32 bit work item id in Y
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Item Id Z
+(enable_vgpr_workitem_id
+> 1)</td>
+<td>1</td>
+<td>32 bit work item id in Z
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The setting of registers is is done by GPU CP/ADC/SPI hardware as follows:</p>
+<ol class="arabic simple">
+<li>SGPRs before the Work-Group Ids are set by CP using the 16 User Data
+registers.</li>
+<li>Work-group Id registers X, Y, Z are set by ADC which supports any
+combination including none.</li>
+<li>Scratch Wave Offset is set by SPI in a per wave basis which is why its value
+cannot included with the flat scratch init value which is per queue.</li>
+<li>The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
+or (X, Y, Z).</li>
+</ol>
+<p>Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64 bit
+value to the hardware required SGPRn-3 and SGPRn-4 respectively.</p>
+<p>The global segment can be accessed either using buffer instructions (GFX6 which
+has V# 64 bit address support), flat instructions (GFX7-GFX9), or global
+instructions (GFX9).</p>
+<p>If buffer operations are used then the compiler can generate a V# with the
+following properties:</p>
+<ul class="simple">
+<li>base address of 0</li>
+<li>no swizzle</li>
+<li>ATC: 1 if IOMMU present (such as APU)</li>
+<li>ptr64: 1</li>
+<li>MTYPE set to support memory coherence that matches the runtime (such as CC for
+APU and NC for dGPU).</li>
+</ul>
+</div>
+<div class="section" id="kernel-prolog">
+<span id="amdgpu-amdhsa-kernel-prolog"></span><h4><a class="toc-backref" href="#id67">Kernel Prolog</a><a class="headerlink" href="#kernel-prolog" title="Permalink to this headline">¶</a></h4>
+<div class="section" id="m0">
+<span id="amdgpu-amdhsa-m0"></span><h5><a class="toc-backref" href="#id68">M0</a><a class="headerlink" href="#m0" title="Permalink to this headline">¶</a></h5>
+<dl class="docutils">
+<dt>GFX6-GFX8</dt>
+<dd>The M0 register must be initialized with a value at least the total LDS size
+if the kernel may access LDS via DS or flat operations. Total LDS size is
+available in dispatch packet. For M0, it is also possible to use maximum
+possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for
+GFX7-GFX8).</dd>
+<dt>GFX9</dt>
+<dd>The M0 register is not used for range checking LDS accesses and so does not
+need to be initialized in the prolog.</dd>
+</dl>
+</div>
+<div class="section" id="flat-scratch">
+<span id="amdgpu-amdhsa-flat-scratch"></span><h5><a class="toc-backref" href="#id69">Flat Scratch</a><a class="headerlink" href="#flat-scratch" title="Permalink to this headline">¶</a></h5>
+<p>If the kernel may use flat operations to access scratch memory, the prolog code
+must set up FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which
+are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wave
+Offset SGPR registers (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>):</p>
+<dl class="docutils">
+<dt>GFX6</dt>
+<dd>Flat scratch is not supported.</dd>
+<dt>GFX7-GFX8</dt>
+<dd><ol class="first last arabic simple">
+<li>The low word of Flat Scratch Init is 32 bit byte offset from
+<code class="docutils literal"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code> to the base of scratch backing memory
+being managed by SPI for the queue executing the kernel dispatch. This is
+the same value used in the Scratch Segment Buffer V# base address. The
+prolog must add the value of Scratch Wave Offset to get the wave’s byte
+scratch backing memory offset from <code class="docutils literal"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>. Since
+FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right shifted
+by 8 before moving into FLAT_SCRATCH_LO.</li>
+<li>The second word of Flat Scratch Init is 32 bit byte size of a single
+work-items scratch memory usage. This is directly loaded from the kernel
+dispatch packet Private Segment Byte Size and rounded up to a multiple of
+DWORD. Having CP load it once avoids loading it at the beginning of every
+wavefront. The prolog must move it to FLAT_SCRATCH_LO for use as FLAT SCRATCH
+SIZE.</li>
+</ol>
+</dd>
+<dt>GFX9</dt>
+<dd>The Flat Scratch Init is the 64 bit address of the base of scratch backing
+memory being managed by SPI for the queue executing the kernel dispatch. The
+prolog must add the value of Scratch Wave Offset and moved to the FLAT_SCRATCH
+pair for use as the flat scratch base in flat memory instructions.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="memory-model">
+<span id="amdgpu-amdhsa-memory-model"></span><h4><a class="toc-backref" href="#id70">Memory Model</a><a class="headerlink" href="#memory-model" title="Permalink to this headline">¶</a></h4>
+<p>This section describes the mapping of LLVM memory model onto AMDGPU machine code
+(see <a class="reference internal" href="LangRef.html#memmodel"><span class="std std-ref">Memory Model for Concurrent Operations</span></a>). <em>The implementation is WIP.</em></p>
+<p>The AMDGPU backend supports the memory synchronization scopes specified in
+<a class="reference internal" href="#amdgpu-memory-scopes"><span class="std std-ref">Memory Scopes</span></a>.</p>
+<p>The code sequences used to implement the memory model are defined in table
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table"><span class="std std-ref">AMDHSA Memory Model Code Sequences GFX6-GFX9</span></a>.</p>
+<p>The sequences specify the order of instructions that a single thread must
+execute. The <code class="docutils literal"><span class="pre">s_waitcnt</span></code> and <code class="docutils literal"><span class="pre">buffer_wbinvl1_vol</span></code> are defined with respect
+to other memory instructions executed by the same thread. This allows them to be
+moved earlier or later which can allow them to be combined with other instances
+of the same instruction, or hoisted/sunk out of loops to improve
+performance. Only the instructions related to the memory model are given;
+additional <code class="docutils literal"><span class="pre">s_waitcnt</span></code> instructions are required to ensure registers are
+defined before being used. These may be able to be combined with the memory
+model <code class="docutils literal"><span class="pre">s_waitcnt</span></code> instructions as described above.</p>
+<p>The AMDGPU backend supports the following memory models:</p>
+<blockquote>
+<div><dl class="docutils">
+<dt>HSA Memory Model <a class="reference internal" href="#hsa" id="id27">[HSA]</a></dt>
+<dd>The HSA memory model uses a single happens-before relation for all address
+spaces (see <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a>).</dd>
+<dt>OpenCL Memory Model <a class="reference internal" href="#id37" id="id28">[OpenCL]</a></dt>
+<dd>The OpenCL memory model which has separate happens-before relations for the
+global and local address spaces. Only a fence specifying both global and
+local address space, and seq_cst instructions join the relationships. Since
+the LLVM <code class="docutils literal"><span class="pre">memfence</span></code> instruction does not allow an address space to be
+specified the OpenCL fence has to convervatively assume both local and
+global address space was specified. However, optimizations can often be
+done to eliminate the additional <code class="docutils literal"><span class="pre">s_waitcnt</span></code> instructions when there are
+no intervening memory instructions which access the corresponding address
+space. The code sequences in the table indicate what can be omitted for the
+OpenCL memory. The target triple environment is used to determine if the
+source language is OpenCL (see <a class="reference internal" href="#amdgpu-opencl"><span class="std std-ref">OpenCL</span></a>).</dd>
+</dl>
+</div></blockquote>
+<p><code class="docutils literal"><span class="pre">ds/flat_load/store/atomic</span></code> instructions to local memory are termed LDS
+operations.</p>
+<p><code class="docutils literal"><span class="pre">buffer/global/flat_load/store/atomic</span></code> instructions to global memory are
+termed vector memory operations.</p>
+<p>For GFX6-GFX9:</p>
+<ul class="simple">
+<li>Each agent has multiple compute units (CU).</li>
+<li>Each CU has multiple SIMDs that execute wavefronts.</li>
+<li>The wavefronts for a single work-group are executed in the same CU but may be
+executed by different SIMDs.</li>
+<li>Each CU has a single LDS memory shared by the wavefronts of the work-groups
+executing on it.</li>
+<li>All LDS operations of a CU are performed as wavefront wide operations in a
+global order and involve no caching. Completion is reported to a wavefront in
+execution order.</li>
+<li>The LDS memory has multiple request queues shared by the SIMDs of a
+CU. Therefore, the LDS operations performed by different waves of a work-group
+can be reordered relative to each other, which can result in reordering the
+visibility of vector memory operations with respect to LDS operations of other
+wavefronts in the same work-group. A <code class="docutils literal"><span class="pre">s_waitcnt</span> <span class="pre">lgkmcnt(0)</span></code> is required to
+ensure synchronization between LDS operations and vector memory operations
+between waves of a work-group, but not between operations performed by the
+same wavefront.</li>
+<li>The vector memory operations are performed as wavefront wide operations and
+completion is reported to a wavefront in execution order. The exception is
+that for GFX7-GFX9 <code class="docutils literal"><span class="pre">flat_load/store/atomic</span></code> instructions can report out of
+vector memory order if they access LDS memory, and out of LDS operation order
+if they access global memory.</li>
+<li>The vector memory operations access a single vector L1 cache shared by all
+SIMDs a CU. Therefore, no special action is required for coherence between the
+lanes of a single wavefront, or for coherence between wavefronts in the same
+work-group. A <code class="docutils literal"><span class="pre">buffer_wbinvl1_vol</span></code> is required for coherence between waves
+executing in different work-groups as they may be executing on different CUs.</li>
+<li>The scalar memory operations access a scalar L1 cache shared by all wavefronts
+on a group of CUs. The scalar and vector L1 caches are not coherent. However,
+scalar operations are used in a restricted way so do not impact the memory
+model. See <a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</li>
+<li>The vector and scalar memory operations use an L2 cache shared by all CUs on
+the same agent.</li>
+<li>The L2 cache has independent channels to service disjoint ranges of virtual
+addresses.</li>
+<li>Each CU has a separate request queue per channel. Therefore, the vector and
+scalar memory operations performed by waves executing in different work-groups
+(which may be executing on different CUs) of an agent can be reordered
+relative to each other. A <code class="docutils literal"><span class="pre">s_waitcnt</span> <span class="pre">vmcnt(0)</span></code> is required to ensure
+synchronization between vector memory operations of different CUs. It ensures a
+previous vector memory operation has completed before executing a subsequent
+vector memory or LDS operation and so can be used to meet the requirements of
+acquire and release.</li>
+<li>The L2 cache can be kept coherent with other agents on some targets, or ranges
+of virtual addresses can be set up to bypass it to ensure system coherence.</li>
+</ul>
+<p>Private address space uses <code class="docutils literal"><span class="pre">buffer_load/store</span></code> using the scratch V# (GFX6-GFX8),
+or <code class="docutils literal"><span class="pre">scratch_load/store</span></code> (GFX9). Since only a single thread is accessing the
+memory, atomic memory orderings are not meaningful and all accesses are treated
+as non-atomic.</p>
+<p>Constant address space uses <code class="docutils literal"><span class="pre">buffer/global_load</span></code> instructions (or equivalent
+scalar memory instructions). Since the constant address space contents do not
+change during the execution of a kernel dispatch it is not legal to perform
+stores, and atomic memory orderings are not meaningful and all access are
+treated as non-atomic.</p>
+<p>A memory synchronization scope wider than work-group is not meaningful for the
+group (LDS) address space and is treated as work-group.</p>
+<p>The memory model does not support the region address space which is treated as
+non-atomic.</p>
+<p>Acquire memory ordering is not meaningful on store atomic instructions and is
+treated as non-atomic.</p>
+<p>Release memory ordering is not meaningful on load atomic instructions and is
+treated a non-atomic.</p>
+<p>Acquire-release memory ordering is not meaningful on load or store atomic
+instructions and is treated as acquire and release respectively.</p>
+<p>AMDGPU backend only uses scalar memory operations to access memory that is
+proven to not change during the execution of the kernel dispatch. This includes
+constant address space and global address space for program scope const
+variables. Therefore the kernel machine code does not have to maintain the
+scalar L1 cache to ensure it is coherent with the vector L1 cache. The scalar
+and vector L1 caches are invalidated between kernel dispatches by CP since
+constant address space data may change between kernel dispatch executions. See
+<a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</p>
+<p>The one execption is if scalar writes are used to spill SGPR registers. In this
+case the AMDGPU backend ensures the memory location used to spill is never
+accessed by vector memory operations at the same time. If scalar writes are used
+then a <code class="docutils literal"><span class="pre">s_dcache_wb</span></code> is inserted before the <code class="docutils literal"><span class="pre">s_endpgm</span></code> and before a function
+return since the locations may be used for vector memory instructions by a
+future wave that uses the same scratch area, or a function call that creates a
+frame at the same address, respectively. There is no need for a <code class="docutils literal"><span class="pre">s_dcache_inv</span></code>
+as all scalar writes are write-before-read in the same thread.</p>
+<p>Scratch backing memory (which is used for the private address space)
+is accessed with MTYPE NC_NV (non-coherenent non-volatile). Since the private
+address space is only accessed by a single thread, and is always
+write-before-read, there is never a need to invalidate these entries from the L1
+cache. Hence all cache invalidates are done as <code class="docutils literal"><span class="pre">*_vol</span></code> to only invalidate the
+volatile cache lines.</p>
+<p>On dGPU the kernarg backing memory is accessed as UC (uncached) to avoid needing
+to invalidate the L2 cache. This also causes it to be treated as
+non-volatile and so is not invalidated by <code class="docutils literal"><span class="pre">*_vol</span></code>. On APU it is accessed as CC
+(cache coherent) and so the L2 cache will coherent with the CPU and other
+agents.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table">
+<caption><span class="caption-text">AMDHSA Memory Model Code Sequences GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="15%" />
+<col width="15%" />
+<col width="18%" />
+<col width="13%" />
+<col width="39%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Instr</th>
+<th class="head">LLVM Memory
+Ordering</th>
+<th class="head">LLVM Memory
+Sync Scope</th>
+<th class="head">AMDGPU
+Address
+Space</th>
+<th class="head">AMDGPU Machine Code</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="5"><strong>Non-Atomic</strong></td>
+</tr>
+<tr class="row-odd"><td>load</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+<li>private</li>
+<li>constant</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>!volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load</li>
+</ol>
+</li>
+<li>volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+glc=1</li>
+</ol>
+</li>
+<li>nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+glc=1 slc=1</li>
+</ol>
+</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>load</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+<li>private</li>
+<li>constant</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>!nontemporal<ol class="arabic">
+<li>buffer/global/flat_store</li>
+</ol>
+</li>
+<li>nontemporal<ol class="arabic">
+<li>buffer/global/flat_stote
+glc=1 slc=1</li>
+</ol>
+</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>store</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Unordered Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as non-atomic</em>.</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as non-atomic</em>.</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as monotonic
+atomic</em>.</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Monotonic Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load
+glc=1</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Acquire Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_load</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global/flat_load
+glc=1</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the load
+has completed
+before invalidating
+the cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following
+loads will not see
+stale global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load glc=1</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the flat_load
+has completed
+before invalidating
+the cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_atomic</li>
+<li>waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global/flat_atomic</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+value read by the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+the following
+buffer_wbinvl1_vol.</li>
+<li>Ensures that the
+fence-paired atomic
+has completed
+before invalidating
+the
+cache. Therefore
+any following
+locations read must
+be no older than
+the value read by
+the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before any
+following global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Release Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to memory have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global and local
+have completed
+before performing
+the atomicrmw that
+is being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Acquire-Release Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_atomic</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However,
+since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Must happen after
+any preceding
+local/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing any
+following global
+memory operations.</li>
+<li>Ensures that the
+preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before following
+global memory
+operations. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+local/generic store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+buffer_wbinvl1_vol.</li>
+<li>Ensures that the
+preceding
+global/local/generic
+load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before invalidating
+the cache. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+global/local/generic
+store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data. This
+satisfies the
+requirements of
+acquire.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="5"><strong>Sequential Consistent Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+load atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must
+happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent local
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+load atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0)
+and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>waitcnt lgkmcnt(0)
+must happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vmcnt(0)
+must happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent global
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>Same as corresponding
+fence acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The memory order also adds the single thread optimization constrains defined in
+table
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table"><span class="std std-ref">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX9</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table">
+<caption><span class="caption-text">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX9</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Memory</th>
+<th class="head">Optimization Constraints</th>
+</tr>
+<tr class="row-even"><th class="head">Ordering</th>
+<th class="head"> </th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-odd"><td>unordered</td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td>monotonic</td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>acquire</td>
+<td><ul class="first last simple">
+<li>If a load atomic/atomicrmw then no following load/load
+atomic/store/ store atomic/atomicrmw/fence instruction can
+be moved before the acquire.</li>
+<li>If a fence then same as load atomic, plus no preceding
+associated fence-paired-atomic can be moved after the fence.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>release</td>
+<td><ul class="first last simple">
+<li>If a store atomic/atomicrmw then no preceding load/load
+atomic/store/ store atomic/atomicrmw/fence instruction can
+be moved after the release.</li>
+<li>If a fence then same as store atomic, plus no following
+associated fence-paired-atomic can be moved before the
+fence.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>acq_rel</td>
+<td>Same constraints as both acquire and release.</td>
+</tr>
+<tr class="row-even"><td>seq_cst</td>
+<td><ul class="first last simple">
+<li>If a load atomic then same constraints as acquire, plus no
+preceding sequentially consistent load atomic/store
+atomic/atomicrmw/fence instruction can be moved after the
+seq_cst.</li>
+<li>If a store atomic then the same constraints as release, plus
+no following sequentially consistent load atomic/store
+atomic/atomicrmw/fence instruction can be moved before the
+seq_cst.</li>
+<li>If an atomicrmw/fence then same constraints as acq_rel.</li>
+</ul>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="trap-handler-abi">
+<h4><a class="toc-backref" href="#id71">Trap Handler ABI</a><a class="headerlink" href="#trap-handler-abi" title="Permalink to this headline">¶</a></h4>
+<p>For code objects generated by AMDGPU backend for HSA <a class="reference internal" href="#hsa" id="id29">[HSA]</a> compatible runtimes
+(such as ROCm <a class="reference internal" href="#amd-rocm" id="id30">[AMD-ROCm]</a>), the runtime installs a trap handler that supports
+the <code class="docutils literal"><span class="pre">s_trap</span></code> instruction with the following usage:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-amdhsa-os-table">
+<caption><span class="caption-text">AMDGPU Trap Handler for AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="21%" />
+<col width="21%" />
+<col width="32%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Usage</th>
+<th class="head">Code Sequence</th>
+<th class="head">Trap Handler
+Inputs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0x00</span></code></td>
+<td> </td>
+<td>Reserved by hardware.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">debugtrap(arg)</span></code></td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0x01</span></code></td>
+<td><dl class="first last docutils">
+<dt><code class="docutils literal"><span class="pre">SGPR0-1</span></code>:</dt>
+<dd><code class="docutils literal"><span class="pre">queue_ptr</span></code></dd>
+<dt><code class="docutils literal"><span class="pre">VGPR0</span></code>:</dt>
+<dd><code class="docutils literal"><span class="pre">arg</span></code></dd>
+</dl>
+</td>
+<td>Reserved for HSA
+<code class="docutils literal"><span class="pre">debugtrap</span></code>
+intrinsic (not
+implemented).</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal"><span class="pre">llvm.trap</span></code></td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0x02</span></code></td>
+<td><dl class="first last docutils">
+<dt><code class="docutils literal"><span class="pre">SGPR0-1</span></code>:</dt>
+<dd><code class="docutils literal"><span class="pre">queue_ptr</span></code></dd>
+</dl>
+</td>
+<td>Causes dispatch to be
+terminated and its
+associated queue put
+into the error state.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal"><span class="pre">llvm.debugtrap</span></code></td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0x03</span></code></td>
+<td><dl class="first last docutils">
+<dt><code class="docutils literal"><span class="pre">SGPR0-1</span></code>:</dt>
+<dd><code class="docutils literal"><span class="pre">queue_ptr</span></code></dd>
+</dl>
+</td>
+<td>If debugger not
+installed handled
+same as <code class="docutils literal"><span class="pre">llvm.trap</span></code>.</td>
+</tr>
+<tr class="row-even"><td>debugger breakpoint</td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0x07</span></code></td>
+<td> </td>
+<td>Reserved for  debugger
+breakpoints.</td>
+</tr>
+<tr class="row-odd"><td>debugger</td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0x08</span></code></td>
+<td> </td>
+<td>Reserved for debugger.</td>
+</tr>
+<tr class="row-even"><td>debugger</td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0xfe</span></code></td>
+<td> </td>
+<td>Reserved for debugger.</td>
+</tr>
+<tr class="row-odd"><td>debugger</td>
+<td><code class="docutils literal"><span class="pre">s_trap</span> <span class="pre">0xff</span></code></td>
+<td> </td>
+<td>Reserved for debugger.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="unspecified-os">
+<h3><a class="toc-backref" href="#id72">Unspecified OS</a><a class="headerlink" href="#unspecified-os" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+empty (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="id31">
+<h4><a class="toc-backref" href="#id73">Trap Handler ABI</a><a class="headerlink" href="#id31" title="Permalink to this headline">¶</a></h4>
+<p>For code objects generated by AMDGPU backend for non-amdhsa OS, the runtime does
+not install a trap handler. The <code class="docutils literal"><span class="pre">llvm.trap</span></code> and <code class="docutils literal"><span class="pre">llvm.debugtrap</span></code>
+instructions are handled as follows:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-non-amdhsa-os-table">
+<caption><span class="caption-text">AMDGPU Trap Handler for Non-AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-non-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="21%" />
+<col width="21%" />
+<col width="59%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Usage</th>
+<th class="head">Code Sequence</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>llvm.trap</td>
+<td>s_endpgm</td>
+<td>Causes wavefront to be terminated.</td>
+</tr>
+<tr class="row-odd"><td>llvm.debugtrap</td>
+<td><em>none</em></td>
+<td>Compiler warning given that there is no
+trap handler installed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+</div>
+<div class="section" id="source-languages">
+<h2><a class="toc-backref" href="#id74">Source Languages</a><a class="headerlink" href="#source-languages" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="opencl">
+<span id="amdgpu-opencl"></span><h3><a class="toc-backref" href="#id75">OpenCL</a><a class="headerlink" href="#opencl" title="Permalink to this headline">¶</a></h3>
+<p>When generating code for the OpenCL language the target triple environment
+should be <code class="docutils literal"><span class="pre">opencl</span></code> or <code class="docutils literal"><span class="pre">amdgizcl</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<p>When the language is OpenCL the following differences occur:</p>
+<ol class="arabic simple">
+<li>The OpenCL memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
+<li>The AMDGPU backend adds additional arguments to the kernel.</li>
+<li>Additional metadata is generated
+(<a class="reference internal" href="#amdgpu-amdhsa-hsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>).</li>
+</ol>
+</div>
+<div class="section" id="hcc">
+<span id="amdgpu-hcc"></span><h3><a class="toc-backref" href="#id76">HCC</a><a class="headerlink" href="#hcc" title="Permalink to this headline">¶</a></h3>
+<p>When generating code for the OpenCL language the target triple environment
+should be <code class="docutils literal"><span class="pre">hcc</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<p>When the language is OpenCL the following differences occur:</p>
+<ol class="arabic simple">
+<li>The HSA memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
+</ol>
+</div>
+<div class="section" id="assembler">
+<h3><a class="toc-backref" href="#id77">Assembler</a><a class="headerlink" href="#assembler" title="Permalink to this headline">¶</a></h3>
+<p>AMDGPU backend has LLVM-MC based assembler which is currently in development.
+It supports AMDGCN GFX6-GFX9.</p>
+<p>This section describes general syntax for instructions and operands. For more
+information about instructions, their semantics and supported combinations of
+operands, refer to one of instruction set architecture manuals
+<a class="reference internal" href="#amd-gcn-gfx6" id="id32">[AMD-GCN-GFX6]</a>, <a class="reference internal" href="#amd-gcn-gfx7" id="id33">[AMD-GCN-GFX7]</a>, <a class="reference internal" href="#amd-gcn-gfx8" id="id34">[AMD-GCN-GFX8]</a> and <a class="reference internal" href="#amd-gcn-gfx9" id="id35">[AMD-GCN-GFX9]</a>.</p>
+<p>An instruction has the following syntax (register operands are normally
+comma-separated while extra operands are space-separated):</p>
+<p><em><opcode> <register_operand0>, ... <extra_operand0> ...</em></p>
+<div class="section" id="operands">
+<h4><a class="toc-backref" href="#id78">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h4>
+<p>The following syntax for register operands is supported:</p>
+<ul class="simple">
+<li>SGPR registers: s0, ... or s[0], ...</li>
+<li>VGPR registers: v0, ... or v[0], ...</li>
+<li>TTMP registers: ttmp0, ... or ttmp[0], ...</li>
+<li>Special registers: exec (exec_lo, exec_hi), vcc (vcc_lo, vcc_hi), flat_scratch (flat_scratch_lo, flat_scratch_hi)</li>
+<li>Special trap registers: tba (tba_lo, tba_hi), tma (tma_lo, tma_hi)</li>
+<li>Register pairs, quads, etc: s[2:3], v[10:11], ttmp[5:6], s[4:7], v[12:15], ttmp[4:7], s[8:15], ...</li>
+<li>Register lists: [s0, s1], [ttmp0, ttmp1, ttmp2, ttmp3]</li>
+<li>Register index expressions: v[2*2], s[1-1:2-1]</li>
+<li>‘off’ indicates that an operand is not enabled</li>
+</ul>
+<p>The following extra operands are supported:</p>
+<ul class="simple">
+<li>offset, offset0, offset1</li>
+<li>idxen, offen bits</li>
+<li>glc, slc, tfe bits</li>
+<li>waitcnt: integer or combination of counter values</li>
+<li>VOP3 modifiers:<ul>
+<li>abs (| |), neg (-)</li>
+</ul>
+</li>
+<li>DPP modifiers:<ul>
+<li>row_shl, row_shr, row_ror, row_rol</li>
+<li>row_mirror, row_half_mirror, row_bcast</li>
+<li>wave_shl, wave_shr, wave_ror, wave_rol, quad_perm</li>
+<li>row_mask, bank_mask, bound_ctrl</li>
+</ul>
+</li>
+<li>SDWA modifiers:<ul>
+<li>dst_sel, src0_sel, src1_sel (BYTE_N, WORD_M, DWORD)</li>
+<li>dst_unused (UNUSED_PAD, UNUSED_SEXT, UNUSED_PRESERVE)</li>
+<li>abs, neg, sext</li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="instruction-examples">
+<h4><a class="toc-backref" href="#id79">Instruction Examples</a><a class="headerlink" href="#instruction-examples" title="Permalink to this headline">¶</a></h4>
+</div>
+<div class="section" id="ds">
+<h4><a class="toc-backref" href="#id80">DS</a><a class="headerlink" href="#ds" title="Permalink to this headline">¶</a></h4>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">ds_add_u32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">16</span>
+<span class="nf">ds_write_src2_b64</span> <span class="nv">v2</span> <span class="nv">offset0</span><span class="p">:</span><span class="mi">4</span> <span class="nv">offset1</span><span class="p">:</span><span class="mi">8</span>
+<span class="nf">ds_cmpst_f32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span><span class="p">,</span> <span class="nv">v6</span>
+<span class="nf">ds_min_rtn_f64</span> <span class="nv">v</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">9</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “LDS/GDS instructions” in ISA Manual.</p>
+<div class="section" id="flat">
+<h5><a class="toc-backref" href="#id81">FLAT</a><a class="headerlink" href="#flat" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">flat_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">]</span>
+<span class="nf">flat_store_dwordx3</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+<span class="nf">flat_atomic_swap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v5</span> <span class="nv">glc</span>
+<span class="nf">flat_atomic_cmpswap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span> <span class="nv">slc</span>
+<span class="nf">flat_atomic_fmax_x2</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “FLAT instructions” in ISA Manual.</p>
+</div>
+<div class="section" id="mubuf">
+<h5><a class="toc-backref" href="#id82">MUBUF</a><a class="headerlink" href="#mubuf" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">buffer_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
+<span class="nf">buffer_store_dwordx4</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">ttmp</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span> <span class="nv">offen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">glc</span> <span class="nv">tfe</span>
+<span class="nf">buffer_store_format_xy</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
+<span class="nf">buffer_wbinvl1</span>
+<span class="nf">buffer_atomic_inc</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">11</span><span class="p">],</span> <span class="nv">s4</span> <span class="nv">idxen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">slc</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “MUBUF Instructions” in ISA Manual.</p>
+</div>
+<div class="section" id="smrd-smem">
+<h5><a class="toc-backref" href="#id83">SMRD/SMEM</a><a class="headerlink" href="#smrd-smem" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">s_load_dword</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="mh">0xfc</span>
+<span class="nf">s_load_dwordx8</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">15</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_load_dwordx16</span> <span class="nv">s</span><span class="p">[</span><span class="mi">88</span><span class="p">:</span><span class="mi">103</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_dcache_inv_vol</span>
+<span class="nf">s_memtime</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “Scalar Memory Operations” in ISA Manual.</p>
+</div>
+<div class="section" id="sop1">
+<h5><a class="toc-backref" href="#id84">SOP1</a><a class="headerlink" href="#sop1" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">s_mov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_mov_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0x80000000</span>
+<span class="nf">s_cmov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="mi">200</span>
+<span class="nf">s_wqm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+<span class="nf">s_bcnt0_i32_b64</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="nf">s_swappc_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+<span class="nf">s_cbranch_join</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “SOP1 Instructions” in ISA Manual.</p>
+</div>
+<div class="section" id="sop2">
+<h5><a class="toc-backref" href="#id85">SOP2</a><a class="headerlink" href="#sop2" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">s_add_u32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
+<span class="nf">s_and_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+<span class="nf">s_cselect_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
+<span class="nf">s_andn2_b32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_lshr_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
+<span class="nf">s_ashr_i32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_bfm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_bfe_i64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
+<span class="nf">s_cbranch_g_fork</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “SOP2 Instructions” in ISA Manual.</p>
+</div>
+<div class="section" id="sopc">
+<h5><a class="toc-backref" href="#id86">SOPC</a><a class="headerlink" href="#sopc" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">s_cmp_eq_i32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_bitcmp1_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_bitcmp0_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_setvskip</span> <span class="nv">s3</span><span class="p">,</span> <span class="nv">s5</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “SOPC Instructions” in ISA Manual.</p>
+</div>
+<div class="section" id="sopp">
+<h5><a class="toc-backref" href="#id87">SOPP</a><a class="headerlink" href="#sopp" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">s_barrier</span>
+<span class="nf">s_nop</span> <span class="mi">2</span>
+<span class="nf">s_endpgm</span>
+<span class="nf">s_waitcnt</span> <span class="mi">0</span> <span class="c1">; Wait for all counters to be 0</span>
+<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">expcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">lgkmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="c1">; Equivalent to above</span>
+<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="c1">; Wait for vmcnt counter to be 1.</span>
+<span class="nf">s_sethalt</span> <span class="mi">9</span>
+<span class="nf">s_sleep</span> <span class="mi">10</span>
+<span class="nf">s_sendmsg</span> <span class="mh">0x1</span>
+<span class="nf">s_sendmsg</span> <span class="nv">sendmsg</span><span class="p">(</span><span class="nv">MSG_INTERRUPT</span><span class="p">)</span>
+<span class="nf">s_trap</span> <span class="mi">1</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “SOPP Instructions” in ISA Manual.</p>
+<p>Unless otherwise mentioned, little verification is performed on the operands
+of SOPP Instructions, so it is up to the programmer to be familiar with the
+range or acceptable values.</p>
+</div>
+<div class="section" id="valu">
+<h5><a class="toc-backref" href="#id88">VALU</a><a class="headerlink" href="#valu" title="Permalink to this headline">¶</a></h5>
+<p>For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
+the assembler will automatically use optimal encoding based on its operands.
+To force specific encoding, one can add a suffix to the opcode of the instruction:</p>
+<ul class="simple">
+<li>_e32 for 32-bit VOP1/VOP2/VOPC</li>
+<li>_e64 for 64-bit VOP3</li>
+<li>_dpp for VOP_DPP</li>
+<li>_sdwa for VOP_SDWA</li>
+</ul>
+<p>VOP1/VOP2/VOP3/VOPC examples:</p>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_mov_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_nop</span>
+<span class="nf">v_cvt_f64_i32_e32</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v2</span>
+<span class="nf">v_floor_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_bfrev_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_add_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_mul_i32_i24_e64</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="mi">3</span>
+<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">3</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">100</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_addc_u32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="nf">v_max_f16_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
+</pre></div>
+</div>
+<p>VOP_DPP examples:</p>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">2</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">wave_shl</span><span class="p">:</span><span class="mi">1</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_mirror</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_bcast</span><span class="p">:</span><span class="mi">31</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">3</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_add_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_max_f16</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+</pre></div>
+</div>
+<p>VOP_SDWA examples:</p>
+<div class="highlight-nasm"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PRESERVE</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">DWORD</span>
+<span class="nf">v_min_u32</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v1</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_1</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">DWORD</span>
+<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
+<span class="nf">v_fract_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">DWORD</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
+<span class="nf">v_cmpx_le_u32</span> <span class="nv">vcc</span><span class="p">,</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_2</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_0</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to “Vector ALU instructions”.</p>
+</div>
+</div>
+<div class="section" id="hsa-code-object-directives">
+<h4><a class="toc-backref" href="#id89">HSA Code Object Directives</a><a class="headerlink" href="#hsa-code-object-directives" title="Permalink to this headline">¶</a></h4>
+<p>AMDGPU ABI defines auxiliary data in output code object. In assembly source,
+one can specify them with assembler directives.</p>
+<div class="section" id="hsa-code-object-version-major-minor">
+<h5><a class="toc-backref" href="#id90">.hsa_code_object_version major, minor</a><a class="headerlink" href="#hsa-code-object-version-major-minor" title="Permalink to this headline">¶</a></h5>
+<p><em>major</em> and <em>minor</em> are integers that specify the version of the HSA code
+object that will be generated by the assembler.</p>
+</div>
+<div class="section" id="hsa-code-object-isa-major-minor-stepping-vendor-arch">
+<h5><a class="toc-backref" href="#id91">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a><a class="headerlink" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" title="Permalink to this headline">¶</a></h5>
+<p><em>major</em>, <em>minor</em>, and <em>stepping</em> are all integers that describe the instruction
+set architecture (ISA) version of the assembly program.</p>
+<p><em>vendor</em> and <em>arch</em> are quoted strings.  <em>vendor</em> should always be equal to
+“AMD” and <em>arch</em> should always be equal to “AMDGPU”.</p>
+<p>By default, the assembler will derive the ISA version, <em>vendor</em>, and <em>arch</em>
+from the value of the -mcpu option that is passed to the assembler.</p>
+</div>
+<div class="section" id="amdgpu-hsa-kernel-name">
+<h5><a class="toc-backref" href="#id92">.amdgpu_hsa_kernel (name)</a><a class="headerlink" href="#amdgpu-hsa-kernel-name" title="Permalink to this headline">¶</a></h5>
+<p>This directives specifies that the symbol with given name is a kernel entry point
+(label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.</p>
+</div>
+<div class="section" id="amd-kernel-code-t">
+<h5><a class="toc-backref" href="#id93">.amd_kernel_code_t</a><a class="headerlink" href="#amd-kernel-code-t" title="Permalink to this headline">¶</a></h5>
+<p>This directive marks the beginning of a list of key / value pairs that are used
+to specify the amd_kernel_code_t object that will be emitted by the assembler.
+The list must be terminated by the <em>.end_amd_kernel_code_t</em> directive.  For
+any amd_kernel_code_t values that are unspecified a default value will be
+used.  The default value for all keys is 0, with the following exceptions:</p>
+<ul class="simple">
+<li><em>kernel_code_version_major</em> defaults to 1.</li>
+<li><em>machine_kind</em> defaults to 1.</li>
+<li><em>machine_version_major</em>, <em>machine_version_minor</em>, and
+<em>machine_version_stepping</em> are derived from the value of the -mcpu option
+that is passed to the assembler.</li>
+<li><em>kernel_code_entry_byte_offset</em> defaults to 256.</li>
+<li><em>wavefront_size</em> defaults to 6.</li>
+<li><em>kernarg_segment_alignment</em>, <em>group_segment_alignment</em>, and
+<em>private_segment_alignment</em> default to 4. Note that alignments are specified
+as a power of two, so a value of <strong>n</strong> means an alignment of 2^ <strong>n</strong>.</li>
+</ul>
+<p>The <em>.amd_kernel_code_t</em> directive must be placed immediately after the
+function label and before any instructions.</p>
+<p>For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
+comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.</p>
+<p>Here is an example of a minimal amd_kernel_code_t specification:</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span>.hsa_code_object_version 1,0
+.hsa_code_object_isa
+
+.hsatext
+.globl  hello_world
+.p2align 8
+.amdgpu_hsa_kernel hello_world
+
+hello_world:
+
+   .amd_kernel_code_t
+      enable_sgpr_kernarg_segment_ptr = 1
+      is_ptr64 = 1
+      compute_pgm_rsrc1_vgprs = 0
+      compute_pgm_rsrc1_sgprs = 0
+      compute_pgm_rsrc2_user_sgpr = 2
+      kernarg_segment_byte_size = 8
+      wavefront_sgpr_count = 2
+      workitem_vgpr_count = 3
+  .end_amd_kernel_code_t
+
+  s_load_dwordx2 s[0:1], s[0:1] 0x0
+  v_mov_b32 v0, 3.14159
+  s_waitcnt lgkmcnt(0)
+  v_mov_b32 v1, s0
+  v_mov_b32 v2, s1
+  flat_store_dword v[1:2], v0
+  s_endpgm
+.Lfunc_end0:
+     .size   hello_world, .Lfunc_end0-hello_world
+</pre></div>
+</div>
+</div>
+</div>
+</div>
+</div>
+<div class="section" id="additional-documentation">
+<h2><a class="toc-backref" href="#id94">Additional Documentation</a><a class="headerlink" href="#additional-documentation" title="Permalink to this headline">¶</a></h2>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-2000-3000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id3">[AMD-RADEON-HD-2000-3000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf">AMD R6xx shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-4000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id4">[AMD-RADEON-HD-4000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf">AMD R7xx shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-5000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id5">[AMD-RADEON-HD-5000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf">AMD Evergreen shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-6000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id6">[AMD-RADEON-HD-6000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf">AMD Cayman/Trinity shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx6" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX6]</td><td><em>(<a class="fn-backref" href="#id7">1</a>, <a class="fn-backref" href="#id32">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf">AMD Southern Islands Series ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx7" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX7]</td><td><em>(<a class="fn-backref" href="#id8">1</a>, <a class="fn-backref" href="#id33">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf">AMD Sea Islands Series ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx8" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX8]</td><td><em>(<a class="fn-backref" href="#id9">1</a>, <a class="fn-backref" href="#id34">2</a>)</em> <a class="reference external" href="http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf">AMD GCN3 Instruction Set Architecture</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx9" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX9]</td><td><em>(<a class="fn-backref" href="#id10">1</a>, <a class="fn-backref" href="#id35">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/12/Vega_Shader_ISA_28July2017.pdf">AMD “Vega” Instruction Set Architecture</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-opencl-programming-guide" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-OpenCL_Programming-Guide]</td><td><a class="reference external" href="http://developer.amd.com/download/AMD_Accelerated_Parallel_Processing_OpenCL_Programming_Guide.pdf">AMD Accelerated Parallel Processing OpenCL Programming Guide</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-app-sdk" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-APP-SDK]</td><td><a class="reference external" href="http://developer.amd.com/tools/heterogeneous-computing/amd-accelerated-parallel-processing-app-sdk/documentation/">AMD Accelerated Parallel Processing APP SDK Documentation</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-rocm" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-ROCm]</td><td><em>(<a class="fn-backref" href="#id2">1</a>, <a class="fn-backref" href="#id17">2</a>, <a class="fn-backref" href="#id20">3</a>, <a class="fn-backref" href="#id30">4</a>)</em> <a class="reference external" href="http://gpuopen.com/compute-product/rocm/">ROCm: Open Platform for Development, Discovery and Education Around GPU Computing</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-rocm-github" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-ROCm-github]</td><td><em>(<a class="fn-backref" href="#id25">1</a>, <a class="fn-backref" href="#id26">2</a>)</em> <a class="reference external" href="http://github.com/RadeonOpenCompute">ROCm github</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="hsa" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[HSA]</td><td><em>(<a class="fn-backref" href="#id1">1</a>, <a class="fn-backref" href="#id11">2</a>, <a class="fn-backref" href="#id16">3</a>, <a class="fn-backref" href="#id19">4</a>, <a class="fn-backref" href="#id22">5</a>, <a class="fn-backref" href="#id23">6</a>, <a class="fn-backref" href="#id24">7</a>, <a class="fn-backref" href="#id27">8</a>, <a class="fn-backref" href="#id29">9</a>)</em> <a class="reference external" href="http://www.hsafoundation.com/">Heterogeneous System Architecture (HSA) Foundation</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="elf" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[ELF]</td><td><em>(<a class="fn-backref" href="#id14">1</a>, <a class="fn-backref" href="#id15">2</a>)</em> <a class="reference external" href="http://www.sco.com/developers/gabi/">Executable and Linkable Format (ELF)</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="id36" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id18">[DWARF]</a></td><td><a class="reference external" href="http://dwarfstd.org/">DWARF Debugging Information Format</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="yaml" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id21">[YAML]</a></td><td><a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html">YAML Ain’t Markup Language (YAML™) Version 1.2</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="id37" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[OpenCL]</td><td><em>(<a class="fn-backref" href="#id13">1</a>, <a class="fn-backref" href="#id28">2</a>)</em> <a class="reference external" href="http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf">The OpenCL Specification Version 2.0</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="hrf" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id12">[HRF]</a></td><td><a class="reference external" href="http://benedictgaster.org/wp-content/uploads/2014/01/asplos269-FINAL.pdf">Heterogeneous-race-free Memory Models</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-amdgpu-compute-application-binary-interface" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-AMDGPU-Compute-Application-Binary-Interface]</td><td><a class="reference external" href="https://github.com/RadeonOpenCompute/ROCm-ComputeABI-Doc/blob/master/AMDGPU-ABI.md">AMDGPU Compute Application Binary Interface</a></td></tr>
+</tbody>
+</table>
+</div>
+</div>
+
+
+          </div>
+      </div>
+      <div class="clearer"></div>
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+
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+            
+  <div class="section" id="advanced-build-configurations">
+<h1>Advanced Build Configurations<a class="headerlink" href="#advanced-build-configurations" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#bootstrap-builds" id="id2">Bootstrap Builds</a></li>
+<li><a class="reference internal" href="#apple-clang-builds-a-more-complex-bootstrap" id="id3">Apple Clang Builds (A More Complex Bootstrap)</a></li>
+<li><a class="reference internal" href="#multi-stage-pgo" id="id4">Multi-stage PGO</a></li>
+<li><a class="reference internal" href="#stage-non-determinism" id="id5">3-Stage Non-Determinism</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p><a class="reference external" href="http://www.cmake.org/">CMake</a> is a cross-platform build-generator tool. CMake
+does not build the project, it generates the files needed by your build tool
+(GNU make, Visual Studio, etc.) for building LLVM.</p>
+<p>If <strong>you are a new contributor</strong>, please start with the <a class="reference internal" href="GettingStarted.html"><span class="doc">Getting Started with the LLVM System</span></a> or
+<a class="reference internal" href="CMake.html"><span class="doc">Building LLVM with CMake</span></a> pages. This page is intended for users doing more complex builds.</p>
+<p>Many of the examples below are written assuming specific CMake Generators.
+Unless otherwise explicitly called out these commands should work with any CMake
+generator.</p>
+</div>
+<div class="section" id="bootstrap-builds">
+<h2><a class="toc-backref" href="#id2">Bootstrap Builds</a><a class="headerlink" href="#bootstrap-builds" title="Permalink to this headline">¶</a></h2>
+<p>The Clang CMake build system supports bootstrap (aka multi-stage) builds. At a
+high level a multi-stage build is a chain of builds that pass data from one
+stage into the next. The most common and simple version of this is a traditional
+bootstrap build.</p>
+<p>In a simple two-stage bootstrap build, we build clang using the system compiler,
+then use that just-built clang to build clang again. In CMake this simplest form
+of a bootstrap build can be configured with a single option,
+CLANG_ENABLE_BOOTSTRAP.</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -DCLANG_ENABLE_BOOTSTRAP<span class="o">=</span>On <path to source>
+<span class="gp">$</span> ninja stage2
+</pre></div>
+</div>
+<p>This command itself isn’t terribly useful because it assumes default
+configurations for each stage. The next series of examples utilize CMake cache
+scripts to provide more complex options.</p>
+<p>The clang build system refers to builds as stages. A stage1 build is a standard
+build using the compiler installed on the host, and a stage2 build is built
+using the stage1 compiler. This nomenclature holds up to more stages too. In
+general a stage*n* build is built using the output from stage*n-1*.</p>
+</div>
+<div class="section" id="apple-clang-builds-a-more-complex-bootstrap">
+<h2><a class="toc-backref" href="#id3">Apple Clang Builds (A More Complex Bootstrap)</a><a class="headerlink" href="#apple-clang-builds-a-more-complex-bootstrap" title="Permalink to this headline">¶</a></h2>
+<p>Apple’s Clang builds are a slightly more complicated example of the simple
+bootstrapping scenario. Apple Clang is built using a 2-stage build.</p>
+<p>The stage1 compiler is a host-only compiler with some options set. The stage1
+compiler is a balance of optimization vs build time because it is a throwaway.
+The stage2 compiler is the fully optimized compiler intended to ship to users.</p>
+<p>Setting up these compilers requires a lot of options. To simplify the
+configuration the Apple Clang build settings are contained in CMake Cache files.
+You can build an Apple Clang compiler using the following commands:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path to clang>/cmake/caches/Apple-stage1.cmake <path to source>
+<span class="gp">$</span> ninja stage2-distribution
+</pre></div>
+</div>
+<p>This CMake invocation configures the stage1 host compiler, and sets
+CLANG_BOOTSTRAP_CMAKE_ARGS to pass the Apple-stage2.cmake cache script to the
+stage2 configuration step.</p>
+<p>When you build the stage2-distribution target it builds the minimal stage1
+compiler and required tools, then configures and builds the stage2 compiler
+based on the settings in Apple-stage2.cmake.</p>
+<p>This pattern of using cache scripts to set complex settings, and specifically to
+make later stage builds include cache scripts is common in our more advanced
+build configurations.</p>
+</div>
+<div class="section" id="multi-stage-pgo">
+<h2><a class="toc-backref" href="#id4">Multi-stage PGO</a><a class="headerlink" href="#multi-stage-pgo" title="Permalink to this headline">¶</a></h2>
+<p>Profile-Guided Optimizations (PGO) is a really great way to optimize the code
+clang generates. Our multi-stage PGO builds are a workflow for generating PGO
+profiles that can be used to optimize clang.</p>
+<p>At a high level, the way PGO works is that you build an instrumented compiler,
+then you run the instrumented compiler against sample source files. While the
+instrumented compiler runs it will output a bunch of files containing
+performance counters (.profraw files). After generating all the profraw files
+you use llvm-profdata to merge the files into a single profdata file that you
+can feed into the LLVM_PROFDATA_FILE option.</p>
+<p>Our PGO.cmake cache script automates that whole process. You can use it by
+running:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path_to_clang>/cmake/caches/PGO.cmake <<span class="nb">source</span> dir>
+<span class="gp">$</span> ninja stage2-instrumented-generate-profdata
+</pre></div>
+</div>
+<p>If you let that run for a few hours or so, it will place a profdata file in your
+build directory. This takes a really long time because it builds clang twice,
+and you <em>must</em> have compiler-rt in your build tree.</p>
+<p>This process uses any source files under the perf-training directory as training
+data as long as the source files are marked up with LIT-style RUN lines.</p>
+<p>After it finishes you can use “find . -name clang.profdata” to find it, but it
+should be at a path something like:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="go"><build dir>/tools/clang/stage2-instrumented-bins/utils/perf-training/clang.profdata</span>
+</pre></div>
+</div>
+<p>You can feed that file into the LLVM_PROFDATA_FILE option when you build your
+optimized compiler.</p>
+<p>The PGO came cache has a slightly different stage naming scheme than other
+multi-stage builds. It generates three stages; stage1, stage2-instrumented, and
+stage2. Both of the stage2 builds are built using the stage1 compiler.</p>
+<p>The PGO came cache generates the following additional targets:</p>
+<dl class="docutils">
+<dt><strong>stage2-instrumented</strong></dt>
+<dd>Builds a stage1 x86 compiler, runtime, and required tools (llvm-config,
+llvm-profdata) then uses that compiler to build an instrumented stage2 compiler.</dd>
+<dt><strong>stage2-instrumented-generate-profdata</strong></dt>
+<dd>Depends on “stage2-instrumented” and will use the instrumented compiler to
+generate profdata based on the training files in <clang>/utils/perf-training</dd>
+<dt><strong>stage2</strong></dt>
+<dd>Depends of “stage2-instrumented-generate-profdata” and will use the stage1
+compiler with the stage2 profdata to build a PGO-optimized compiler.</dd>
+<dt><strong>stage2-check-llvm</strong></dt>
+<dd>Depends on stage2 and runs check-llvm using the stage2 compiler.</dd>
+<dt><strong>stage2-check-clang</strong></dt>
+<dd>Depends on stage2 and runs check-clang using the stage2 compiler.</dd>
+<dt><strong>stage2-check-all</strong></dt>
+<dd>Depends on stage2 and runs check-all using the stage2 compiler.</dd>
+<dt><strong>stage2-test-suite</strong></dt>
+<dd>Depends on stage2 and runs the test-suite using the stage3 compiler (requires
+in-tree test-suite).</dd>
+</dl>
+</div>
+<div class="section" id="stage-non-determinism">
+<h2><a class="toc-backref" href="#id5">3-Stage Non-Determinism</a><a class="headerlink" href="#stage-non-determinism" title="Permalink to this headline">¶</a></h2>
+<p>In the ancient lore of compilers non-determinism is like the multi-headed hydra.
+Whenever it’s head pops up, terror and chaos ensue.</p>
+<p>Historically one of the tests to verify that a compiler was deterministic would
+be a three stage build. The idea of a three stage build is you take your sources
+and build a compiler (stage1), then use that compiler to rebuild the sources
+(stage2), then you use that compiler to rebuild the sources a third time
+(stage3) with an identical configuration to the stage2 build. At the end of
+this, you have a stage2 and stage3 compiler that should be bit-for-bit
+identical.</p>
+<p>You can perform one of these 3-stage builds with LLVM & clang using the
+following commands:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path_to_clang>/cmake/caches/3-stage.cmake <<span class="nb">source</span> dir>
+<span class="gp">$</span> ninja stage3
+</pre></div>
+</div>
+<p>After the build you can compare the stage2 & stage3 compilers. We have a bot
+setup <a class="reference external" href="http://lab.llvm.org:8011/builders/clang-3stage-ubuntu">here</a> that runs
+this build and compare configuration.</p>
+</div>
+</div>
+
+
+          </div>
+      </div>
+      <div class="clearer"></div>
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+    <div class="related" role="navigation" aria-label="related navigation">
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+             >index</a></li>
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+            
+  <div class="section" id="llvm-alias-analysis-infrastructure">
+<h1>LLVM Alias Analysis Infrastructure<a class="headerlink" href="#llvm-alias-analysis-infrastructure" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#aliasanalysis-class-overview" id="id2"><code class="docutils literal"><span class="pre">AliasAnalysis</span></code> Class Overview</a><ul>
+<li><a class="reference internal" href="#representation-of-pointers" id="id3">Representation of Pointers</a></li>
+<li><a class="reference internal" href="#the-alias-method" id="id4">The <code class="docutils literal"><span class="pre">alias</span></code> method</a><ul>
+<li><a class="reference internal" href="#must-may-and-no-alias-responses" id="id5">Must, May, and No Alias Responses</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#the-getmodrefinfo-methods" id="id6">The <code class="docutils literal"><span class="pre">getModRefInfo</span></code> methods</a></li>
+<li><a class="reference internal" href="#other-useful-aliasanalysis-methods" id="id7">Other useful <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> methods</a><ul>
+<li><a class="reference internal" href="#the-pointstoconstantmemory-method" id="id8">The <code class="docutils literal"><span class="pre">pointsToConstantMemory</span></code> method</a></li>
+<li><a class="reference internal" href="#the-doesnotaccessmemory-and-onlyreadsmemory-methods" id="id9">The <code class="docutils literal"><span class="pre">doesNotAccessMemory</span></code> and  <code class="docutils literal"><span class="pre">onlyReadsMemory</span></code> methods</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#writing-a-new-aliasanalysis-implementation" id="id10">Writing a new <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> Implementation</a><ul>
+<li><a class="reference internal" href="#different-pass-styles" id="id11">Different Pass styles</a></li>
+<li><a class="reference internal" href="#required-initialization-calls" id="id12">Required initialization calls</a></li>
+<li><a class="reference internal" href="#required-methods-to-override" id="id13">Required methods to override</a></li>
+<li><a class="reference internal" href="#interfaces-which-may-be-specified" id="id14">Interfaces which may be specified</a></li>
+<li><a class="reference internal" href="#aliasanalysis-chaining-behavior" id="id15"><code class="docutils literal"><span class="pre">AliasAnalysis</span></code> chaining behavior</a></li>
+<li><a class="reference internal" href="#updating-analysis-results-for-transformations" id="id16">Updating analysis results for transformations</a><ul>
+<li><a class="reference internal" href="#the-deletevalue-method" id="id17">The <code class="docutils literal"><span class="pre">deleteValue</span></code> method</a></li>
+<li><a class="reference internal" href="#the-copyvalue-method" id="id18">The <code class="docutils literal"><span class="pre">copyValue</span></code> method</a></li>
+<li><a class="reference internal" href="#the-replacewithnewvalue-method" id="id19">The <code class="docutils literal"><span class="pre">replaceWithNewValue</span></code> method</a></li>
+<li><a class="reference internal" href="#the-addescapinguse-method" id="id20">The <code class="docutils literal"><span class="pre">addEscapingUse</span></code> method</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#efficiency-issues" id="id21">Efficiency Issues</a></li>
+<li><a class="reference internal" href="#limitations" id="id22">Limitations</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#using-alias-analysis-results" id="id23">Using alias analysis results</a><ul>
+<li><a class="reference internal" href="#using-the-memorydependenceanalysis-pass" id="id24">Using the <code class="docutils literal"><span class="pre">MemoryDependenceAnalysis</span></code> Pass</a></li>
+<li><a class="reference internal" href="#using-the-aliassettracker-class" id="id25">Using the <code class="docutils literal"><span class="pre">AliasSetTracker</span></code> class</a><ul>
+<li><a class="reference internal" href="#the-aliassettracker-implementation" id="id26">The AliasSetTracker implementation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#using-the-aliasanalysis-interface-directly" id="id27">Using the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface directly</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#existing-alias-analysis-implementations-and-clients" id="id28">Existing alias analysis implementations and clients</a><ul>
+<li><a class="reference internal" href="#available-aliasanalysis-implementations" id="id29">Available <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> implementations</a><ul>
+<li><a class="reference internal" href="#the-no-aa-pass" id="id30">The <code class="docutils literal"><span class="pre">-no-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-basicaa-pass" id="id31">The <code class="docutils literal"><span class="pre">-basicaa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-globalsmodref-aa-pass" id="id32">The <code class="docutils literal"><span class="pre">-globalsmodref-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-steens-aa-pass" id="id33">The <code class="docutils literal"><span class="pre">-steens-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-ds-aa-pass" id="id34">The <code class="docutils literal"><span class="pre">-ds-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-scev-aa-pass" id="id35">The <code class="docutils literal"><span class="pre">-scev-aa</span></code> pass</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#alias-analysis-driven-transformations" id="id36">Alias analysis driven transformations</a><ul>
+<li><a class="reference internal" href="#the-adce-pass" id="id37">The <code class="docutils literal"><span class="pre">-adce</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-licm-pass" id="id38">The <code class="docutils literal"><span class="pre">-licm</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-argpromotion-pass" id="id39">The <code class="docutils literal"><span class="pre">-argpromotion</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-gvn-memcpyopt-and-dse-passes" id="id40">The <code class="docutils literal"><span class="pre">-gvn</span></code>, <code class="docutils literal"><span class="pre">-memcpyopt</span></code>, and <code class="docutils literal"><span class="pre">-dse</span></code> passes</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#clients-for-debugging-and-evaluation-of-implementations" id="id41">Clients for debugging and evaluation of implementations</a><ul>
+<li><a class="reference internal" href="#the-print-alias-sets-pass" id="id42">The <code class="docutils literal"><span class="pre">-print-alias-sets</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-count-aa-pass" id="id43">The <code class="docutils literal"><span class="pre">-count-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-aa-eval-pass" id="id44">The <code class="docutils literal"><span class="pre">-aa-eval</span></code> pass</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#memory-dependence-analysis" id="id45">Memory Dependence Analysis</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Alias Analysis (aka Pointer Analysis) is a class of techniques which attempt to
+determine whether or not two pointers ever can point to the same object in
+memory.  There are many different algorithms for alias analysis and many
+different ways of classifying them: flow-sensitive vs. flow-insensitive,
+context-sensitive vs. context-insensitive, field-sensitive
+vs. field-insensitive, unification-based vs. subset-based, etc.  Traditionally,
+alias analyses respond to a query with a <a class="reference internal" href="#must-may-or-no">Must, May, or No</a> alias response,
+indicating that two pointers always point to the same object, might point to the
+same object, or are known to never point to the same object.</p>
+<p>The LLVM <a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a> class is the
+primary interface used by clients and implementations of alias analyses in the
+LLVM system.  This class is the common interface between clients of alias
+analysis information and the implementations providing it, and is designed to
+support a wide range of implementations and clients (but currently all clients
+are assumed to be flow-insensitive).  In addition to simple alias analysis
+information, this class exposes Mod/Ref information from those implementations
+which can provide it, allowing for powerful analyses and transformations to work
+well together.</p>
+<p>This document contains information necessary to successfully implement this
+interface, use it, and to test both sides.  It also explains some of the finer
+points about what exactly results mean.</p>
+</div>
+<div class="section" id="aliasanalysis-class-overview">
+<h2><a class="toc-backref" href="#id2"><code class="docutils literal"><span class="pre">AliasAnalysis</span></code> Class Overview</a><a class="headerlink" href="#aliasanalysis-class-overview" title="Permalink to this headline">¶</a></h2>
+<p>The <a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a>
+class defines the interface that the various alias analysis implementations
+should support.  This class exports two important enums: <code class="docutils literal"><span class="pre">AliasResult</span></code> and
+<code class="docutils literal"><span class="pre">ModRefResult</span></code> which represent the result of an alias query or a mod/ref
+query, respectively.</p>
+<p>The <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface exposes information about memory, represented in
+several different ways.  In particular, memory objects are represented as a
+starting address and size, and function calls are represented as the actual
+<code class="docutils literal"><span class="pre">call</span></code> or <code class="docutils literal"><span class="pre">invoke</span></code> instructions that performs the call.  The
+<code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface also exposes some helper methods which allow you to
+get mod/ref information for arbitrary instructions.</p>
+<p>All <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interfaces require that in queries involving multiple
+values, values which are not <a class="reference internal" href="LangRef.html#constants"><span class="std std-ref">constants</span></a> are all
+defined within the same function.</p>
+<div class="section" id="representation-of-pointers">
+<h3><a class="toc-backref" href="#id3">Representation of Pointers</a><a class="headerlink" href="#representation-of-pointers" title="Permalink to this headline">¶</a></h3>
+<p>Most importantly, the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> class provides several methods which are
+used to query whether or not two memory objects alias, whether function calls
+can modify or read a memory object, etc.  For all of these queries, memory
+objects are represented as a pair of their starting address (a symbolic LLVM
+<code class="docutils literal"><span class="pre">Value*</span></code>) and a static size.</p>
+<p>Representing memory objects as a starting address and a size is critically
+important for correct Alias Analyses.  For example, consider this (silly, but
+possible) C code:</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="kt">int</span> <span class="n">i</span><span class="p">;</span>
+<span class="kt">char</span> <span class="n">C</span><span class="p">[</span><span class="mi">2</span><span class="p">];</span>
+<span class="kt">char</span> <span class="n">A</span><span class="p">[</span><span class="mi">10</span><span class="p">];</span>
+<span class="cm">/* ... */</span>
+<span class="k">for</span> <span class="p">(</span><span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o">!=</span> <span class="mi">10</span><span class="p">;</span> <span class="o">++</span><span class="n">i</span><span class="p">)</span> <span class="p">{</span>
+  <span class="n">C</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="n">i</span><span class="p">];</span>          <span class="cm">/* One byte store */</span>
+  <span class="n">C</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="mi">9</span><span class="o">-</span><span class="n">i</span><span class="p">];</span>        <span class="cm">/* One byte store */</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>In this case, the <code class="docutils literal"><span class="pre">basicaa</span></code> pass will disambiguate the stores to <code class="docutils literal"><span class="pre">C[0]</span></code> and
+<code class="docutils literal"><span class="pre">C[1]</span></code> because they are accesses to two distinct locations one byte apart, and
+the accesses are each one byte.  In this case, the Loop Invariant Code Motion
+(LICM) pass can use store motion to remove the stores from the loop.  In
+constrast, the following code:</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="kt">int</span> <span class="n">i</span><span class="p">;</span>
+<span class="kt">char</span> <span class="n">C</span><span class="p">[</span><span class="mi">2</span><span class="p">];</span>
+<span class="kt">char</span> <span class="n">A</span><span class="p">[</span><span class="mi">10</span><span class="p">];</span>
+<span class="cm">/* ... */</span>
+<span class="k">for</span> <span class="p">(</span><span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o">!=</span> <span class="mi">10</span><span class="p">;</span> <span class="o">++</span><span class="n">i</span><span class="p">)</span> <span class="p">{</span>
+  <span class="p">((</span><span class="kt">short</span><span class="o">*</span><span class="p">)</span><span class="n">C</span><span class="p">)[</span><span class="mi">0</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="n">i</span><span class="p">];</span>  <span class="cm">/* Two byte store! */</span>
+  <span class="n">C</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="mi">9</span><span class="o">-</span><span class="n">i</span><span class="p">];</span>          <span class="cm">/* One byte store */</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>In this case, the two stores to C do alias each other, because the access to the
+<code class="docutils literal"><span class="pre">&C[0]</span></code> element is a two byte access.  If size information wasn’t available in
+the query, even the first case would have to conservatively assume that the
+accesses alias.</p>
+</div>
+<div class="section" id="the-alias-method">
+<span id="alias"></span><h3><a class="toc-backref" href="#id4">The <code class="docutils literal"><span class="pre">alias</span></code> method</a><a class="headerlink" href="#the-alias-method" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">alias</span></code> method is the primary interface used to determine whether or not
+two memory objects alias each other.  It takes two memory objects as input and
+returns MustAlias, PartialAlias, MayAlias, or NoAlias as appropriate.</p>
+<p>Like all <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interfaces, the <code class="docutils literal"><span class="pre">alias</span></code> method requires that either
+the two pointer values be defined within the same function, or at least one of
+the values is a <a class="reference internal" href="LangRef.html#constants"><span class="std std-ref">constant</span></a>.</p>
+<div class="section" id="must-may-and-no-alias-responses">
+<span id="must-may-or-no"></span><h4><a class="toc-backref" href="#id5">Must, May, and No Alias Responses</a><a class="headerlink" href="#must-may-and-no-alias-responses" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">NoAlias</span></code> response may be used when there is never an immediate dependence
+between any memory reference <em>based</em> on one pointer and any memory reference
+<em>based</em> the other. The most obvious example is when the two pointers point to
+non-overlapping memory ranges. Another is when the two pointers are only ever
+used for reading memory. Another is when the memory is freed and reallocated
+between accesses through one pointer and accesses through the other — in this
+case, there is a dependence, but it’s mediated by the free and reallocation.</p>
+<p>As an exception to this is with the <a class="reference internal" href="LangRef.html#noalias"><span class="std std-ref">noalias</span></a> keyword;
+the “irrelevant” dependencies are ignored.</p>
+<p>The <code class="docutils literal"><span class="pre">MayAlias</span></code> response is used whenever the two pointers might refer to the
+same object.</p>
+<p>The <code class="docutils literal"><span class="pre">PartialAlias</span></code> response is used when the two memory objects are known to
+be overlapping in some way, regardless whether they start at the same address
+or not.</p>
+<p>The <code class="docutils literal"><span class="pre">MustAlias</span></code> response may only be returned if the two memory objects are
+guaranteed to always start at exactly the same location. A <code class="docutils literal"><span class="pre">MustAlias</span></code>
+response does not imply that the pointers compare equal.</p>
+</div>
+</div>
+<div class="section" id="the-getmodrefinfo-methods">
+<h3><a class="toc-backref" href="#id6">The <code class="docutils literal"><span class="pre">getModRefInfo</span></code> methods</a><a class="headerlink" href="#the-getmodrefinfo-methods" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">getModRefInfo</span></code> methods return information about whether the execution of
+an instruction can read or modify a memory location.  Mod/Ref information is
+always conservative: if an instruction <strong>might</strong> read or write a location,
+<code class="docutils literal"><span class="pre">ModRef</span></code> is returned.</p>
+<p>The <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> class also provides a <code class="docutils literal"><span class="pre">getModRefInfo</span></code> method for testing
+dependencies between function calls.  This method takes two call sites (<code class="docutils literal"><span class="pre">CS1</span></code>
+& <code class="docutils literal"><span class="pre">CS2</span></code>), returns <code class="docutils literal"><span class="pre">NoModRef</span></code> if neither call writes to memory read or
+written by the other, <code class="docutils literal"><span class="pre">Ref</span></code> if <code class="docutils literal"><span class="pre">CS1</span></code> reads memory written by <code class="docutils literal"><span class="pre">CS2</span></code>,
+<code class="docutils literal"><span class="pre">Mod</span></code> if <code class="docutils literal"><span class="pre">CS1</span></code> writes to memory read or written by <code class="docutils literal"><span class="pre">CS2</span></code>, or <code class="docutils literal"><span class="pre">ModRef</span></code> if
+<code class="docutils literal"><span class="pre">CS1</span></code> might read or write memory written to by <code class="docutils literal"><span class="pre">CS2</span></code>.  Note that this
+relation is not commutative.</p>
+</div>
+<div class="section" id="other-useful-aliasanalysis-methods">
+<h3><a class="toc-backref" href="#id7">Other useful <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> methods</a><a class="headerlink" href="#other-useful-aliasanalysis-methods" title="Permalink to this headline">¶</a></h3>
+<p>Several other tidbits of information are often collected by various alias
+analysis implementations and can be put to good use by various clients.</p>
+<div class="section" id="the-pointstoconstantmemory-method">
+<h4><a class="toc-backref" href="#id8">The <code class="docutils literal"><span class="pre">pointsToConstantMemory</span></code> method</a><a class="headerlink" href="#the-pointstoconstantmemory-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">pointsToConstantMemory</span></code> method returns true if and only if the analysis
+can prove that the pointer only points to unchanging memory locations
+(functions, constant global variables, and the null pointer).  This information
+can be used to refine mod/ref information: it is impossible for an unchanging
+memory location to be modified.</p>
+</div>
+<div class="section" id="the-doesnotaccessmemory-and-onlyreadsmemory-methods">
+<span id="never-access-memory-or-only-read-memory"></span><h4><a class="toc-backref" href="#id9">The <code class="docutils literal"><span class="pre">doesNotAccessMemory</span></code> and  <code class="docutils literal"><span class="pre">onlyReadsMemory</span></code> methods</a><a class="headerlink" href="#the-doesnotaccessmemory-and-onlyreadsmemory-methods" title="Permalink to this headline">¶</a></h4>
+<p>These methods are used to provide very simple mod/ref information for function
+calls.  The <code class="docutils literal"><span class="pre">doesNotAccessMemory</span></code> method returns true for a function if the
+analysis can prove that the function never reads or writes to memory, or if the
+function only reads from constant memory.  Functions with this property are
+side-effect free and only depend on their input arguments, allowing them to be
+eliminated if they form common subexpressions or be hoisted out of loops.  Many
+common functions behave this way (e.g., <code class="docutils literal"><span class="pre">sin</span></code> and <code class="docutils literal"><span class="pre">cos</span></code>) but many others do
+not (e.g., <code class="docutils literal"><span class="pre">acos</span></code>, which modifies the <code class="docutils literal"><span class="pre">errno</span></code> variable).</p>
+<p>The <code class="docutils literal"><span class="pre">onlyReadsMemory</span></code> method returns true for a function if analysis can prove
+that (at most) the function only reads from non-volatile memory.  Functions with
+this property are side-effect free, only depending on their input arguments and
+the state of memory when they are called.  This property allows calls to these
+functions to be eliminated and moved around, as long as there is no store
+instruction that changes the contents of memory.  Note that all functions that
+satisfy the <code class="docutils literal"><span class="pre">doesNotAccessMemory</span></code> method also satisfy <code class="docutils literal"><span class="pre">onlyReadsMemory</span></code>.</p>
+</div>
+</div>
+</div>
+<div class="section" id="writing-a-new-aliasanalysis-implementation">
+<h2><a class="toc-backref" href="#id10">Writing a new <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> Implementation</a><a class="headerlink" href="#writing-a-new-aliasanalysis-implementation" title="Permalink to this headline">¶</a></h2>
+<p>Writing a new alias analysis implementation for LLVM is quite straight-forward.
+There are already several implementations that you can use for examples, and the
+following information should help fill in any details.  For a examples, take a
+look at the <a class="reference internal" href="#various-alias-analysis-implementations">various alias analysis implementations</a> included with LLVM.</p>
+<div class="section" id="different-pass-styles">
+<h3><a class="toc-backref" href="#id11">Different Pass styles</a><a class="headerlink" href="#different-pass-styles" title="Permalink to this headline">¶</a></h3>
+<p>The first step to determining what type of <a class="reference internal" href="WritingAnLLVMPass.html"><span class="doc">LLVM pass</span></a>
+you need to use for your Alias Analysis.  As is the case with most other
+analyses and transformations, the answer should be fairly obvious from what type
+of problem you are trying to solve:</p>
+<ol class="arabic simple">
+<li>If you require interprocedural analysis, it should be a <code class="docutils literal"><span class="pre">Pass</span></code>.</li>
+<li>If you are a function-local analysis, subclass <code class="docutils literal"><span class="pre">FunctionPass</span></code>.</li>
+<li>If you don’t need to look at the program at all, subclass <code class="docutils literal"><span class="pre">ImmutablePass</span></code>.</li>
+</ol>
+<p>In addition to the pass that you subclass, you should also inherit from the
+<code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface, of course, and use the <code class="docutils literal"><span class="pre">RegisterAnalysisGroup</span></code>
+template to register as an implementation of <code class="docutils literal"><span class="pre">AliasAnalysis</span></code>.</p>
+</div>
+<div class="section" id="required-initialization-calls">
+<h3><a class="toc-backref" href="#id12">Required initialization calls</a><a class="headerlink" href="#required-initialization-calls" title="Permalink to this headline">¶</a></h3>
+<p>Your subclass of <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> is required to invoke two methods on the
+<code class="docutils literal"><span class="pre">AliasAnalysis</span></code> base class: <code class="docutils literal"><span class="pre">getAnalysisUsage</span></code> and
+<code class="docutils literal"><span class="pre">InitializeAliasAnalysis</span></code>.  In particular, your implementation of
+<code class="docutils literal"><span class="pre">getAnalysisUsage</span></code> should explicitly call into the
+<code class="docutils literal"><span class="pre">AliasAnalysis::getAnalysisUsage</span></code> method in addition to doing any declaring
+any pass dependencies your pass has.  Thus you should have something like this:</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="kt">void</span> <span class="nf">getAnalysisUsage</span><span class="p">(</span><span class="n">AnalysisUsage</span> <span class="o">&</span><span class="n">AU</span><span class="p">)</span> <span class="k">const</span> <span class="p">{</span>
+  <span class="n">AliasAnalysis</span><span class="o">::</span><span class="n">getAnalysisUsage</span><span class="p">(</span><span class="n">AU</span><span class="p">);</span>
+  <span class="c1">// declare your dependencies here.</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>Additionally, your must invoke the <code class="docutils literal"><span class="pre">InitializeAliasAnalysis</span></code> method from your
+analysis run method (<code class="docutils literal"><span class="pre">run</span></code> for a <code class="docutils literal"><span class="pre">Pass</span></code>, <code class="docutils literal"><span class="pre">runOnFunction</span></code> for a
+<code class="docutils literal"><span class="pre">FunctionPass</span></code>, or <code class="docutils literal"><span class="pre">InitializePass</span></code> for an <code class="docutils literal"><span class="pre">ImmutablePass</span></code>).  For example
+(as part of a <code class="docutils literal"><span class="pre">Pass</span></code>):</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="kt">bool</span> <span class="nf">run</span><span class="p">(</span><span class="n">Module</span> <span class="o">&</span><span class="n">M</span><span class="p">)</span> <span class="p">{</span>
+  <span class="n">InitializeAliasAnalysis</span><span class="p">(</span><span class="k">this</span><span class="p">);</span>
+  <span class="c1">// Perform analysis here...</span>
+  <span class="k">return</span> <span class="nb">false</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="required-methods-to-override">
+<h3><a class="toc-backref" href="#id13">Required methods to override</a><a class="headerlink" href="#required-methods-to-override" title="Permalink to this headline">¶</a></h3>
+<p>You must override the <code class="docutils literal"><span class="pre">getAdjustedAnalysisPointer</span></code> method on all subclasses
+of <code class="docutils literal"><span class="pre">AliasAnalysis</span></code>. An example implementation of this method would look like:</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="kt">void</span> <span class="o">*</span><span class="nf">getAdjustedAnalysisPointer</span><span class="p">(</span><span class="k">const</span> <span class="kt">void</span><span class="o">*</span> <span class="n">ID</span><span class="p">)</span> <span class="k">override</span> <span class="p">{</span>
+  <span class="k">if</span> <span class="p">(</span><span class="n">ID</span> <span class="o">==</span> <span class="o">&</span><span class="n">AliasAnalysis</span><span class="o">::</span><span class="n">ID</span><span class="p">)</span>
+    <span class="k">return</span> <span class="p">(</span><span class="n">AliasAnalysis</span><span class="o">*</span><span class="p">)</span><span class="k">this</span><span class="p">;</span>
+  <span class="k">return</span> <span class="k">this</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="interfaces-which-may-be-specified">
+<h3><a class="toc-backref" href="#id14">Interfaces which may be specified</a><a class="headerlink" href="#interfaces-which-may-be-specified" title="Permalink to this headline">¶</a></h3>
+<p>All of the <a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a> virtual methods
+default to providing <a class="reference internal" href="#aliasanalysis-chaining"><span class="std std-ref">chaining</span></a> to another alias
+analysis implementation, which ends up returning conservatively correct
+information (returning “May” Alias and “Mod/Ref” for alias and mod/ref queries
+respectively).  Depending on the capabilities of the analysis you are
+implementing, you just override the interfaces you can improve.</p>
+</div>
+<div class="section" id="aliasanalysis-chaining-behavior">
+<span id="aliasanalysis-chaining"></span><h3><a class="toc-backref" href="#id15"><code class="docutils literal"><span class="pre">AliasAnalysis</span></code> chaining behavior</a><a class="headerlink" href="#aliasanalysis-chaining-behavior" title="Permalink to this headline">¶</a></h3>
+<p>With only one special exception (the <a class="reference internal" href="#aliasanalysis-no-aa"><span class="std std-ref">-no-aa</span></a> pass)
+every alias analysis pass chains to another alias analysis implementation (for
+example, the user can specify “<code class="docutils literal"><span class="pre">-basicaa</span> <span class="pre">-ds-aa</span> <span class="pre">-licm</span></code>” to get the maximum
+benefit from both alias analyses).  The alias analysis class automatically
+takes care of most of this for methods that you don’t override.  For methods
+that you do override, in code paths that return a conservative MayAlias or
+Mod/Ref result, simply return whatever the superclass computes.  For example:</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="n">AliasResult</span> <span class="nf">alias</span><span class="p">(</span><span class="k">const</span> <span class="n">Value</span> <span class="o">*</span><span class="n">V1</span><span class="p">,</span> <span class="kt">unsigned</span> <span class="n">V1Size</span><span class="p">,</span>
+                  <span class="k">const</span> <span class="n">Value</span> <span class="o">*</span><span class="n">V2</span><span class="p">,</span> <span class="kt">unsigned</span> <span class="n">V2Size</span><span class="p">)</span> <span class="p">{</span>
+  <span class="k">if</span> <span class="p">(...)</span>
+    <span class="k">return</span> <span class="n">NoAlias</span><span class="p">;</span>
+  <span class="p">...</span>
+
+  <span class="c1">// Couldn't determine a must or no-alias result.</span>
+  <span class="k">return</span> <span class="n">AliasAnalysis</span><span class="o">::</span><span class="n">alias</span><span class="p">(</span><span class="n">V1</span><span class="p">,</span> <span class="n">V1Size</span><span class="p">,</span> <span class="n">V2</span><span class="p">,</span> <span class="n">V2Size</span><span class="p">);</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>In addition to analysis queries, you must make sure to unconditionally pass LLVM
+<a class="reference internal" href="#update-notification">update notification</a> methods to the superclass as well if you override them,
+which allows all alias analyses in a change to be updated.</p>
+</div>
+<div class="section" id="updating-analysis-results-for-transformations">
+<span id="update-notification"></span><h3><a class="toc-backref" href="#id16">Updating analysis results for transformations</a><a class="headerlink" href="#updating-analysis-results-for-transformations" title="Permalink to this headline">¶</a></h3>
+<p>Alias analysis information is initially computed for a static snapshot of the
+program, but clients will use this information to make transformations to the
+code.  All but the most trivial forms of alias analysis will need to have their
+analysis results updated to reflect the changes made by these transformations.</p>
+<p>The <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface exposes four methods which are used to
+communicate program changes from the clients to the analysis implementations.
+Various alias analysis implementations should use these methods to ensure that
+their internal data structures are kept up-to-date as the program changes (for
+example, when an instruction is deleted), and clients of alias analysis must be
+sure to call these interfaces appropriately.</p>
+<div class="section" id="the-deletevalue-method">
+<h4><a class="toc-backref" href="#id17">The <code class="docutils literal"><span class="pre">deleteValue</span></code> method</a><a class="headerlink" href="#the-deletevalue-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">deleteValue</span></code> method is called by transformations when they remove an
+instruction or any other value from the program (including values that do not
+use pointers).  Typically alias analyses keep data structures that have entries
+for each value in the program.  When this method is called, they should remove
+any entries for the specified value, if they exist.</p>
+</div>
+<div class="section" id="the-copyvalue-method">
+<h4><a class="toc-backref" href="#id18">The <code class="docutils literal"><span class="pre">copyValue</span></code> method</a><a class="headerlink" href="#the-copyvalue-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">copyValue</span></code> method is used when a new value is introduced into the
+program.  There is no way to introduce a value into the program that did not
+exist before (this doesn’t make sense for a safe compiler transformation), so
+this is the only way to introduce a new value.  This method indicates that the
+new value has exactly the same properties as the value being copied.</p>
+</div>
+<div class="section" id="the-replacewithnewvalue-method">
+<h4><a class="toc-backref" href="#id19">The <code class="docutils literal"><span class="pre">replaceWithNewValue</span></code> method</a><a class="headerlink" href="#the-replacewithnewvalue-method" title="Permalink to this headline">¶</a></h4>
+<p>This method is a simple helper method that is provided to make clients easier to
+use.  It is implemented by copying the old analysis information to the new
+value, then deleting the old value.  This method cannot be overridden by alias
+analysis implementations.</p>
+</div>
+<div class="section" id="the-addescapinguse-method">
+<h4><a class="toc-backref" href="#id20">The <code class="docutils literal"><span class="pre">addEscapingUse</span></code> method</a><a class="headerlink" href="#the-addescapinguse-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">addEscapingUse</span></code> method is used when the uses of a pointer value have
+changed in ways that may invalidate precomputed analysis information.
+Implementations may either use this callback to provide conservative responses
+for points whose uses have change since analysis time, or may recompute some or
+all of their internal state to continue providing accurate responses.</p>
+<p>In general, any new use of a pointer value is considered an escaping use, and
+must be reported through this callback, <em>except</em> for the uses below:</p>
+<ul class="simple">
+<li>A <code class="docutils literal"><span class="pre">bitcast</span></code> or <code class="docutils literal"><span class="pre">getelementptr</span></code> of the pointer</li>
+<li>A <code class="docutils literal"><span class="pre">store</span></code> through the pointer (but not a <code class="docutils literal"><span class="pre">store</span></code> <em>of</em> the pointer)</li>
+<li>A <code class="docutils literal"><span class="pre">load</span></code> through the pointer</li>
+</ul>
+</div>
+</div>
+<div class="section" id="efficiency-issues">
+<h3><a class="toc-backref" href="#id21">Efficiency Issues</a><a class="headerlink" href="#efficiency-issues" title="Permalink to this headline">¶</a></h3>
+<p>From the LLVM perspective, the only thing you need to do to provide an efficient
+alias analysis is to make sure that alias analysis <strong>queries</strong> are serviced
+quickly.  The actual calculation of the alias analysis results (the “run”
+method) is only performed once, but many (perhaps duplicate) queries may be
+performed.  Because of this, try to move as much computation to the run method
+as possible (within reason).</p>
+</div>
+<div class="section" id="limitations">
+<h3><a class="toc-backref" href="#id22">Limitations</a><a class="headerlink" href="#limitations" title="Permalink to this headline">¶</a></h3>
+<p>The AliasAnalysis infrastructure has several limitations which make writing a
+new <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> implementation difficult.</p>
+<p>There is no way to override the default alias analysis. It would be very useful
+to be able to do something like “<code class="docutils literal"><span class="pre">opt</span> <span class="pre">-my-aa</span> <span class="pre">-O2</span></code>” and have it use <code class="docutils literal"><span class="pre">-my-aa</span></code>
+for all passes which need AliasAnalysis, but there is currently no support for
+that, short of changing the source code and recompiling. Similarly, there is
+also no way of setting a chain of analyses as the default.</p>
+<p>There is no way for transform passes to declare that they preserve
+<code class="docutils literal"><span class="pre">AliasAnalysis</span></code> implementations. The <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface includes
+<code class="docutils literal"><span class="pre">deleteValue</span></code> and <code class="docutils literal"><span class="pre">copyValue</span></code> methods which are intended to allow a pass to
+keep an AliasAnalysis consistent, however there’s no way for a pass to declare
+in its <code class="docutils literal"><span class="pre">getAnalysisUsage</span></code> that it does so. Some passes attempt to use
+<code class="docutils literal"><span class="pre">AU.addPreserved<AliasAnalysis></span></code>, however this doesn’t actually have any
+effect.</p>
+<p><code class="docutils literal"><span class="pre">AliasAnalysisCounter</span></code> (<code class="docutils literal"><span class="pre">-count-aa</span></code>) are implemented as <code class="docutils literal"><span class="pre">ModulePass</span></code>
+classes, so if your alias analysis uses <code class="docutils literal"><span class="pre">FunctionPass</span></code>, it won’t be able to
+use these utilities. If you try to use them, the pass manager will silently
+route alias analysis queries directly to <code class="docutils literal"><span class="pre">BasicAliasAnalysis</span></code> instead.</p>
+<p>Similarly, the <code class="docutils literal"><span class="pre">opt</span> <span class="pre">-p</span></code> option introduces <code class="docutils literal"><span class="pre">ModulePass</span></code> passes between each
+pass, which prevents the use of <code class="docutils literal"><span class="pre">FunctionPass</span></code> alias analysis passes.</p>
+<p>The <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> API does have functions for notifying implementations when
+values are deleted or copied, however these aren’t sufficient. There are many
+other ways that LLVM IR can be modified which could be relevant to
+<code class="docutils literal"><span class="pre">AliasAnalysis</span></code> implementations which can not be expressed.</p>
+<p>The <code class="docutils literal"><span class="pre">AliasAnalysisDebugger</span></code> utility seems to suggest that <code class="docutils literal"><span class="pre">AliasAnalysis</span></code>
+implementations can expect that they will be informed of any relevant <code class="docutils literal"><span class="pre">Value</span></code>
+before it appears in an alias query. However, popular clients such as <code class="docutils literal"><span class="pre">GVN</span></code>
+don’t support this, and are known to trigger errors when run with the
+<code class="docutils literal"><span class="pre">AliasAnalysisDebugger</span></code>.</p>
+<p>Due to several of the above limitations, the most obvious use for the
+<code class="docutils literal"><span class="pre">AliasAnalysisCounter</span></code> utility, collecting stats on all alias queries in a
+compilation, doesn’t work, even if the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> implementations don’t
+use <code class="docutils literal"><span class="pre">FunctionPass</span></code>.  There’s no way to set a default, much less a default
+sequence, and there’s no way to preserve it.</p>
+<p>The <code class="docutils literal"><span class="pre">AliasSetTracker</span></code> class (which is used by <code class="docutils literal"><span class="pre">LICM</span></code>) makes a
+non-deterministic number of alias queries. This can cause stats collected by
+<code class="docutils literal"><span class="pre">AliasAnalysisCounter</span></code> to have fluctuations among identical runs, for
+example. Another consequence is that debugging techniques involving pausing
+execution after a predetermined number of queries can be unreliable.</p>
+<p>Many alias queries can be reformulated in terms of other alias queries. When
+multiple <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> queries are chained together, it would make sense to
+start those queries from the beginning of the chain, with care taken to avoid
+infinite looping, however currently an implementation which wants to do this can
+only start such queries from itself.</p>
+</div>
+</div>
+<div class="section" id="using-alias-analysis-results">
+<h2><a class="toc-backref" href="#id23">Using alias analysis results</a><a class="headerlink" href="#using-alias-analysis-results" title="Permalink to this headline">¶</a></h2>
+<p>There are several different ways to use alias analysis results.  In order of
+preference, these are:</p>
+<div class="section" id="using-the-memorydependenceanalysis-pass">
+<h3><a class="toc-backref" href="#id24">Using the <code class="docutils literal"><span class="pre">MemoryDependenceAnalysis</span></code> Pass</a><a class="headerlink" href="#using-the-memorydependenceanalysis-pass" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">memdep</span></code> pass uses alias analysis to provide high-level dependence
+information about memory-using instructions.  This will tell you which store
+feeds into a load, for example.  It uses caching and other techniques to be
+efficient, and is used by Dead Store Elimination, GVN, and memcpy optimizations.</p>
+</div>
+<div class="section" id="using-the-aliassettracker-class">
+<span id="aliassettracker"></span><h3><a class="toc-backref" href="#id25">Using the <code class="docutils literal"><span class="pre">AliasSetTracker</span></code> class</a><a class="headerlink" href="#using-the-aliassettracker-class" title="Permalink to this headline">¶</a></h3>
+<p>Many transformations need information about alias <strong>sets</strong> that are active in
+some scope, rather than information about pairwise aliasing.  The
+<a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasSetTracker.html">AliasSetTracker</a>
+class is used to efficiently build these Alias Sets from the pairwise alias
+analysis information provided by the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface.</p>
+<p>First you initialize the AliasSetTracker by using the “<code class="docutils literal"><span class="pre">add</span></code>” methods to add
+information about various potentially aliasing instructions in the scope you are
+interested in.  Once all of the alias sets are completed, your pass should
+simply iterate through the constructed alias sets, using the <code class="docutils literal"><span class="pre">AliasSetTracker</span></code>
+<code class="docutils literal"><span class="pre">begin()</span></code>/<code class="docutils literal"><span class="pre">end()</span></code> methods.</p>
+<p>The <code class="docutils literal"><span class="pre">AliasSet</span></code>s formed by the <code class="docutils literal"><span class="pre">AliasSetTracker</span></code> are guaranteed to be
+disjoint, calculate mod/ref information and volatility for the set, and keep
+track of whether or not all of the pointers in the set are Must aliases.  The
+AliasSetTracker also makes sure that sets are properly folded due to call
+instructions, and can provide a list of pointers in each set.</p>
+<p>As an example user of this, the <a class="reference external" href="doxygen/structLICM.html">Loop Invariant Code Motion</a> pass uses <code class="docutils literal"><span class="pre">AliasSetTracker</span></code>s to calculate alias
+sets for each loop nest.  If an <code class="docutils literal"><span class="pre">AliasSet</span></code> in a loop is not modified, then all
+load instructions from that set may be hoisted out of the loop.  If any alias
+sets are stored to <strong>and</strong> are must alias sets, then the stores may be sunk
+to outside of the loop, promoting the memory location to a register for the
+duration of the loop nest.  Both of these transformations only apply if the
+pointer argument is loop-invariant.</p>
+<div class="section" id="the-aliassettracker-implementation">
+<h4><a class="toc-backref" href="#id26">The AliasSetTracker implementation</a><a class="headerlink" href="#the-aliassettracker-implementation" title="Permalink to this headline">¶</a></h4>
+<p>The AliasSetTracker class is implemented to be as efficient as possible.  It
+uses the union-find algorithm to efficiently merge AliasSets when a pointer is
+inserted into the AliasSetTracker that aliases multiple sets.  The primary data
+structure is a hash table mapping pointers to the AliasSet they are in.</p>
+<p>The AliasSetTracker class must maintain a list of all of the LLVM <code class="docutils literal"><span class="pre">Value*</span></code>s
+that are in each AliasSet.  Since the hash table already has entries for each
+LLVM <code class="docutils literal"><span class="pre">Value*</span></code> of interest, the AliasesSets thread the linked list through
+these hash-table nodes to avoid having to allocate memory unnecessarily, and to
+make merging alias sets extremely efficient (the linked list merge is constant
+time).</p>
+<p>You shouldn’t need to understand these details if you are just a client of the
+AliasSetTracker, but if you look at the code, hopefully this brief description
+will help make sense of why things are designed the way they are.</p>
+</div>
+</div>
+<div class="section" id="using-the-aliasanalysis-interface-directly">
+<h3><a class="toc-backref" href="#id27">Using the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface directly</a><a class="headerlink" href="#using-the-aliasanalysis-interface-directly" title="Permalink to this headline">¶</a></h3>
+<p>If neither of these utility class are what your pass needs, you should use the
+interfaces exposed by the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> class directly.  Try to use the
+higher-level methods when possible (e.g., use mod/ref information instead of the
+<a class="reference internal" href="#alias">alias</a> method directly if possible) to get the best precision and efficiency.</p>
+</div>
+</div>
+<div class="section" id="existing-alias-analysis-implementations-and-clients">
+<h2><a class="toc-backref" href="#id28">Existing alias analysis implementations and clients</a><a class="headerlink" href="#existing-alias-analysis-implementations-and-clients" title="Permalink to this headline">¶</a></h2>
+<p>If you’re going to be working with the LLVM alias analysis infrastructure, you
+should know what clients and implementations of alias analysis are available.
+In particular, if you are implementing an alias analysis, you should be aware of
+the <a class="reference internal" href="#the-clients">the clients</a> that are useful for monitoring and evaluating different
+implementations.</p>
+<div class="section" id="available-aliasanalysis-implementations">
+<span id="various-alias-analysis-implementations"></span><h3><a class="toc-backref" href="#id29">Available <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> implementations</a><a class="headerlink" href="#available-aliasanalysis-implementations" title="Permalink to this headline">¶</a></h3>
+<p>This section lists the various implementations of the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code>
+interface.  With the exception of the <a class="reference internal" href="#aliasanalysis-no-aa"><span class="std std-ref">-no-aa</span></a>
+implementation, all of these <a class="reference internal" href="#aliasanalysis-chaining"><span class="std std-ref">chain</span></a> to other
+alias analysis implementations.</p>
+<div class="section" id="the-no-aa-pass">
+<span id="aliasanalysis-no-aa"></span><h4><a class="toc-backref" href="#id30">The <code class="docutils literal"><span class="pre">-no-aa</span></code> pass</a><a class="headerlink" href="#the-no-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-no-aa</span></code> pass is just like what it sounds: an alias analysis that never
+returns any useful information.  This pass can be useful if you think that alias
+analysis is doing something wrong and are trying to narrow down a problem.</p>
+</div>
+<div class="section" id="the-basicaa-pass">
+<h4><a class="toc-backref" href="#id31">The <code class="docutils literal"><span class="pre">-basicaa</span></code> pass</a><a class="headerlink" href="#the-basicaa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-basicaa</span></code> pass is an aggressive local analysis that <em>knows</em> many
+important facts:</p>
+<ul class="simple">
+<li>Distinct globals, stack allocations, and heap allocations can never alias.</li>
+<li>Globals, stack allocations, and heap allocations never alias the null pointer.</li>
+<li>Different fields of a structure do not alias.</li>
+<li>Indexes into arrays with statically differing subscripts cannot alias.</li>
+<li>Many common standard C library functions <a class="reference internal" href="#never-access-memory-or-only-read-memory">never access memory or only read
+memory</a>.</li>
+<li>Pointers that obviously point to constant globals “<code class="docutils literal"><span class="pre">pointToConstantMemory</span></code>”.</li>
+<li>Function calls can not modify or references stack allocations if they never
+escape from the function that allocates them (a common case for automatic
+arrays).</li>
+</ul>
+</div>
+<div class="section" id="the-globalsmodref-aa-pass">
+<h4><a class="toc-backref" href="#id32">The <code class="docutils literal"><span class="pre">-globalsmodref-aa</span></code> pass</a><a class="headerlink" href="#the-globalsmodref-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>This pass implements a simple context-sensitive mod/ref and alias analysis for
+internal global variables that don’t “have their address taken”.  If a global
+does not have its address taken, the pass knows that no pointers alias the
+global.  This pass also keeps track of functions that it knows never access
+memory or never read memory.  This allows certain optimizations (e.g. GVN) to
+eliminate call instructions entirely.</p>
+<p>The real power of this pass is that it provides context-sensitive mod/ref
+information for call instructions.  This allows the optimizer to know that calls
+to a function do not clobber or read the value of the global, allowing loads and
+stores to be eliminated.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">This pass is somewhat limited in its scope (only support non-address taken
+globals), but is very quick analysis.</p>
+</div>
+</div>
+<div class="section" id="the-steens-aa-pass">
+<h4><a class="toc-backref" href="#id33">The <code class="docutils literal"><span class="pre">-steens-aa</span></code> pass</a><a class="headerlink" href="#the-steens-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-steens-aa</span></code> pass implements a variation on the well-known “Steensgaard’s
+algorithm” for interprocedural alias analysis.  Steensgaard’s algorithm is a
+unification-based, flow-insensitive, context-insensitive, and field-insensitive
+alias analysis that is also very scalable (effectively linear time).</p>
+<p>The LLVM <code class="docutils literal"><span class="pre">-steens-aa</span></code> pass implements a “speculatively field-<strong>sensitive</strong>”
+version of Steensgaard’s algorithm using the Data Structure Analysis framework.
+This gives it substantially more precision than the standard algorithm while
+maintaining excellent analysis scalability.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last"><code class="docutils literal"><span class="pre">-steens-aa</span></code> is available in the optional “poolalloc” module. It is not part
+of the LLVM core.</p>
+</div>
+</div>
+<div class="section" id="the-ds-aa-pass">
+<h4><a class="toc-backref" href="#id34">The <code class="docutils literal"><span class="pre">-ds-aa</span></code> pass</a><a class="headerlink" href="#the-ds-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-ds-aa</span></code> pass implements the full Data Structure Analysis algorithm.  Data
+Structure Analysis is a modular unification-based, flow-insensitive,
+context-<strong>sensitive</strong>, and speculatively field-<strong>sensitive</strong> alias
+analysis that is also quite scalable, usually at <code class="docutils literal"><span class="pre">O(n</span> <span class="pre">*</span> <span class="pre">log(n))</span></code>.</p>
+<p>This algorithm is capable of responding to a full variety of alias analysis
+queries, and can provide context-sensitive mod/ref information as well.  The
+only major facility not implemented so far is support for must-alias
+information.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last"><code class="docutils literal"><span class="pre">-ds-aa</span></code> is available in the optional “poolalloc” module. It is not part of
+the LLVM core.</p>
+</div>
+</div>
+<div class="section" id="the-scev-aa-pass">
+<h4><a class="toc-backref" href="#id35">The <code class="docutils literal"><span class="pre">-scev-aa</span></code> pass</a><a class="headerlink" href="#the-scev-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-scev-aa</span></code> pass implements AliasAnalysis queries by translating them into
+ScalarEvolution queries. This gives it a more complete understanding of
+<code class="docutils literal"><span class="pre">getelementptr</span></code> instructions and loop induction variables than other alias
+analyses have.</p>
+</div>
+</div>
+<div class="section" id="alias-analysis-driven-transformations">
+<h3><a class="toc-backref" href="#id36">Alias analysis driven transformations</a><a class="headerlink" href="#alias-analysis-driven-transformations" title="Permalink to this headline">¶</a></h3>
+<p>LLVM includes several alias-analysis driven transformations which can be used
+with any of the implementations above.</p>
+<div class="section" id="the-adce-pass">
+<h4><a class="toc-backref" href="#id37">The <code class="docutils literal"><span class="pre">-adce</span></code> pass</a><a class="headerlink" href="#the-adce-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-adce</span></code> pass, which implements Aggressive Dead Code Elimination uses the
+<code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface to delete calls to functions that do not have
+side-effects and are not used.</p>
+</div>
+<div class="section" id="the-licm-pass">
+<h4><a class="toc-backref" href="#id38">The <code class="docutils literal"><span class="pre">-licm</span></code> pass</a><a class="headerlink" href="#the-licm-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-licm</span></code> pass implements various Loop Invariant Code Motion related
+transformations.  It uses the <code class="docutils literal"><span class="pre">AliasAnalysis</span></code> interface for several different
+transformations:</p>
+<ul class="simple">
+<li>It uses mod/ref information to hoist or sink load instructions out of loops if
+there are no instructions in the loop that modifies the memory loaded.</li>
+<li>It uses mod/ref information to hoist function calls out of loops that do not
+write to memory and are loop-invariant.</li>
+<li>It uses alias information to promote memory objects that are loaded and stored
+to in loops to live in a register instead.  It can do this if there are no may
+aliases to the loaded/stored memory location.</li>
+</ul>
+</div>
+<div class="section" id="the-argpromotion-pass">
+<h4><a class="toc-backref" href="#id39">The <code class="docutils literal"><span class="pre">-argpromotion</span></code> pass</a><a class="headerlink" href="#the-argpromotion-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-argpromotion</span></code> pass promotes by-reference arguments to be passed in
+by-value instead.  In particular, if pointer arguments are only loaded from it
+passes in the value loaded instead of the address to the function.  This pass
+uses alias information to make sure that the value loaded from the argument
+pointer is not modified between the entry of the function and any load of the
+pointer.</p>
+</div>
+<div class="section" id="the-gvn-memcpyopt-and-dse-passes">
+<h4><a class="toc-backref" href="#id40">The <code class="docutils literal"><span class="pre">-gvn</span></code>, <code class="docutils literal"><span class="pre">-memcpyopt</span></code>, and <code class="docutils literal"><span class="pre">-dse</span></code> passes</a><a class="headerlink" href="#the-gvn-memcpyopt-and-dse-passes" title="Permalink to this headline">¶</a></h4>
+<p>These passes use AliasAnalysis information to reason about loads and stores.</p>
+</div>
+</div>
+<div class="section" id="clients-for-debugging-and-evaluation-of-implementations">
+<span id="the-clients"></span><h3><a class="toc-backref" href="#id41">Clients for debugging and evaluation of implementations</a><a class="headerlink" href="#clients-for-debugging-and-evaluation-of-implementations" title="Permalink to this headline">¶</a></h3>
+<p>These passes are useful for evaluating the various alias analysis
+implementations.  You can use them with commands like:</p>
+<div class="highlight-bash"><div class="highlight"><pre><span></span>% opt -ds-aa -aa-eval foo.bc -disable-output -stats
+</pre></div>
+</div>
+<div class="section" id="the-print-alias-sets-pass">
+<h4><a class="toc-backref" href="#id42">The <code class="docutils literal"><span class="pre">-print-alias-sets</span></code> pass</a><a class="headerlink" href="#the-print-alias-sets-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-print-alias-sets</span></code> pass is exposed as part of the <code class="docutils literal"><span class="pre">opt</span></code> tool to print
+out the Alias Sets formed by the <a class="reference internal" href="#aliassettracker">AliasSetTracker</a> class.  This is useful if
+you’re using the <code class="docutils literal"><span class="pre">AliasSetTracker</span></code> class.  To use it, use something like:</p>
+<div class="highlight-bash"><div class="highlight"><pre><span></span>% opt -ds-aa -print-alias-sets -disable-output
+</pre></div>
+</div>
+</div>
+<div class="section" id="the-count-aa-pass">
+<h4><a class="toc-backref" href="#id43">The <code class="docutils literal"><span class="pre">-count-aa</span></code> pass</a><a class="headerlink" href="#the-count-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-count-aa</span></code> pass is useful to see how many queries a particular pass is
+making and what responses are returned by the alias analysis.  As an example:</p>
+<div class="highlight-bash"><div class="highlight"><pre><span></span>% opt -basicaa -count-aa -ds-aa -count-aa -licm
+</pre></div>
+</div>
+<p>will print out how many queries (and what responses are returned) by the
+<code class="docutils literal"><span class="pre">-licm</span></code> pass (of the <code class="docutils literal"><span class="pre">-ds-aa</span></code> pass) and how many queries are made of the
+<code class="docutils literal"><span class="pre">-basicaa</span></code> pass by the <code class="docutils literal"><span class="pre">-ds-aa</span></code> pass.  This can be useful when debugging a
+transformation or an alias analysis implementation.</p>
+</div>
+<div class="section" id="the-aa-eval-pass">
+<h4><a class="toc-backref" href="#id44">The <code class="docutils literal"><span class="pre">-aa-eval</span></code> pass</a><a class="headerlink" href="#the-aa-eval-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">-aa-eval</span></code> pass simply iterates through all pairs of pointers in a
+function and asks an alias analysis whether or not the pointers alias.  This
+gives an indication of the precision of the alias analysis.  Statistics are
+printed indicating the percent of no/may/must aliases found (a more precise
+algorithm will have a lower number of may aliases).</p>
+</div>
+</div>
+</div>
+<div class="section" id="memory-dependence-analysis">
+<h2><a class="toc-backref" href="#id45">Memory Dependence Analysis</a><a class="headerlink" href="#memory-dependence-analysis" title="Permalink to this headline">¶</a></h2>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">We are currently in the process of migrating things from
+<code class="docutils literal"><span class="pre">MemoryDependenceAnalysis</span></code> to <a class="reference internal" href="MemorySSA.html"><span class="doc">MemorySSA</span></a>. Please try to use
+that instead.</p>
+</div>
+<p>If you’re just looking to be a client of alias analysis information, consider
+using the Memory Dependence Analysis interface instead.  MemDep is a lazy,
+caching layer on top of alias analysis that is able to answer the question of
+what preceding memory operations a given instruction depends on, either at an
+intra- or inter-block level.  Because of its laziness and caching policy, using
+MemDep can be a significant performance win over accessing alias analysis
+directly.</p>
+</div>
+</div>
+
+
+          </div>
+      </div>
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+  <div class="section" id="llvm-atomic-instructions-and-concurrency-guide">
+<h1>LLVM Atomic Instructions and Concurrency Guide<a class="headerlink" href="#llvm-atomic-instructions-and-concurrency-guide" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id4">Introduction</a></li>
+<li><a class="reference internal" href="#optimization-outside-atomic" id="id5">Optimization outside atomic</a></li>
+<li><a class="reference internal" href="#atomic-instructions" id="id6">Atomic instructions</a></li>
+<li><a class="reference internal" href="#atomic-orderings" id="id7">Atomic orderings</a><ul>
+<li><a class="reference internal" href="#notatomic" id="id8">NotAtomic</a></li>
+<li><a class="reference internal" href="#unordered" id="id9">Unordered</a></li>
+<li><a class="reference internal" href="#monotonic" id="id10">Monotonic</a></li>
+<li><a class="reference internal" href="#acquire" id="id11">Acquire</a></li>
+<li><a class="reference internal" href="#release" id="id12">Release</a></li>
+<li><a class="reference internal" href="#acquirerelease" id="id13">AcquireRelease</a></li>
+<li><a class="reference internal" href="#sequentiallyconsistent" id="id14">SequentiallyConsistent</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#atomics-and-ir-optimization" id="id15">Atomics and IR optimization</a></li>
+<li><a class="reference internal" href="#atomics-and-codegen" id="id16">Atomics and Codegen</a></li>
+<li><a class="reference internal" href="#libcalls-atomic" id="id17">Libcalls: __atomic_*</a></li>
+<li><a class="reference internal" href="#libcalls-sync" id="id18">Libcalls: __sync_*</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id4">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>LLVM supports instructions which are well-defined in the presence of threads and
+asynchronous signals.</p>
+<p>The atomic instructions are designed specifically to provide readable IR and
+optimized code generation for the following:</p>
+<ul class="simple">
+<li>The C++11 <code class="docutils literal"><span class="pre"><atomic></span></code> header.  (<a class="reference external" href="http://www.open-std.org/jtc1/sc22/wg21/">C++11 draft available here</a>.) (<a class="reference external" href="http://www.open-std.org/jtc1/sc22/wg14/">C11 draft available here</a>.)</li>
+<li>Proper semantics for Java-style memory, for both <code class="docutils literal"><span class="pre">volatile</span></code> and regular
+shared variables. (<a class="reference external" href="http://docs.oracle.com/javase/specs/jls/se8/html/jls-17.html">Java Specification</a>)</li>
+<li>gcc-compatible <code class="docutils literal"><span class="pre">__sync_*</span></code> builtins. (<a class="reference external" href="https://gcc.gnu.org/onlinedocs/gcc/_005f_005fsync-Builtins.html">Description</a>)</li>
+<li>Other scenarios with atomic semantics, including <code class="docutils literal"><span class="pre">static</span></code> variables with
+non-trivial constructors in C++.</li>
+</ul>
+<p>Atomic and volatile in the IR are orthogonal; “volatile” is the C/C++ volatile,
+which ensures that every volatile load and store happens and is performed in the
+stated order.  A couple examples: if a SequentiallyConsistent store is
+immediately followed by another SequentiallyConsistent store to the same
+address, the first store can be erased. This transformation is not allowed for a
+pair of volatile stores. On the other hand, a non-volatile non-atomic load can
+be moved across a volatile load freely, but not an Acquire load.</p>
+<p>This document is intended to provide a guide to anyone either writing a frontend
+for LLVM or working on optimization passes for LLVM with a guide for how to deal
+with instructions with special semantics in the presence of concurrency.  This
+is not intended to be a precise guide to the semantics; the details can get
+extremely complicated and unreadable, and are not usually necessary.</p>
+</div>
+<div class="section" id="optimization-outside-atomic">
+<span id="id1"></span><h2><a class="toc-backref" href="#id5">Optimization outside atomic</a><a class="headerlink" href="#optimization-outside-atomic" title="Permalink to this headline">¶</a></h2>
+<p>The basic <code class="docutils literal"><span class="pre">'load'</span></code> and <code class="docutils literal"><span class="pre">'store'</span></code> allow a variety of optimizations, but can
+lead to undefined results in a concurrent environment; see <a class="reference internal" href="#notatomic">NotAtomic</a>. This
+section specifically goes into the one optimizer restriction which applies in
+concurrent environments, which gets a bit more of an extended description
+because any optimization dealing with stores needs to be aware of it.</p>
+<p>From the optimizer’s point of view, the rule is that if there are not any
+instructions with atomic ordering involved, concurrency does not matter, with
+one exception: if a variable might be visible to another thread or signal
+handler, a store cannot be inserted along a path where it might not execute
+otherwise.  Take the following example:</p>
+<div class="highlight-c"><div class="highlight"><pre><span></span><span class="cm">/* C code, for readability; run through clang -O2 -S -emit-llvm to get</span>
+<span class="cm">    equivalent IR */</span>
+ <span class="kt">int</span> <span class="n">x</span><span class="p">;</span>
+ <span class="kt">void</span> <span class="nf">f</span><span class="p">(</span><span class="kt">int</span><span class="o">*</span> <span class="n">a</span><span class="p">)</span> <span class="p">{</span>
+   <span class="k">for</span> <span class="p">(</span><span class="kt">int</span> <span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o"><</span> <span class="mi">100</span><span class="p">;</span> <span class="n">i</span><span class="o">++</span><span class="p">)</span> <span class="p">{</span>
+     <span class="k">if</span> <span class="p">(</span><span class="n">a</span><span class="p">[</span><span class="n">i</span><span class="p">])</span>
+       <span class="n">x</span> <span class="o">+=</span> <span class="mi">1</span><span class="p">;</span>
+   <span class="p">}</span>
+ <span class="p">}</span>
+</pre></div>
+</div>
+<p>The following is equivalent in non-concurrent situations:</p>
+<div class="highlight-c"><div class="highlight"><pre><span></span><span class="kt">int</span> <span class="n">x</span><span class="p">;</span>
+<span class="kt">void</span> <span class="nf">f</span><span class="p">(</span><span class="kt">int</span><span class="o">*</span> <span class="n">a</span><span class="p">)</span> <span class="p">{</span>
+  <span class="kt">int</span> <span class="n">xtemp</span> <span class="o">=</span> <span class="n">x</span><span class="p">;</span>
+  <span class="k">for</span> <span class="p">(</span><span class="kt">int</span> <span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o"><</span> <span class="mi">100</span><span class="p">;</span> <span class="n">i</span><span class="o">++</span><span class="p">)</span> <span class="p">{</span>
+    <span class="k">if</span> <span class="p">(</span><span class="n">a</span><span class="p">[</span><span class="n">i</span><span class="p">])</span>
+      <span class="n">xtemp</span> <span class="o">+=</span> <span class="mi">1</span><span class="p">;</span>
+  <span class="p">}</span>
+  <span class="n">x</span> <span class="o">=</span> <span class="n">xtemp</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>However, LLVM is not allowed to transform the former to the latter: it could
+indirectly introduce undefined behavior if another thread can access <code class="docutils literal"><span class="pre">x</span></code> at
+the same time. (This example is particularly of interest because before the
+concurrency model was implemented, LLVM would perform this transformation.)</p>
+<p>Note that speculative loads are allowed; a load which is part of a race returns
+<code class="docutils literal"><span class="pre">undef</span></code>, but does not have undefined behavior.</p>
+</div>
+<div class="section" id="atomic-instructions">
+<h2><a class="toc-backref" href="#id6">Atomic instructions</a><a class="headerlink" href="#atomic-instructions" title="Permalink to this headline">¶</a></h2>
+<p>For cases where simple loads and stores are not sufficient, LLVM provides
+various atomic instructions. The exact guarantees provided depend on the
+ordering; see <a class="reference internal" href="#atomic-orderings">Atomic orderings</a>.</p>
+<p><code class="docutils literal"><span class="pre">load</span> <span class="pre">atomic</span></code> and <code class="docutils literal"><span class="pre">store</span> <span class="pre">atomic</span></code> provide the same basic functionality as
+non-atomic loads and stores, but provide additional guarantees in situations
+where threads and signals are involved.</p>
+<p><code class="docutils literal"><span class="pre">cmpxchg</span></code> and <code class="docutils literal"><span class="pre">atomicrmw</span></code> are essentially like an atomic load followed by an
+atomic store (where the store is conditional for <code class="docutils literal"><span class="pre">cmpxchg</span></code>), but no other
+memory operation can happen on any thread between the load and store.</p>
+<p>A <code class="docutils literal"><span class="pre">fence</span></code> provides Acquire and/or Release ordering which is not part of
+another operation; it is normally used along with Monotonic memory operations.
+A Monotonic load followed by an Acquire fence is roughly equivalent to an
+Acquire load, and a Monotonic store following a Release fence is roughly
+equivalent to a Release store. SequentiallyConsistent fences behave as both
+an Acquire and a Release fence, and offer some additional complicated
+guarantees, see the C++11 standard for details.</p>
+<p>Frontends generating atomic instructions generally need to be aware of the
+target to some degree; atomic instructions are guaranteed to be lock-free, and
+therefore an instruction which is wider than the target natively supports can be
+impossible to generate.</p>
+</div>
+<div class="section" id="atomic-orderings">
+<span id="id2"></span><h2><a class="toc-backref" href="#id7">Atomic orderings</a><a class="headerlink" href="#atomic-orderings" title="Permalink to this headline">¶</a></h2>
+<p>In order to achieve a balance between performance and necessary guarantees,
+there are six levels of atomicity. They are listed in order of strength; each
+level includes all the guarantees of the previous level except for
+Acquire/Release. (See also <a class="reference external" href="LangRef.html#ordering">LangRef Ordering</a>.)</p>
+<div class="section" id="notatomic">
+<span id="id3"></span><h3><a class="toc-backref" href="#id8">NotAtomic</a><a class="headerlink" href="#notatomic" title="Permalink to this headline">¶</a></h3>
+<p>NotAtomic is the obvious, a load or store which is not atomic. (This isn’t
+really a level of atomicity, but is listed here for comparison.) This is
+essentially a regular load or store. If there is a race on a given memory
+location, loads from that location return undef.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This is intended to match shared variables in C/C++, and to be used in any
+other context where memory access is necessary, and a race is impossible. (The
+precise definition is in <a class="reference external" href="LangRef.html#memmodel">LangRef Memory Model</a>.)</dd>
+<dt>Notes for frontends</dt>
+<dd>The rule is essentially that all memory accessed with basic loads and stores
+by multiple threads should be protected by a lock or other synchronization;
+otherwise, you are likely to run into undefined behavior. If your frontend is
+for a “safe” language like Java, use Unordered to load and store any shared
+variable.  Note that NotAtomic volatile loads and stores are not properly
+atomic; do not try to use them as a substitute. (Per the C/C++ standards,
+volatile does provide some limited guarantees around asynchronous signals, but
+atomics are generally a better solution.)</dd>
+<dt>Notes for optimizers</dt>
+<dd>Introducing loads to shared variables along a codepath where they would not
+otherwise exist is allowed; introducing stores to shared variables is not. See
+<a class="reference internal" href="#optimization-outside-atomic">Optimization outside atomic</a>.</dd>
+<dt>Notes for code generation</dt>
+<dd>The one interesting restriction here is that it is not allowed to write to
+bytes outside of the bytes relevant to a store.  This is mostly relevant to
+unaligned stores: it is not allowed in general to convert an unaligned store
+into two aligned stores of the same width as the unaligned store. Backends are
+also expected to generate an i8 store as an i8 store, and not an instruction
+which writes to surrounding bytes.  (If you are writing a backend for an
+architecture which cannot satisfy these restrictions and cares about
+concurrency, please send an email to llvm-dev.)</dd>
+</dl>
+</div>
+<div class="section" id="unordered">
+<h3><a class="toc-backref" href="#id9">Unordered</a><a class="headerlink" href="#unordered" title="Permalink to this headline">¶</a></h3>
+<p>Unordered is the lowest level of atomicity. It essentially guarantees that races
+produce somewhat sane results instead of having undefined behavior.  It also
+guarantees the operation to be lock-free, so it does not depend on the data
+being part of a special atomic structure or depend on a separate per-process
+global lock.  Note that code generation will fail for unsupported atomic
+operations; if you need such an operation, use explicit locking.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This is intended to match the Java memory model for shared variables.</dd>
+<dt>Notes for frontends</dt>
+<dd>This cannot be used for synchronization, but is useful for Java and other
+“safe” languages which need to guarantee that the generated code never
+exhibits undefined behavior. Note that this guarantee is cheap on common
+platforms for loads of a native width, but can be expensive or unavailable for
+wider loads, like a 64-bit store on ARM. (A frontend for Java or other “safe”
+languages would normally split a 64-bit store on ARM into two 32-bit unordered
+stores.)</dd>
+<dt>Notes for optimizers</dt>
+<dd>In terms of the optimizer, this prohibits any transformation that transforms a
+single load into multiple loads, transforms a store into multiple stores,
+narrows a store, or stores a value which would not be stored otherwise.  Some
+examples of unsafe optimizations are narrowing an assignment into a bitfield,
+rematerializing a load, and turning loads and stores into a memcpy
+call. Reordering unordered operations is safe, though, and optimizers should
+take advantage of that because unordered operations are common in languages
+that need them.</dd>
+<dt>Notes for code generation</dt>
+<dd>These operations are required to be atomic in the sense that if you use
+unordered loads and unordered stores, a load cannot see a value which was
+never stored.  A normal load or store instruction is usually sufficient, but
+note that an unordered load or store cannot be split into multiple
+instructions (or an instruction which does multiple memory operations, like
+<code class="docutils literal"><span class="pre">LDRD</span></code> on ARM without LPAE, or not naturally-aligned <code class="docutils literal"><span class="pre">LDRD</span></code> on LPAE ARM).</dd>
+</dl>
+</div>
+<div class="section" id="monotonic">
+<h3><a class="toc-backref" href="#id10">Monotonic</a><a class="headerlink" href="#monotonic" title="Permalink to this headline">¶</a></h3>
+<p>Monotonic is the weakest level of atomicity that can be used in synchronization
+primitives, although it does not provide any general synchronization. It
+essentially guarantees that if you take all the operations affecting a specific
+address, a consistent ordering exists.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal"><span class="pre">memory_order_relaxed</span></code>; see those
+standards for the exact definition.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution.  The
+guarantees in terms of synchronization are very weak, so make sure these are
+only used in a pattern which you know is correct.  Generally, these would
+either be used for atomic operations which do not protect other memory (like
+an atomic counter), or along with a <code class="docutils literal"><span class="pre">fence</span></code>.</dd>
+<dt>Notes for optimizers</dt>
+<dd>In terms of the optimizer, this can be treated as a read+write on the relevant
+memory location (and alias analysis will take advantage of that). In addition,
+it is legal to reorder non-atomic and Unordered loads around Monotonic
+loads. CSE/DSE and a few other optimizations are allowed, but Monotonic
+operations are unlikely to be used in ways which would make those
+optimizations useful.</dd>
+<dt>Notes for code generation</dt>
+<dd>Code generation is essentially the same as that for unordered for loads and
+stores.  No fences are required.  <code class="docutils literal"><span class="pre">cmpxchg</span></code> and <code class="docutils literal"><span class="pre">atomicrmw</span></code> are required
+to appear as a single operation.</dd>
+</dl>
+</div>
+<div class="section" id="acquire">
+<h3><a class="toc-backref" href="#id11">Acquire</a><a class="headerlink" href="#acquire" title="Permalink to this headline">¶</a></h3>
+<p>Acquire provides a barrier of the sort necessary to acquire a lock to access
+other memory with normal loads and stores.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal"><span class="pre">memory_order_acquire</span></code>. It should also be
+used for C++11/C11 <code class="docutils literal"><span class="pre">memory_order_consume</span></code>.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution.
+Acquire only provides a semantic guarantee when paired with a Release
+operation.</dd>
+<dt>Notes for optimizers</dt>
+<dd>Optimizers not aware of atomics can treat this like a nothrow call.  It is
+also possible to move stores from before an Acquire load or read-modify-write
+operation to after it, and move non-Acquire loads from before an Acquire
+operation to after it.</dd>
+<dt>Notes for code generation</dt>
+<dd>Architectures with weak memory ordering (essentially everything relevant today
+except x86 and SPARC) require some sort of fence to maintain the Acquire
+semantics.  The precise fences required varies widely by architecture, but for
+a simple implementation, most architectures provide a barrier which is strong
+enough for everything (<code class="docutils literal"><span class="pre">dmb</span></code> on ARM, <code class="docutils literal"><span class="pre">sync</span></code> on PowerPC, etc.).  Putting
+such a fence after the equivalent Monotonic operation is sufficient to
+maintain Acquire semantics for a memory operation.</dd>
+</dl>
+</div>
+<div class="section" id="release">
+<h3><a class="toc-backref" href="#id12">Release</a><a class="headerlink" href="#release" title="Permalink to this headline">¶</a></h3>
+<p>Release is similar to Acquire, but with a barrier of the sort necessary to
+release a lock.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal"><span class="pre">memory_order_release</span></code>.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution.
+Release only provides a semantic guarantee when paired with a Acquire
+operation.</dd>
+<dt>Notes for optimizers</dt>
+<dd>Optimizers not aware of atomics can treat this like a nothrow call.  It is
+also possible to move loads from after a Release store or read-modify-write
+operation to before it, and move non-Release stores from after an Release
+operation to before it.</dd>
+<dt>Notes for code generation</dt>
+<dd>See the section on Acquire; a fence before the relevant operation is usually
+sufficient for Release. Note that a store-store fence is not sufficient to
+implement Release semantics; store-store fences are generally not exposed to
+IR because they are extremely difficult to use correctly.</dd>
+</dl>
+</div>
+<div class="section" id="acquirerelease">
+<h3><a class="toc-backref" href="#id13">AcquireRelease</a><a class="headerlink" href="#acquirerelease" title="Permalink to this headline">¶</a></h3>
+<p>AcquireRelease (<code class="docutils literal"><span class="pre">acq_rel</span></code> in IR) provides both an Acquire and a Release
+barrier (for fences and operations which both read and write memory).</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal"><span class="pre">memory_order_acq_rel</span></code>.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution.
+Acquire only provides a semantic guarantee when paired with a Release
+operation, and vice versa.</dd>
+<dt>Notes for optimizers</dt>
+<dd>In general, optimizers should treat this like a nothrow call; the possible
+optimizations are usually not interesting.</dd>
+<dt>Notes for code generation</dt>
+<dd>This operation has Acquire and Release semantics; see the sections on Acquire
+and Release.</dd>
+</dl>
+</div>
+<div class="section" id="sequentiallyconsistent">
+<h3><a class="toc-backref" href="#id14">SequentiallyConsistent</a><a class="headerlink" href="#sequentiallyconsistent" title="Permalink to this headline">¶</a></h3>
+<p>SequentiallyConsistent (<code class="docutils literal"><span class="pre">seq_cst</span></code> in IR) provides Acquire semantics for loads
+and Release semantics for stores. Additionally, it guarantees that a total
+ordering exists between all SequentiallyConsistent operations.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal"><span class="pre">memory_order_seq_cst</span></code>, Java volatile, and
+the gcc-compatible <code class="docutils literal"><span class="pre">__sync_*</span></code> builtins which do not specify otherwise.</dd>
+<dt>Notes for frontends</dt>
+<dd>If a frontend is exposing atomic operations, these are much easier to reason
+about for the programmer than other kinds of operations, and using them is
+generally a practical performance tradeoff.</dd>
+<dt>Notes for optimizers</dt>
+<dd>Optimizers not aware of atomics can treat this like a nothrow call.  For
+SequentiallyConsistent loads and stores, the same reorderings are allowed as
+for Acquire loads and Release stores, except that SequentiallyConsistent
+operations may not be reordered.</dd>
+<dt>Notes for code generation</dt>
+<dd>SequentiallyConsistent loads minimally require the same barriers as Acquire
+operations and SequentiallyConsistent stores require Release
+barriers. Additionally, the code generator must enforce ordering between
+SequentiallyConsistent stores followed by SequentiallyConsistent loads. This
+is usually done by emitting either a full fence before the loads or a full
+fence after the stores; which is preferred varies by architecture.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="atomics-and-ir-optimization">
+<h2><a class="toc-backref" href="#id15">Atomics and IR optimization</a><a class="headerlink" href="#atomics-and-ir-optimization" title="Permalink to this headline">¶</a></h2>
+<p>Predicates for optimizer writers to query:</p>
+<ul class="simple">
+<li><code class="docutils literal"><span class="pre">isSimple()</span></code>: A load or store which is not volatile or atomic.  This is
+what, for example, memcpyopt would check for operations it might transform.</li>
+<li><code class="docutils literal"><span class="pre">isUnordered()</span></code>: A load or store which is not volatile and at most
+Unordered. This would be checked, for example, by LICM before hoisting an
+operation.</li>
+<li><code class="docutils literal"><span class="pre">mayReadFromMemory()</span></code>/<code class="docutils literal"><span class="pre">mayWriteToMemory()</span></code>: Existing predicate, but note
+that they return true for any operation which is volatile or at least
+Monotonic.</li>
+<li><code class="docutils literal"><span class="pre">isStrongerThan</span></code> / <code class="docutils literal"><span class="pre">isAtLeastOrStrongerThan</span></code>: These are predicates on
+orderings. They can be useful for passes that are aware of atomics, for
+example to do DSE across a single atomic access, but not across a
+release-acquire pair (see MemoryDependencyAnalysis for an example of this)</li>
+<li>Alias analysis: Note that AA will return ModRef for anything Acquire or
+Release, and for the address accessed by any Monotonic operation.</li>
+</ul>
+<p>To support optimizing around atomic operations, make sure you are using the
+right predicates; everything should work if that is done.  If your pass should
+optimize some atomic operations (Unordered operations in particular), make sure
+it doesn’t replace an atomic load or store with a non-atomic operation.</p>
+<p>Some examples of how optimizations interact with various kinds of atomic
+operations:</p>
+<ul class="simple">
+<li><code class="docutils literal"><span class="pre">memcpyopt</span></code>: An atomic operation cannot be optimized into part of a
+memcpy/memset, including unordered loads/stores.  It can pull operations
+across some atomic operations.</li>
+<li>LICM: Unordered loads/stores can be moved out of a loop.  It just treats
+monotonic operations like a read+write to a memory location, and anything
+stricter than that like a nothrow call.</li>
+<li>DSE: Unordered stores can be DSE’ed like normal stores.  Monotonic stores can
+be DSE’ed in some cases, but it’s tricky to reason about, and not especially
+important. It is possible in some case for DSE to operate across a stronger
+atomic operation, but it is fairly tricky. DSE delegates this reasoning to
+MemoryDependencyAnalysis (which is also used by other passes like GVN).</li>
+<li>Folding a load: Any atomic load from a constant global can be constant-folded,
+because it cannot be observed.  Similar reasoning allows sroa with
+atomic loads and stores.</li>
+</ul>
+</div>
+<div class="section" id="atomics-and-codegen">
+<h2><a class="toc-backref" href="#id16">Atomics and Codegen</a><a class="headerlink" href="#atomics-and-codegen" title="Permalink to this headline">¶</a></h2>
+<p>Atomic operations are represented in the SelectionDAG with <code class="docutils literal"><span class="pre">ATOMIC_*</span></code> opcodes.
+On architectures which use barrier instructions for all atomic ordering (like
+ARM), appropriate fences can be emitted by the AtomicExpand Codegen pass if
+<code class="docutils literal"><span class="pre">setInsertFencesForAtomic()</span></code> was used.</p>
+<p>The MachineMemOperand for all atomic operations is currently marked as volatile;
+this is not correct in the IR sense of volatile, but CodeGen handles anything
+marked volatile very conservatively.  This should get fixed at some point.</p>
+<p>One very important property of the atomic operations is that if your backend
+supports any inline lock-free atomic operations of a given size, you should
+support <em>ALL</em> operations of that size in a lock-free manner.</p>
+<p>When the target implements atomic <code class="docutils literal"><span class="pre">cmpxchg</span></code> or LL/SC instructions (as most do)
+this is trivial: all the other operations can be implemented on top of those
+primitives. However, on many older CPUs (e.g. ARMv5, SparcV8, Intel 80386) there
+are atomic load and store instructions, but no <code class="docutils literal"><span class="pre">cmpxchg</span></code> or LL/SC. As it is
+invalid to implement <code class="docutils literal"><span class="pre">atomic</span> <span class="pre">load</span></code> using the native instruction, but
+<code class="docutils literal"><span class="pre">cmpxchg</span></code> using a library call to a function that uses a mutex, <code class="docutils literal"><span class="pre">atomic</span>
+<span class="pre">load</span></code> must <em>also</em> expand to a library call on such architectures, so that it
+can remain atomic with regards to a simultaneous <code class="docutils literal"><span class="pre">cmpxchg</span></code>, by using the same
+mutex.</p>
+<p>AtomicExpandPass can help with that: it will expand all atomic operations to the
+proper <code class="docutils literal"><span class="pre">__atomic_*</span></code> libcalls for any size above the maximum set by
+<code class="docutils literal"><span class="pre">setMaxAtomicSizeInBitsSupported</span></code> (which defaults to 0).</p>
+<p>On x86, all atomic loads generate a <code class="docutils literal"><span class="pre">MOV</span></code>. SequentiallyConsistent stores
+generate an <code class="docutils literal"><span class="pre">XCHG</span></code>, other stores generate a <code class="docutils literal"><span class="pre">MOV</span></code>. SequentiallyConsistent
+fences generate an <code class="docutils literal"><span class="pre">MFENCE</span></code>, other fences do not cause any code to be
+generated.  <code class="docutils literal"><span class="pre">cmpxchg</span></code> uses the <code class="docutils literal"><span class="pre">LOCK</span> <span class="pre">CMPXCHG</span></code> instruction.  <code class="docutils literal"><span class="pre">atomicrmw</span> <span class="pre">xchg</span></code>
+uses <code class="docutils literal"><span class="pre">XCHG</span></code>, <code class="docutils literal"><span class="pre">atomicrmw</span> <span class="pre">add</span></code> and <code class="docutils literal"><span class="pre">atomicrmw</span> <span class="pre">sub</span></code> use <code class="docutils literal"><span class="pre">XADD</span></code>, and all
+other <code class="docutils literal"><span class="pre">atomicrmw</span></code> operations generate a loop with <code class="docutils literal"><span class="pre">LOCK</span> <span class="pre">CMPXCHG</span></code>.  Depending
+on the users of the result, some <code class="docutils literal"><span class="pre">atomicrmw</span></code> operations can be translated into
+operations like <code class="docutils literal"><span class="pre">LOCK</span> <span class="pre">AND</span></code>, but that does not work in general.</p>
+<p>On ARM (before v8), MIPS, and many other RISC architectures, Acquire, Release,
+and SequentiallyConsistent semantics require barrier instructions for every such
+operation. Loads and stores generate normal instructions.  <code class="docutils literal"><span class="pre">cmpxchg</span></code> and
+<code class="docutils literal"><span class="pre">atomicrmw</span></code> can be represented using a loop with LL/SC-style instructions
+which take some sort of exclusive lock on a cache line (<code class="docutils literal"><span class="pre">LDREX</span></code> and <code class="docutils literal"><span class="pre">STREX</span></code>
+on ARM, etc.).</p>
+<p>It is often easiest for backends to use AtomicExpandPass to lower some of the
+atomic constructs. Here are some lowerings it can do:</p>
+<ul class="simple">
+<li>cmpxchg -> loop with load-linked/store-conditional
+by overriding <code class="docutils literal"><span class="pre">shouldExpandAtomicCmpXchgInIR()</span></code>, <code class="docutils literal"><span class="pre">emitLoadLinked()</span></code>,
+<code class="docutils literal"><span class="pre">emitStoreConditional()</span></code></li>
+<li>large loads/stores -> ll-sc/cmpxchg
+by overriding <code class="docutils literal"><span class="pre">shouldExpandAtomicStoreInIR()</span></code>/<code class="docutils literal"><span class="pre">shouldExpandAtomicLoadInIR()</span></code></li>
+<li>strong atomic accesses -> monotonic accesses + fences by overriding
+<code class="docutils literal"><span class="pre">shouldInsertFencesForAtomic()</span></code>, <code class="docutils literal"><span class="pre">emitLeadingFence()</span></code>, and
+<code class="docutils literal"><span class="pre">emitTrailingFence()</span></code></li>
+<li>atomic rmw -> loop with cmpxchg or load-linked/store-conditional
+by overriding <code class="docutils literal"><span class="pre">expandAtomicRMWInIR()</span></code></li>
+<li>expansion to __atomic_* libcalls for unsupported sizes.</li>
+</ul>
+<p>For an example of all of these, look at the ARM backend.</p>
+</div>
+<div class="section" id="libcalls-atomic">
+<h2><a class="toc-backref" href="#id17">Libcalls: __atomic_*</a><a class="headerlink" href="#libcalls-atomic" title="Permalink to this headline">¶</a></h2>
+<p>There are two kinds of atomic library calls that are generated by LLVM. Please
+note that both sets of library functions somewhat confusingly share the names of
+builtin functions defined by clang. Despite this, the library functions are
+not directly related to the builtins: it is <em>not</em> the case that <code class="docutils literal"><span class="pre">__atomic_*</span></code>
+builtins lower to <code class="docutils literal"><span class="pre">__atomic_*</span></code> library calls and <code class="docutils literal"><span class="pre">__sync_*</span></code> builtins lower
+to <code class="docutils literal"><span class="pre">__sync_*</span></code> library calls.</p>
+<p>The first set of library functions are named <code class="docutils literal"><span class="pre">__atomic_*</span></code>. This set has been
+“standardized” by GCC, and is described below. (See also <a class="reference external" href="https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary">GCC’s documentation</a>)</p>
+<p>LLVM’s AtomicExpandPass will translate atomic operations on data sizes above
+<code class="docutils literal"><span class="pre">MaxAtomicSizeInBitsSupported</span></code> into calls to these functions.</p>
+<p>There are four generic functions, which can be called with data of any size or
+alignment:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">void</span> <span class="n">__atomic_load</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ret</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">void</span> <span class="n">__atomic_store</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">void</span> <span class="n">__atomic_exchange</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">val</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ret</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="nb">bool</span> <span class="n">__atomic_compare_exchange</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">expected</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">desired</span><span class="p">,</span> <span class="nb">int</span> <span class="n">success_order</span><span class="p">,</span> <span class="nb">int</span> <span class="n">failure_order</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>There are also size-specialized versions of the above functions, which can only
+be used with <em>naturally-aligned</em> pointers of the appropriate size. In the
+signatures below, “N” is one of 1, 2, 4, 8, and 16, and “iN” is the appropriate
+integer type of that size; if no such integer type exists, the specialization
+cannot be used:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">iN</span> <span class="n">__atomic_load_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">void</span> <span class="n">__atomic_store_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_exchange_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="nb">bool</span> <span class="n">__atomic_compare_exchange_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="o">*</span><span class="n">expected</span><span class="p">,</span> <span class="n">iN</span> <span class="n">desired</span><span class="p">,</span> <span class="nb">int</span> <span class="n">success_order</span><span class="p">,</span> <span class="nb">int</span> <span class="n">failure_order</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>Finally there are some read-modify-write functions, which are only available in
+the size-specific variants (any other sizes use a <code class="docutils literal"><span class="pre">__atomic_compare_exchange</span></code>
+loop):</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">iN</span> <span class="n">__atomic_fetch_add_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_sub_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_and_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_or_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_xor_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_nand_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>This set of library functions have some interesting implementation requirements
+to take note of:</p>
+<ul class="simple">
+<li>They support all sizes and alignments – including those which cannot be
+implemented natively on any existing hardware. Therefore, they will certainly
+use mutexes in for some sizes/alignments.</li>
+<li>As a consequence, they cannot be shipped in a statically linked
+compiler-support library, as they have state which must be shared amongst all
+DSOs loaded in the program. They must be provided in a shared library used by
+all objects.</li>
+<li>The set of atomic sizes supported lock-free must be a superset of the sizes
+any compiler can emit. That is: if a new compiler introduces support for
+inline-lock-free atomics of size N, the <code class="docutils literal"><span class="pre">__atomic_*</span></code> functions must also have a
+lock-free implementation for size N. This is a requirement so that code
+produced by an old compiler (which will have called the <code class="docutils literal"><span class="pre">__atomic_*</span></code> function)
+interoperates with code produced by the new compiler (which will use native
+the atomic instruction).</li>
+</ul>
+<p>Note that it’s possible to write an entirely target-independent implementation
+of these library functions by using the compiler atomic builtins themselves to
+implement the operations on naturally-aligned pointers of supported sizes, and a
+generic mutex implementation otherwise.</p>
+</div>
+<div class="section" id="libcalls-sync">
+<h2><a class="toc-backref" href="#id18">Libcalls: __sync_*</a><a class="headerlink" href="#libcalls-sync" title="Permalink to this headline">¶</a></h2>
+<p>Some targets or OS/target combinations can support lock-free atomics, but for
+various reasons, it is not practical to emit the instructions inline.</p>
+<p>There’s two typical examples of this.</p>
+<p>Some CPUs support multiple instruction sets which can be swiched back and forth
+on function-call boundaries. For example, MIPS supports the MIPS16 ISA, which
+has a smaller instruction encoding than the usual MIPS32 ISA. ARM, similarly,
+has the Thumb ISA. In MIPS16 and earlier versions of Thumb, the atomic
+instructions are not encodable. However, those instructions are available via a
+function call to a function with the longer encoding.</p>
+<p>Additionally, a few OS/target pairs provide kernel-supported lock-free
+atomics. ARM/Linux is an example of this: the kernel <a class="reference external" href="https://www.kernel.org/doc/Documentation/arm/kernel_user_helpers.txt">provides</a> a
+function which on older CPUs contains a “magically-restartable” atomic sequence
+(which looks atomic so long as there’s only one CPU), and contains actual atomic
+instructions on newer multicore models. This sort of functionality can typically
+be provided on any architecture, if all CPUs which are missing atomic
+compare-and-swap support are uniprocessor (no SMP). This is almost always the
+case. The only common architecture without that property is SPARC – SPARCV8 SMP
+systems were common, yet it doesn’t support any sort of compare-and-swap
+operation.</p>
+<p>In either of these cases, the Target in LLVM can claim support for atomics of an
+appropriate size, and then implement some subset of the operations via libcalls
+to a <code class="docutils literal"><span class="pre">__sync_*</span></code> function. Such functions <em>must</em> not use locks in their
+implementation, because unlike the <code class="docutils literal"><span class="pre">__atomic_*</span></code> routines used by
+AtomicExpandPass, these may be mixed-and-matched with native instructions by the
+target lowering.</p>
+<p>Further, these routines do not need to be shared, as they are stateless. So,
+there is no issue with having multiple copies included in one binary. Thus,
+typically these routines are implemented by the statically-linked compiler
+runtime support library.</p>
+<p>LLVM will emit a call to an appropriate <code class="docutils literal"><span class="pre">__sync_*</span></code> routine if the target
+ISelLowering code has set the corresponding <code class="docutils literal"><span class="pre">ATOMIC_CMPXCHG</span></code>, <code class="docutils literal"><span class="pre">ATOMIC_SWAP</span></code>,
+or <code class="docutils literal"><span class="pre">ATOMIC_LOAD_*</span></code> operation to “Expand”, and if it has opted-into the
+availability of those library functions via a call to <code class="docutils literal"><span class="pre">initSyncLibcalls()</span></code>.</p>
+<p>The full set of functions that may be called by LLVM is (for <code class="docutils literal"><span class="pre">N</span></code> being 1, 2,
+4, 8, or 16):</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">iN</span> <span class="n">__sync_val_compare_and_swap_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">expected</span><span class="p">,</span> <span class="n">iN</span> <span class="n">desired</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_lock_test_and_set_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_add_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_sub_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_and_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_or_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_xor_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_nand_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_max_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_umax_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_min_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_umin_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>This list doesn’t include any function for atomic load or store; all known
+architectures support atomic loads and stores directly (possibly by emitting a
+fence on either side of a normal load or store.)</p>
+<p>There’s also, somewhat separately, the possibility to lower <code class="docutils literal"><span class="pre">ATOMIC_FENCE</span></code> to
+<code class="docutils literal"><span class="pre">__sync_synchronize()</span></code>. This may happen or not happen independent of all the
+above, controlled purely by <code class="docutils literal"><span class="pre">setOperationAction(ISD::ATOMIC_FENCE,</span> <span class="pre">...)</span></code>.</p>
+</div>
+</div>
+
+
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+            
+  <div class="section" id="benchmarking-tips">
+<h1>Benchmarking tips<a class="headerlink" href="#benchmarking-tips" title="Permalink to this headline">¶</a></h1>
+<div class="section" id="introduction">
+<h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>For benchmarking a patch we want to reduce all possible sources of
+noise as much as possible. How to do that is very OS dependent.</p>
+<p>Note that low noise is required, but not sufficient. It does not
+exclude measurement bias. See
+<a class="reference external" href="https://www.cis.upenn.edu/~cis501/papers/producing-wrong-data.pdf">https://www.cis.upenn.edu/~cis501/papers/producing-wrong-data.pdf</a> for
+example.</p>
+</div>
+<div class="section" id="general">
+<h2>General<a class="headerlink" href="#general" title="Permalink to this headline">¶</a></h2>
+<ul>
+<li><p class="first">Use a high resolution timer, e.g. perf under linux.</p>
+</li>
+<li><p class="first">Run the benchmark multiple times to be able to recognize noise.</p>
+</li>
+<li><p class="first">Disable as many processes or services as possible on the target system.</p>
+</li>
+<li><p class="first">Disable frequency scaling, turbo boost and address space
+randomization (see OS specific section).</p>
+</li>
+<li><p class="first">Static link if the OS supports it. That avoids any variation that
+might be introduced by loading dynamic libraries. This can be done
+by passing <code class="docutils literal"><span class="pre">-DLLVM_BUILD_STATIC=ON</span></code> to cmake.</p>
+</li>
+<li><p class="first">Try to avoid storage. On some systems you can use tmpfs. Putting the
+program, inputs and outputs on tmpfs avoids touching a real storage
+system, which can have a pretty big variability.</p>
+<p>To mount it (on linux and freebsd at least):</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">mount</span> <span class="o">-</span><span class="n">t</span> <span class="n">tmpfs</span> <span class="o">-</span><span class="n">o</span> <span class="n">size</span><span class="o">=<</span><span class="n">XX</span><span class="o">></span><span class="n">g</span> <span class="n">none</span> <span class="n">dir_to_mount</span>
+</pre></div>
+</div>
+</li>
+</ul>
+</div>
+<div class="section" id="linux">
+<h2>Linux<a class="headerlink" href="#linux" title="Permalink to this headline">¶</a></h2>
+<ul>
+<li><p class="first">Disable address space randomization:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">echo</span> <span class="mi">0</span> <span class="o">></span> <span class="o">/</span><span class="n">proc</span><span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">kernel</span><span class="o">/</span><span class="n">randomize_va_space</span>
+</pre></div>
+</div>
+</li>
+<li><p class="first">Set scaling_governor to performance:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="k">for</span> <span class="n">i</span> <span class="ow">in</span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">cpu</span><span class="o">*/</span><span class="n">cpufreq</span><span class="o">/</span><span class="n">scaling_governor</span>
+<span class="n">do</span>
+  <span class="n">echo</span> <span class="n">performance</span> <span class="o">></span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">cpu</span><span class="o">*/</span><span class="n">cpufreq</span><span class="o">/</span><span class="n">scaling_governor</span>
+<span class="n">done</span>
+</pre></div>
+</div>
+</li>
+<li><p class="first">Use <a class="reference external" href="https://github.com/lpechacek/cpuset">https://github.com/lpechacek/cpuset</a> to reserve cpus for just the
+program you are benchmarking. If using perf, leave at least 2 cores
+so that perf runs in one and your program in another:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">cset</span> <span class="n">shield</span> <span class="o">-</span><span class="n">c</span> <span class="n">N1</span><span class="p">,</span><span class="n">N2</span> <span class="o">-</span><span class="n">k</span> <span class="n">on</span>
+</pre></div>
+</div>
+<p>This will move all threads out of N1 and N2. The <code class="docutils literal"><span class="pre">-k</span> <span class="pre">on</span></code> means
+that even kernel threads are moved out.</p>
+</li>
+<li><p class="first">Disable the SMT pair of the cpus you will use for the benchmark. The
+pair of cpu N can be found in
+<code class="docutils literal"><span class="pre">/sys/devices/system/cpu/cpuN/topology/thread_siblings_list</span></code> and
+disabled with:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">echo</span> <span class="mi">0</span> <span class="o">></span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">cpuX</span><span class="o">/</span><span class="n">online</span>
+</pre></div>
+</div>
+</li>
+<li><p class="first">Run the program with:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">cset</span> <span class="n">shield</span> <span class="o">--</span><span class="n">exec</span> <span class="o">--</span> <span class="n">perf</span> <span class="n">stat</span> <span class="o">-</span><span class="n">r</span> <span class="mi">10</span> <span class="o"><</span><span class="n">cmd</span><span class="o">></span>
+</pre></div>
+</div>
+<p>This will run the command after <code class="docutils literal"><span class="pre">--</span></code> in the isolated cpus. The
+particular perf command runs the <code class="docutils literal"><span class="pre"><cmd></span></code> 10 times and reports
+statistics.</p>
+</li>
+</ul>
+<p>With these in place you can expect perf variations of less than 0.1%.</p>
+<div class="section" id="linux-intel">
+<h3>Linux Intel<a class="headerlink" href="#linux-intel" title="Permalink to this headline">¶</a></h3>
+<ul>
+<li><p class="first">Disable turbo mode:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">echo</span> <span class="mi">1</span> <span class="o">></span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">intel_pstate</span><span class="o">/</span><span class="n">no_turbo</span>
+</pre></div>
+</div>
+</li>
+</ul>
+</div>
+</div>
+</div>
+
+
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+  <div class="section" id="using-arm-neon-instructions-in-big-endian-mode">
+<h1>Using ARM NEON instructions in big endian mode<a class="headerlink" href="#using-arm-neon-instructions-in-big-endian-mode" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id5">Introduction</a><ul>
+<li><a class="reference internal" href="#example-c-level-intrinsics-assembly" id="id6">Example: C-level intrinsics -> assembly</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#problem" id="id7">Problem</a></li>
+<li><a class="reference internal" href="#ldr-and-ld1" id="id8"><code class="docutils literal"><span class="pre">LDR</span></code> and <code class="docutils literal"><span class="pre">LD1</span></code></a></li>
+<li><a class="reference internal" href="#considerations" id="id9">Considerations</a><ul>
+<li><a class="reference internal" href="#llvm-ir-lane-ordering" id="id10">LLVM IR Lane ordering</a></li>
+<li><a class="reference internal" href="#aapcs" id="id11">AAPCS</a></li>
+<li><a class="reference internal" href="#alignment" id="id12">Alignment</a></li>
+<li><a class="reference internal" href="#summary" id="id13">Summary</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#implementation" id="id14">Implementation</a><ul>
+<li><a class="reference internal" href="#bitconverts" id="id15">Bitconverts</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id5">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Generating code for big endian ARM processors is for the most part straightforward. NEON loads and stores however have some interesting properties that make code generation decisions less obvious in big endian mode.</p>
+<p>The aim of this document is to explain the problem with NEON loads and stores, and the solution that has been implemented in LLVM.</p>
+<p>In this document the term “vector” refers to what the ARM ABI calls a “short vector”, which is a sequence of items that can fit in a NEON register. This sequence can be 64 or 128 bits in length, and can constitute 8, 16, 32 or 64 bit items. This document refers to A64 instructions throughout, but is almost applicable to the A32/ARMv7 instruction sets also. The ABI format for passing vectors in A32 is sligtly different to A64. Apart from that, the same concepts apply.</p>
+<div class="section" id="example-c-level-intrinsics-assembly">
+<h3><a class="toc-backref" href="#id6">Example: C-level intrinsics -> assembly</a><a class="headerlink" href="#example-c-level-intrinsics-assembly" title="Permalink to this headline">¶</a></h3>
+<p>It may be helpful first to illustrate how C-level ARM NEON intrinsics are lowered to instructions.</p>
+<p>This trivial C function takes a vector of four ints and sets the zero’th lane to the value “42”:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="c1">#include <arm_neon.h></span>
+<span class="n">int32x4_t</span> <span class="n">f</span><span class="p">(</span><span class="n">int32x4_t</span> <span class="n">p</span><span class="p">)</span> <span class="p">{</span>
+    <span class="k">return</span> <span class="n">vsetq_lane_s32</span><span class="p">(</span><span class="mi">42</span><span class="p">,</span> <span class="n">p</span><span class="p">,</span> <span class="mi">0</span><span class="p">);</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>arm_neon.h intrinsics generate “generic” IR where possible (that is, normal IR instructions not <code class="docutils literal"><span class="pre">llvm.arm.neon.*</span></code> intrinsic calls). The above generates:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">define</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="nd">@f</span><span class="p">(</span><span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">p</span><span class="p">)</span> <span class="p">{</span>
+  <span class="o">%</span><span class="n">vset_lane</span> <span class="o">=</span> <span class="n">insertelement</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">p</span><span class="p">,</span> <span class="n">i32</span> <span class="mi">42</span><span class="p">,</span> <span class="n">i32</span> <span class="mi">0</span>
+  <span class="n">ret</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">vset_lane</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>Which then becomes the following trivial assembly:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">f</span><span class="p">:</span>                                      <span class="o">//</span> <span class="nd">@f</span>
+        <span class="n">movz</span>        <span class="n">w8</span><span class="p">,</span> <span class="c1">#0x2a</span>
+        <span class="n">ins</span>         <span class="n">v0</span><span class="o">.</span><span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">],</span> <span class="n">w8</span>
+        <span class="n">ret</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="problem">
+<h2><a class="toc-backref" href="#id7">Problem</a><a class="headerlink" href="#problem" title="Permalink to this headline">¶</a></h2>
+<p>The main problem is how vectors are represented in memory and in registers.</p>
+<p>First, a recap. The “endianness” of an item affects its representation in memory only. In a register, a number is just a sequence of bits - 64 bits in the case of AArch64 general purpose registers. Memory, however, is a sequence of addressable units of 8 bits in size. Any number greater than 8 bits must therefore be split up into 8-bit chunks, and endianness describes the order in which these chunks are laid out in memory.</p>
+<p>A “little endian” layout has the least significant byte first (lowest in memory address). A “big endian” layout has the <em>most</em> significant byte first. This means that when loading an item from big endian memory, the lowest 8-bits in memory must go in the most significant 8-bits, and so forth.</p>
+</div>
+<div class="section" id="ldr-and-ld1">
+<h2><a class="toc-backref" href="#id8"><code class="docutils literal"><span class="pre">LDR</span></code> and <code class="docutils literal"><span class="pre">LD1</span></code></a><a class="headerlink" href="#ldr-and-ld1" title="Permalink to this headline">¶</a></h2>
+<div class="figure align-right" id="id3">
+<img alt="_images/ARM-BE-ldr.png" src="_images/ARM-BE-ldr.png" />
+<p class="caption"><span class="caption-text">Big endian vector load using <code class="docutils literal"><span class="pre">LDR</span></code>.</span></p>
+</div>
+<p>A vector is a consecutive sequence of items that are operated on simultaneously. To load a 64-bit vector, 64 bits need to be read from memory. In little endian mode, we can do this by just performing a 64-bit load - <code class="docutils literal"><span class="pre">LDR</span> <span class="pre">q0,</span> <span class="pre">[foo]</span></code>. However if we try this in big endian mode, because of the byte swapping the lane indices end up being swapped! The zero’th item as laid out in memory becomes the n’th lane in the vector.</p>
+<div class="figure align-right" id="id4">
+<img alt="_images/ARM-BE-ld1.png" src="_images/ARM-BE-ld1.png" />
+<p class="caption"><span class="caption-text">Big endian vector load using <code class="docutils literal"><span class="pre">LD1</span></code>. Note that the lanes retain the correct ordering.</span></p>
+</div>
+<p>Because of this, the instruction <code class="docutils literal"><span class="pre">LD1</span></code> performs a vector load but performs byte swapping not on the entire 64 bits, but on the individual items within the vector. This means that the register content is the same as it would have been on a little endian system.</p>
+<p>It may seem that <code class="docutils literal"><span class="pre">LD1</span></code> should suffice to peform vector loads on a big endian machine. However there are pros and cons to the two approaches that make it less than simple which register format to pick.</p>
+<p>There are two options:</p>
+<blockquote>
+<div><ol class="arabic simple">
+<li>The content of a vector register is the same <em>as if</em> it had been loaded with an <code class="docutils literal"><span class="pre">LDR</span></code> instruction.</li>
+<li>The content of a vector register is the same <em>as if</em> it had been loaded with an <code class="docutils literal"><span class="pre">LD1</span></code> instruction.</li>
+</ol>
+</div></blockquote>
+<p>Because <code class="docutils literal"><span class="pre">LD1</span> <span class="pre">==</span> <span class="pre">LDR</span> <span class="pre">+</span> <span class="pre">REV</span></code> and similarly <code class="docutils literal"><span class="pre">LDR</span> <span class="pre">==</span> <span class="pre">LD1</span> <span class="pre">+</span> <span class="pre">REV</span></code> (on a big endian system), we can simulate either type of load with the other type of load plus a <code class="docutils literal"><span class="pre">REV</span></code> instruction. So we’re not deciding which instructions to use, but which format to use (which will then influence which instruction is best to use).</p>
+<div class="clearer docutils container">
+Note that throughout this section we only mention loads. Stores have exactly the same problems as their associated loads, so have been skipped for brevity.</div>
+</div>
+<div class="section" id="considerations">
+<h2><a class="toc-backref" href="#id9">Considerations</a><a class="headerlink" href="#considerations" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="llvm-ir-lane-ordering">
+<h3><a class="toc-backref" href="#id10">LLVM IR Lane ordering</a><a class="headerlink" href="#llvm-ir-lane-ordering" title="Permalink to this headline">¶</a></h3>
+<p>LLVM IR has first class vector types. In LLVM IR, the zero’th element of a vector resides at the lowest memory address. The optimizer relies on this property in certain areas, for example when concatenating vectors together. The intention is for arrays and vectors to have identical memory layouts - <code class="docutils literal"><span class="pre">[4</span> <span class="pre">x</span> <span class="pre">i8]</span></code> and <code class="docutils literal"><span class="pre"><4</span> <span class="pre">x</span> <span class="pre">i8></span></code> should be represented the same in memory. Without this property there would be many special cases that the optimizer would have to cleverly handle.</p>
+<p>Use of <code class="docutils literal"><span class="pre">LDR</span></code> would break this lane ordering property. This doesn’t preclude the use of <code class="docutils literal"><span class="pre">LDR</span></code>, but we would have to do one of two things:</p>
+<blockquote>
+<div><ol class="arabic simple">
+<li>Insert a <code class="docutils literal"><span class="pre">REV</span></code> instruction to reverse the lane order after every <code class="docutils literal"><span class="pre">LDR</span></code>.</li>
+<li>Disable all optimizations that rely on lane layout, and for every access to an individual lane (<code class="docutils literal"><span class="pre">insertelement</span></code>/<code class="docutils literal"><span class="pre">extractelement</span></code>/<code class="docutils literal"><span class="pre">shufflevector</span></code>) reverse the lane index.</li>
+</ol>
+</div></blockquote>
+</div>
+<div class="section" id="aapcs">
+<h3><a class="toc-backref" href="#id11">AAPCS</a><a class="headerlink" href="#aapcs" title="Permalink to this headline">¶</a></h3>
+<p>The ARM procedure call standard (AAPCS) defines the ABI for passing vectors between functions in registers. It states:</p>
+<blockquote>
+<div><p>When a short vector is transferred between registers and memory it is treated as an opaque object. That is a short vector is stored in memory as if it were stored with a single <code class="docutils literal"><span class="pre">STR</span></code> of the entire register; a short vector is loaded from memory using the corresponding <code class="docutils literal"><span class="pre">LDR</span></code> instruction. On a little-endian system this means that element 0 will always contain the lowest addressed element of a short vector; on a big-endian system element 0 will contain the highest-addressed element of a short vector.</p>
+<p class="attribution">—Procedure Call Standard for the ARM 64-bit Architecture (AArch64), 4.1.2 Short Vectors</p>
+</div></blockquote>
+<p>The use of <code class="docutils literal"><span class="pre">LDR</span></code> and <code class="docutils literal"><span class="pre">STR</span></code> as the ABI defines has at least one advantage over <code class="docutils literal"><span class="pre">LD1</span></code> and <code class="docutils literal"><span class="pre">ST1</span></code>. <code class="docutils literal"><span class="pre">LDR</span></code> and <code class="docutils literal"><span class="pre">STR</span></code> are oblivious to the size of the individual lanes of a vector. <code class="docutils literal"><span class="pre">LD1</span></code> and <code class="docutils literal"><span class="pre">ST1</span></code> are not - the lane size is encoded within them. This is important across an ABI boundary, because it would become necessary to know the lane width the callee expects. Consider the following code:</p>
+<div class="highlight-c"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">callee</span><span class="p">.</span><span class="n">c</span><span class="o">></span>
+<span class="kt">void</span> <span class="n">callee</span><span class="p">(</span><span class="n">uint32x2_t</span> <span class="n">v</span><span class="p">)</span> <span class="p">{</span>
+  <span class="p">...</span>
+<span class="p">}</span>
+
+<span class="o"><</span><span class="n">caller</span><span class="p">.</span><span class="n">c</span><span class="o">></span>
+<span class="k">extern</span> <span class="kt">void</span> <span class="n">callee</span><span class="p">(</span><span class="n">uint32x2_t</span><span class="p">);</span>
+<span class="kt">void</span> <span class="nf">caller</span><span class="p">()</span> <span class="p">{</span>
+  <span class="n">callee</span><span class="p">(...);</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>If <code class="docutils literal"><span class="pre">callee</span></code> changed its signature to <code class="docutils literal"><span class="pre">uint16x4_t</span></code>, which is equivalent in register content, if we passed as <code class="docutils literal"><span class="pre">LD1</span></code> we’d break this code until <code class="docutils literal"><span class="pre">caller</span></code> was updated and recompiled.</p>
+<p>There is an argument that if the signatures of the two functions are different then the behaviour should be undefined. But there may be functions that are agnostic to the lane layout of the vector, and treating the vector as an opaque value (just loading it and storing it) would be impossible without a common format across ABI boundaries.</p>
+<p>So to preserve ABI compatibility, we need to use the <code class="docutils literal"><span class="pre">LDR</span></code> lane layout across function calls.</p>
+</div>
+<div class="section" id="alignment">
+<h3><a class="toc-backref" href="#id12">Alignment</a><a class="headerlink" href="#alignment" title="Permalink to this headline">¶</a></h3>
+<p>In strict alignment mode, <code class="docutils literal"><span class="pre">LDR</span> <span class="pre">qX</span></code> requires its address to be 128-bit aligned, whereas <code class="docutils literal"><span class="pre">LD1</span></code> only requires it to be as aligned as the lane size. If we canonicalised on using <code class="docutils literal"><span class="pre">LDR</span></code>, we’d still need to use <code class="docutils literal"><span class="pre">LD1</span></code> in some places to avoid alignment faults (the result of the <code class="docutils literal"><span class="pre">LD1</span></code> would then need to be reversed with <code class="docutils literal"><span class="pre">REV</span></code>).</p>
+<p>Most operating systems however do not run with alignment faults enabled, so this is often not an issue.</p>
+</div>
+<div class="section" id="summary">
+<h3><a class="toc-backref" href="#id13">Summary</a><a class="headerlink" href="#summary" title="Permalink to this headline">¶</a></h3>
+<p>The following table summarises the instructions that are required to be emitted for each property mentioned above for each of the two solutions.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="37%" />
+<col width="37%" />
+<col width="25%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head"> </th>
+<th class="head"><code class="docutils literal"><span class="pre">LDR</span></code> layout</th>
+<th class="head"><code class="docutils literal"><span class="pre">LD1</span></code> layout</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Lane ordering</td>
+<td><code class="docutils literal"><span class="pre">LDR</span> <span class="pre">+</span> <span class="pre">REV</span></code></td>
+<td><code class="docutils literal"><span class="pre">LD1</span></code></td>
+</tr>
+<tr class="row-odd"><td>AAPCS</td>
+<td><code class="docutils literal"><span class="pre">LDR</span></code></td>
+<td><code class="docutils literal"><span class="pre">LD1</span> <span class="pre">+</span> <span class="pre">REV</span></code></td>
+</tr>
+<tr class="row-even"><td>Alignment for strict mode</td>
+<td><code class="docutils literal"><span class="pre">LDR</span></code> / <code class="docutils literal"><span class="pre">LD1</span> <span class="pre">+</span> <span class="pre">REV</span></code></td>
+<td><code class="docutils literal"><span class="pre">LD1</span></code></td>
+</tr>
+</tbody>
+</table>
+<p>Neither approach is perfect, and choosing one boils down to choosing the lesser of two evils. The issue with lane ordering, it was decided, would have to change target-agnostic compiler passes and would result in a strange IR in which lane indices were reversed. It was decided that this was worse than the changes that would have to be made to support <code class="docutils literal"><span class="pre">LD1</span></code>, so <code class="docutils literal"><span class="pre">LD1</span></code> was chosen as the canonical vector load instruction (and by inference, <code class="docutils literal"><span class="pre">ST1</span></code> for vector stores).</p>
+</div>
+</div>
+<div class="section" id="implementation">
+<h2><a class="toc-backref" href="#id14">Implementation</a><a class="headerlink" href="#implementation" title="Permalink to this headline">¶</a></h2>
+<p>There are 3 parts to the implementation:</p>
+<blockquote>
+<div><ol class="arabic simple">
+<li>Predicate <code class="docutils literal"><span class="pre">LDR</span></code> and <code class="docutils literal"><span class="pre">STR</span></code> instructions so that they are never allowed to be selected to generate vector loads and stores. The exception is one-lane vectors <a class="footnote-reference" href="#id2" id="id1">[1]</a> - these by definition cannot have lane ordering problems so are fine to use <code class="docutils literal"><span class="pre">LDR</span></code>/<code class="docutils literal"><span class="pre">STR</span></code>.</li>
+<li>Create code generation patterns for bitconverts that create <code class="docutils literal"><span class="pre">REV</span></code> instructions.</li>
+<li>Make sure appropriate bitconverts are created so that vector values get passed over call boundaries as 1-element vectors (which is the same as if they were loaded with <code class="docutils literal"><span class="pre">LDR</span></code>).</li>
+</ol>
+</div></blockquote>
+<div class="section" id="bitconverts">
+<h3><a class="toc-backref" href="#id15">Bitconverts</a><a class="headerlink" href="#bitconverts" title="Permalink to this headline">¶</a></h3>
+<img alt="_images/ARM-BE-bitcastfail.png" class="align-right" src="_images/ARM-BE-bitcastfail.png" />
+<p>The main problem with the <code class="docutils literal"><span class="pre">LD1</span></code> solution is dealing with bitconverts (or bitcasts, or reinterpret casts). These are pseudo instructions that only change the compiler’s interpretation of data, not the underlying data itself. A requirement is that if data is loaded and then saved again (called a “round trip”), the memory contents should be the same after the store as before the load. If a vector is loaded and is then bitconverted to a different vector type before storing, the round trip will currently be broken.</p>
+<p>Take for example this code sequence:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="o">%</span><span class="mi">0</span> <span class="o">=</span> <span class="n">load</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">x</span>
+<span class="o">%</span><span class="mi">1</span> <span class="o">=</span> <span class="n">bitcast</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="mi">0</span> <span class="n">to</span> <span class="o"><</span><span class="mi">2</span> <span class="n">x</span> <span class="n">i64</span><span class="o">></span>
+     <span class="n">store</span> <span class="o"><</span><span class="mi">2</span> <span class="n">x</span> <span class="n">i64</span><span class="o">></span> <span class="o">%</span><span class="mi">1</span><span class="p">,</span> <span class="o"><</span><span class="mi">2</span> <span class="n">x</span> <span class="n">i64</span><span class="o">>*</span> <span class="o">%</span><span class="n">y</span>
+</pre></div>
+</div>
+<p>This would produce a code sequence such as that in the figure on the right. The mismatched <code class="docutils literal"><span class="pre">LD1</span></code> and <code class="docutils literal"><span class="pre">ST1</span></code> cause the stored data to differ from the loaded data.</p>
+<div class="clearer docutils container">
+When we see a bitcast from type <code class="docutils literal"><span class="pre">X</span></code> to type <code class="docutils literal"><span class="pre">Y</span></code>, what we need to do is to change the in-register representation of the data to be <em>as if</em> it had just been loaded by a <code class="docutils literal"><span class="pre">LD1</span></code> of type <code class="docutils literal"><span class="pre">Y</span></code>.</div>
+<img alt="_images/ARM-BE-bitcastsuccess.png" class="align-right" src="_images/ARM-BE-bitcastsuccess.png" />
+<p>Conceptually this is simple - we can insert a <code class="docutils literal"><span class="pre">REV</span></code> undoing the <code class="docutils literal"><span class="pre">LD1</span></code> of type <code class="docutils literal"><span class="pre">X</span></code> (converting the in-register representation to the same as if it had been loaded by <code class="docutils literal"><span class="pre">LDR</span></code>) and then insert another <code class="docutils literal"><span class="pre">REV</span></code> to change the representation to be as if it had been loaded by an <code class="docutils literal"><span class="pre">LD1</span></code> of type <code class="docutils literal"><span class="pre">Y</span></code>.</p>
+<p>For the previous example, this would be:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">LD1</span>   <span class="n">v0</span><span class="o">.</span><span class="mi">4</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">x</span><span class="p">]</span>
+
+<span class="n">REV64</span> <span class="n">v0</span><span class="o">.</span><span class="mi">4</span><span class="n">s</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">4</span><span class="n">s</span>                  <span class="o">//</span> <span class="n">There</span> <span class="ow">is</span> <span class="n">no</span> <span class="n">REV128</span> <span class="n">instruction</span><span class="p">,</span> <span class="n">so</span> <span class="n">it</span> <span class="n">must</span> <span class="n">be</span> <span class="n">synthesizedcd</span>
+<span class="n">EXT</span>   <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="c1">#8    // with a REV64 then an EXT to swap the two 64-bit elements.</span>
+
+<span class="n">REV64</span> <span class="n">v0</span><span class="o">.</span><span class="mi">2</span><span class="n">d</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">2</span><span class="n">d</span>
+<span class="n">EXT</span>   <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="c1">#8</span>
+
+<span class="n">ST1</span>   <span class="n">v0</span><span class="o">.</span><span class="mi">2</span><span class="n">d</span><span class="p">,</span> <span class="p">[</span><span class="n">y</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>It turns out that these <code class="docutils literal"><span class="pre">REV</span></code> pairs can, in almost all cases, be squashed together into a single <code class="docutils literal"><span class="pre">REV</span></code>. For the example above, a <code class="docutils literal"><span class="pre">REV128</span> <span class="pre">4s</span></code> + <code class="docutils literal"><span class="pre">REV128</span> <span class="pre">2d</span></code> is actually a <code class="docutils literal"><span class="pre">REV64</span> <span class="pre">4s</span></code>, as shown in the figure on the right.</p>
+<table class="docutils footnote" frame="void" id="id2" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id1">[1]</a></td><td>One lane vectors may seem useless as a concept but they serve to distinguish between values held in general purpose registers and values held in NEON/VFP registers. For example, an <code class="docutils literal"><span class="pre">i64</span></code> would live in an <code class="docutils literal"><span class="pre">x</span></code> register, but <code class="docutils literal"><span class="pre"><1</span> <span class="pre">x</span> <span class="pre">i64></span></code> would live in a <code class="docutils literal"><span class="pre">d</span></code> register.</td></tr>
+</tbody>
+</table>
+</div>
+</div>
+</div>
+
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+  <div class="section" id="llvm-bitcode-file-format">
+<h1>LLVM Bitcode File Format<a class="headerlink" href="#llvm-bitcode-file-format" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#abstract" id="id9">Abstract</a></li>
+<li><a class="reference internal" href="#overview" id="id10">Overview</a></li>
+<li><a class="reference internal" href="#bitstream-format" id="id11">Bitstream Format</a><ul>
+<li><a class="reference internal" href="#magic-numbers" id="id12">Magic Numbers</a></li>
+<li><a class="reference internal" href="#primitives" id="id13">Primitives</a><ul>
+<li><a class="reference internal" href="#fixed-width-value" id="id14">Fixed Width Integers</a></li>
+<li><a class="reference internal" href="#variable-width-value" id="id15">Variable Width Integers</a></li>
+<li><a class="reference internal" href="#bit-characters" id="id16">6-bit characters</a></li>
+<li><a class="reference internal" href="#word-alignment" id="id17">Word Alignment</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#abbreviation-ids" id="id18">Abbreviation IDs</a></li>
+<li><a class="reference internal" href="#blocks" id="id19">Blocks</a><ul>
+<li><a class="reference internal" href="#enter-subblock-encoding" id="id20">ENTER_SUBBLOCK Encoding</a></li>
+<li><a class="reference internal" href="#end-block-encoding" id="id21">END_BLOCK Encoding</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#data-records" id="id22">Data Records</a><ul>
+<li><a class="reference internal" href="#unabbrev-record-encoding" id="id23">UNABBREV_RECORD Encoding</a></li>
+<li><a class="reference internal" href="#abbreviated-record-encoding" id="id24">Abbreviated Record Encoding</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#abbreviations" id="id25">Abbreviations</a><ul>
+<li><a class="reference internal" href="#define-abbrev-encoding" id="id26">DEFINE_ABBREV Encoding</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#standard-block" id="id27">Standard Blocks</a><ul>
+<li><a class="reference internal" href="#blockinfo-block" id="id28">#0 - BLOCKINFO Block</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#bitcode-wrapper-format" id="id29">Bitcode Wrapper Format</a></li>
+<li><a class="reference internal" href="#native-object-file-wrapper-format" id="id30">Native Object File Wrapper Format</a></li>
+<li><a class="reference internal" href="#llvm-ir-encoding" id="id31">LLVM IR Encoding</a><ul>
+<li><a class="reference internal" href="#basics" id="id32">Basics</a><ul>
+<li><a class="reference internal" href="#llvm-ir-magic-number" id="id33">LLVM IR Magic Number</a></li>
+<li><a class="reference internal" href="#signed-vbrs" id="id34">Signed VBRs</a></li>
+<li><a class="reference internal" href="#llvm-ir-blocks" id="id35">LLVM IR Blocks</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#module-block-contents" id="id36">MODULE_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#module-code-version-record" id="id37">MODULE_CODE_VERSION Record</a></li>
+<li><a class="reference internal" href="#module-code-triple-record" id="id38">MODULE_CODE_TRIPLE Record</a></li>
+<li><a class="reference internal" href="#module-code-datalayout-record" id="id39">MODULE_CODE_DATALAYOUT Record</a></li>
+<li><a class="reference internal" href="#module-code-asm-record" id="id40">MODULE_CODE_ASM Record</a></li>
+<li><a class="reference internal" href="#module-code-sectionname-record" id="id41">MODULE_CODE_SECTIONNAME Record</a></li>
+<li><a class="reference internal" href="#module-code-deplib-record" id="id42">MODULE_CODE_DEPLIB Record</a></li>
+<li><a class="reference internal" href="#module-code-globalvar-record" id="id43">MODULE_CODE_GLOBALVAR Record</a></li>
+<li><a class="reference internal" href="#module-code-function-record" id="id44">MODULE_CODE_FUNCTION Record</a></li>
+<li><a class="reference internal" href="#module-code-alias-record" id="id45">MODULE_CODE_ALIAS Record</a></li>
+<li><a class="reference internal" href="#module-code-gcname-record" id="id46">MODULE_CODE_GCNAME Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#paramattr-block-contents" id="id47">PARAMATTR_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#paramattr-code-entry-record" id="id48">PARAMATTR_CODE_ENTRY Record</a></li>
+<li><a class="reference internal" href="#paramattr-code-entry-old-record" id="id49">PARAMATTR_CODE_ENTRY_OLD Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#paramattr-group-block-contents" id="id50">PARAMATTR_GROUP_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#paramattr-grp-code-entry-record" id="id51">PARAMATTR_GRP_CODE_ENTRY Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#type-block-contents" id="id52">TYPE_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#type-code-numentry-record" id="id53">TYPE_CODE_NUMENTRY Record</a></li>
+<li><a class="reference internal" href="#type-code-void-record" id="id54">TYPE_CODE_VOID Record</a></li>
+<li><a class="reference internal" href="#type-code-half-record" id="id55">TYPE_CODE_HALF Record</a></li>
+<li><a class="reference internal" href="#type-code-float-record" id="id56">TYPE_CODE_FLOAT Record</a></li>
+<li><a class="reference internal" href="#type-code-double-record" id="id57">TYPE_CODE_DOUBLE Record</a></li>
+<li><a class="reference internal" href="#type-code-label-record" id="id58">TYPE_CODE_LABEL Record</a></li>
+<li><a class="reference internal" href="#type-code-opaque-record" id="id59">TYPE_CODE_OPAQUE Record</a></li>
+<li><a class="reference internal" href="#type-code-integer-record" id="id60">TYPE_CODE_INTEGER Record</a></li>
+<li><a class="reference internal" href="#type-code-pointer-record" id="id61">TYPE_CODE_POINTER Record</a></li>
+<li><a class="reference internal" href="#type-code-function-old-record" id="id62">TYPE_CODE_FUNCTION_OLD Record</a></li>
+<li><a class="reference internal" href="#type-code-array-record" id="id63">TYPE_CODE_ARRAY Record</a></li>
+<li><a class="reference internal" href="#type-code-vector-record" id="id64">TYPE_CODE_VECTOR Record</a></li>
+<li><a class="reference internal" href="#type-code-x86-fp80-record" id="id65">TYPE_CODE_X86_FP80 Record</a></li>
+<li><a class="reference internal" href="#type-code-fp128-record" id="id66">TYPE_CODE_FP128 Record</a></li>
+<li><a class="reference internal" href="#type-code-ppc-fp128-record" id="id67">TYPE_CODE_PPC_FP128 Record</a></li>
+<li><a class="reference internal" href="#type-code-metadata-record" id="id68">TYPE_CODE_METADATA Record</a></li>
+<li><a class="reference internal" href="#type-code-x86-mmx-record" id="id69">TYPE_CODE_X86_MMX Record</a></li>
+<li><a class="reference internal" href="#type-code-struct-anon-record" id="id70">TYPE_CODE_STRUCT_ANON Record</a></li>
+<li><a class="reference internal" href="#type-code-struct-name-record" id="id71">TYPE_CODE_STRUCT_NAME Record</a></li>
+<li><a class="reference internal" href="#type-code-struct-named-record" id="id72">TYPE_CODE_STRUCT_NAMED Record</a></li>
+<li><a class="reference internal" href="#type-code-function-record" id="id73">TYPE_CODE_FUNCTION Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#constants-block-contents" id="id74">CONSTANTS_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#function-block-contents" id="id75">FUNCTION_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#value-symtab-block-contents" id="id76">VALUE_SYMTAB_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#metadata-block-contents" id="id77">METADATA_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#metadata-attachment-contents" id="id78">METADATA_ATTACHMENT Contents</a></li>
+<li><a class="reference internal" href="#strtab-block-contents" id="id79">STRTAB_BLOCK Contents</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="abstract">
+<h2><a class="toc-backref" href="#id9">Abstract</a><a class="headerlink" href="#abstract" title="Permalink to this headline">¶</a></h2>
+<p>This document describes the LLVM bitstream file format and the encoding of the
+LLVM IR into it.</p>
+</div>
+<div class="section" id="overview">
+<h2><a class="toc-backref" href="#id10">Overview</a><a class="headerlink" href="#overview" title="Permalink to this headline">¶</a></h2>
+<p>What is commonly known as the LLVM bitcode file format (also, sometimes
+anachronistically known as bytecode) is actually two things: a <a class="reference internal" href="#bitstream-container-format">bitstream
+container format</a> and an <a class="reference internal" href="#encoding-of-llvm-ir">encoding of LLVM IR</a> into the container format.</p>
+<p>The bitstream format is an abstract encoding of structured data, very similar to
+XML in some ways.  Like XML, bitstream files contain tags, and nested
+structures, and you can parse the file without having to understand the tags.
+Unlike XML, the bitstream format is a binary encoding, and unlike XML it
+provides a mechanism for the file to self-describe “abbreviations”, which are
+effectively size optimizations for the content.</p>
+<p>LLVM IR files may be optionally embedded into a <a class="reference internal" href="#wrapper">wrapper</a> structure, or in a
+<a class="reference internal" href="#native-object-file">native object file</a>. Both of these mechanisms make it easy to embed extra
+data along with LLVM IR files.</p>
+<p>This document first describes the LLVM bitstream format, describes the wrapper
+format, then describes the record structure used by LLVM IR files.</p>
+</div>
+<div class="section" id="bitstream-format">
+<span id="bitstream-container-format"></span><h2><a class="toc-backref" href="#id11">Bitstream Format</a><a class="headerlink" href="#bitstream-format" title="Permalink to this headline">¶</a></h2>
+<p>The bitstream format is literally a stream of bits, with a very simple
+structure.  This structure consists of the following concepts:</p>
+<ul class="simple">
+<li>A “<a class="reference internal" href="#magic-number">magic number</a>” that identifies the contents of the stream.</li>
+<li>Encoding <a class="reference internal" href="#primitives">primitives</a> like variable bit-rate integers.</li>
+<li><a class="reference internal" href="#blocks">Blocks</a>, which define nested content.</li>
+<li><a class="reference internal" href="#data-records">Data Records</a>, which describe entities within the file.</li>
+<li>Abbreviations, which specify compression optimizations for the file.</li>
+</ul>
+<p>Note that the <a class="reference internal" href="CommandGuide/llvm-bcanalyzer.html"><span class="doc">llvm-bcanalyzer</span></a> tool can be
+used to dump and inspect arbitrary bitstreams, which is very useful for
+understanding the encoding.</p>
+<div class="section" id="magic-numbers">
+<span id="magic-number"></span><h3><a class="toc-backref" href="#id12">Magic Numbers</a><a class="headerlink" href="#magic-numbers" title="Permalink to this headline">¶</a></h3>
+<p>The first two bytes of a bitcode file are ‘BC’ (<code class="docutils literal"><span class="pre">0x42</span></code>, <code class="docutils literal"><span class="pre">0x43</span></code>).  The second
+two bytes are an application-specific magic number.  Generic bitcode tools can
+look at only the first two bytes to verify the file is bitcode, while
+application-specific programs will want to look at all four.</p>
+</div>
+<div class="section" id="primitives">
+<span id="id1"></span><h3><a class="toc-backref" href="#id13">Primitives</a><a class="headerlink" href="#primitives" title="Permalink to this headline">¶</a></h3>
+<p>A bitstream literally consists of a stream of bits, which are read in order
+starting with the least significant bit of each byte.  The stream is made up of
+a number of primitive values that encode a stream of unsigned integer values.
+These integers are encoded in two ways: either as <a class="reference internal" href="#fixed-width-integers">Fixed Width Integers</a> or as
+<a class="reference internal" href="#variable-width-integers">Variable Width Integers</a>.</p>
+<div class="section" id="fixed-width-value">
+<span id="fixed-width-integers"></span><span id="id2"></span><h4><a class="toc-backref" href="#id14">Fixed Width Integers</a><a class="headerlink" href="#fixed-width-value" title="Permalink to this headline">¶</a></h4>
+<p>Fixed-width integer values have their low bits emitted directly to the file.
+For example, a 3-bit integer value encodes 1 as 001.  Fixed width integers are
+used when there are a well-known number of options for a field.  For example,
+boolean values are usually encoded with a 1-bit wide integer.</p>
+</div>
+<div class="section" id="variable-width-value">
+<span id="variable-width-integer"></span><span id="variable-width-integers"></span><span id="id3"></span><h4><a class="toc-backref" href="#id15">Variable Width Integers</a><a class="headerlink" href="#variable-width-value" title="Permalink to this headline">¶</a></h4>
+<p>Variable-width integer (VBR) values encode values of arbitrary size, optimizing
+for the case where the values are small.  Given a 4-bit VBR field, any 3-bit
+value (0 through 7) is encoded directly, with the high bit set to zero.  Values
+larger than N-1 bits emit their bits in a series of N-1 bit chunks, where all
+but the last set the high bit.</p>
+<p>For example, the value 27 (0x1B) is encoded as 1011 0011 when emitted as a vbr4
+value.  The first set of four bits indicates the value 3 (011) with a
+continuation piece (indicated by a high bit of 1).  The next word indicates a
+value of 24 (011 << 3) with no continuation.  The sum (3+24) yields the value
+27.</p>
+</div>
+<div class="section" id="bit-characters">
+<span id="char6-encoded-value"></span><h4><a class="toc-backref" href="#id16">6-bit characters</a><a class="headerlink" href="#bit-characters" title="Permalink to this headline">¶</a></h4>
+<p>6-bit characters encode common characters into a fixed 6-bit field.  They
+represent the following characters with the following 6-bit values:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="s1">'a'</span> <span class="o">..</span> <span class="s1">'z'</span> <span class="o">---</span>  <span class="mi">0</span> <span class="o">..</span> <span class="mi">25</span>
+<span class="s1">'A'</span> <span class="o">..</span> <span class="s1">'Z'</span> <span class="o">---</span> <span class="mi">26</span> <span class="o">..</span> <span class="mi">51</span>
+<span class="s1">'0'</span> <span class="o">..</span> <span class="s1">'9'</span> <span class="o">---</span> <span class="mi">52</span> <span class="o">..</span> <span class="mi">61</span>
+       <span class="s1">'.'</span> <span class="o">---</span> <span class="mi">62</span>
+       <span class="s1">'_'</span> <span class="o">---</span> <span class="mi">63</span>
+</pre></div>
+</div>
+<p>This encoding is only suitable for encoding characters and strings that consist
+only of the above characters.  It is completely incapable of encoding characters
+not in the set.</p>
+</div>
+<div class="section" id="word-alignment">
+<h4><a class="toc-backref" href="#id17">Word Alignment</a><a class="headerlink" href="#word-alignment" title="Permalink to this headline">¶</a></h4>
+<p>Occasionally, it is useful to emit zero bits until the bitstream is a multiple
+of 32 bits.  This ensures that the bit position in the stream can be represented
+as a multiple of 32-bit words.</p>
+</div>
+</div>
+<div class="section" id="abbreviation-ids">
+<h3><a class="toc-backref" href="#id18">Abbreviation IDs</a><a class="headerlink" href="#abbreviation-ids" title="Permalink to this headline">¶</a></h3>
+<p>A bitstream is a sequential series of <a class="reference internal" href="#blocks">Blocks</a> and <a class="reference internal" href="#data-records">Data Records</a>.  Both of
+these start with an abbreviation ID encoded as a fixed-bitwidth field.  The
+width is specified by the current block, as described below.  The value of the
+abbreviation ID specifies either a builtin ID (which have special meanings,
+defined below) or one of the abbreviation IDs defined for the current block by
+the stream itself.</p>
+<p>The set of builtin abbrev IDs is:</p>
+<ul class="simple">
+<li>0 - <a class="reference internal" href="#end-block">END_BLOCK</a> — This abbrev ID marks the end of the current block.</li>
+<li>1 - <a class="reference internal" href="#enter-subblock">ENTER_SUBBLOCK</a> — This abbrev ID marks the beginning of a new
+block.</li>
+<li>2 - <a class="reference internal" href="#define-abbrev">DEFINE_ABBREV</a> — This defines a new abbreviation.</li>
+<li>3 - <a class="reference internal" href="#unabbrev-record">UNABBREV_RECORD</a> — This ID specifies the definition of an
+unabbreviated record.</li>
+</ul>
+<p>Abbreviation IDs 4 and above are defined by the stream itself, and specify an
+<a class="reference internal" href="#abbreviated-record-encoding">abbreviated record encoding</a>.</p>
+</div>
+<div class="section" id="blocks">
+<span id="id4"></span><h3><a class="toc-backref" href="#id19">Blocks</a><a class="headerlink" href="#blocks" title="Permalink to this headline">¶</a></h3>
+<p>Blocks in a bitstream denote nested regions of the stream, and are identified by
+a content-specific id number (for example, LLVM IR uses an ID of 12 to represent
+function bodies).  Block IDs 0-7 are reserved for <a class="reference internal" href="#standard-blocks">standard blocks</a> whose
+meaning is defined by Bitcode; block IDs 8 and greater are application
+specific. Nested blocks capture the hierarchical structure of the data encoded
+in it, and various properties are associated with blocks as the file is parsed.
+Block definitions allow the reader to efficiently skip blocks in constant time
+if the reader wants a summary of blocks, or if it wants to efficiently skip data
+it does not understand.  The LLVM IR reader uses this mechanism to skip function
+bodies, lazily reading them on demand.</p>
+<p>When reading and encoding the stream, several properties are maintained for the
+block.  In particular, each block maintains:</p>
+<ol class="arabic simple">
+<li>A current abbrev id width.  This value starts at 2 at the beginning of the
+stream, and is set every time a block record is entered.  The block entry
+specifies the abbrev id width for the body of the block.</li>
+<li>A set of abbreviations.  Abbreviations may be defined within a block, in
+which case they are only defined in that block (neither subblocks nor
+enclosing blocks see the abbreviation).  Abbreviations can also be defined
+inside a <a class="reference internal" href="#blockinfo">BLOCKINFO</a> block, in which case they are defined in all blocks
+that match the ID that the <code class="docutils literal"><span class="pre">BLOCKINFO</span></code> block is describing.</li>
+</ol>
+<p>As sub blocks are entered, these properties are saved and the new sub-block has
+its own set of abbreviations, and its own abbrev id width.  When a sub-block is
+popped, the saved values are restored.</p>
+<div class="section" id="enter-subblock-encoding">
+<span id="enter-subblock"></span><h4><a class="toc-backref" href="#id20">ENTER_SUBBLOCK Encoding</a><a class="headerlink" href="#enter-subblock-encoding" title="Permalink to this headline">¶</a></h4>
+<p><span class="raw-html"><tt></span>
+[ENTER_SUBBLOCK, blockid<sub>vbr8</sub>, newabbrevlen<sub>vbr4</sub>, <align32bits>, blocklen_32]
+<span class="raw-html"></tt></span></p>
+<p>The <code class="docutils literal"><span class="pre">ENTER_SUBBLOCK</span></code> abbreviation ID specifies the start of a new block
+record.  The <code class="docutils literal"><span class="pre">blockid</span></code> value is encoded as an 8-bit VBR identifier, and
+indicates the type of block being entered, which can be a <a class="reference internal" href="#standard-block">standard block</a> or
+an application-specific block.  The <code class="docutils literal"><span class="pre">newabbrevlen</span></code> value is a 4-bit VBR, which
+specifies the abbrev id width for the sub-block.  The <code class="docutils literal"><span class="pre">blocklen</span></code> value is a
+32-bit aligned value that specifies the size of the subblock in 32-bit
+words. This value allows the reader to skip over the entire block in one jump.</p>
+</div>
+<div class="section" id="end-block-encoding">
+<span id="end-block"></span><h4><a class="toc-backref" href="#id21">END_BLOCK Encoding</a><a class="headerlink" href="#end-block-encoding" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[END_BLOCK,</span> <span class="pre"><align32bits>]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">END_BLOCK</span></code> abbreviation ID specifies the end of the current block record.
+Its end is aligned to 32-bits to ensure that the size of the block is an even
+multiple of 32-bits.</p>
+</div>
+</div>
+<div class="section" id="data-records">
+<span id="id5"></span><h3><a class="toc-backref" href="#id22">Data Records</a><a class="headerlink" href="#data-records" title="Permalink to this headline">¶</a></h3>
+<p>Data records consist of a record code and a number of (up to) 64-bit integer
+values.  The interpretation of the code and values is application specific and
+may vary between different block types.  Records can be encoded either using an
+unabbrev record, or with an abbreviation.  In the LLVM IR format, for example,
+there is a record which encodes the target triple of a module.  The code is
+<code class="docutils literal"><span class="pre">MODULE_CODE_TRIPLE</span></code>, and the values of the record are the ASCII codes for the
+characters in the string.</p>
+<div class="section" id="unabbrev-record-encoding">
+<span id="unabbrev-record"></span><h4><a class="toc-backref" href="#id23">UNABBREV_RECORD Encoding</a><a class="headerlink" href="#unabbrev-record-encoding" title="Permalink to this headline">¶</a></h4>
+<p><span class="raw-html"><tt></span>
+[UNABBREV_RECORD, code<sub>vbr6</sub>, numops<sub>vbr6</sub>, op0<sub>vbr6</sub>, op1<sub>vbr6</sub>, ...]
+<span class="raw-html"></tt></span></p>
+<p>An <code class="docutils literal"><span class="pre">UNABBREV_RECORD</span></code> provides a default fallback encoding, which is both
+completely general and extremely inefficient.  It can describe an arbitrary
+record by emitting the code and operands as VBRs.</p>
+<p>For example, emitting an LLVM IR target triple as an unabbreviated record
+requires emitting the <code class="docutils literal"><span class="pre">UNABBREV_RECORD</span></code> abbrevid, a vbr6 for the
+<code class="docutils literal"><span class="pre">MODULE_CODE_TRIPLE</span></code> code, a vbr6 for the length of the string, which is equal
+to the number of operands, and a vbr6 for each character.  Because there are no
+letters with values less than 32, each letter would need to be emitted as at
+least a two-part VBR, which means that each letter would require at least 12
+bits.  This is not an efficient encoding, but it is fully general.</p>
+</div>
+<div class="section" id="abbreviated-record-encoding">
+<span id="id6"></span><h4><a class="toc-backref" href="#id24">Abbreviated Record Encoding</a><a class="headerlink" href="#abbreviated-record-encoding" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[<abbrevid>,</span> <span class="pre">fields...]</span></code></p>
+<p>An abbreviated record is a abbreviation id followed by a set of fields that are
+encoded according to the <a class="reference internal" href="#abbreviation-definition">abbreviation definition</a>.  This allows records to be
+encoded significantly more densely than records encoded with the
+<a class="reference internal" href="#unabbrev-record">UNABBREV_RECORD</a> type, and allows the abbreviation types to be specified in
+the stream itself, which allows the files to be completely self describing.  The
+actual encoding of abbreviations is defined below.</p>
+<p>The record code, which is the first field of an abbreviated record, may be
+encoded in the abbreviation definition (as a literal operand) or supplied in the
+abbreviated record (as a Fixed or VBR operand value).</p>
+</div>
+</div>
+<div class="section" id="abbreviations">
+<span id="abbreviation-definition"></span><h3><a class="toc-backref" href="#id25">Abbreviations</a><a class="headerlink" href="#abbreviations" title="Permalink to this headline">¶</a></h3>
+<p>Abbreviations are an important form of compression for bitstreams.  The idea is
+to specify a dense encoding for a class of records once, then use that encoding
+to emit many records.  It takes space to emit the encoding into the file, but
+the space is recouped (hopefully plus some) when the records that use it are
+emitted.</p>
+<p>Abbreviations can be determined dynamically per client, per file. Because the
+abbreviations are stored in the bitstream itself, different streams of the same
+format can contain different sets of abbreviations according to the needs of the
+specific stream.  As a concrete example, LLVM IR files usually emit an
+abbreviation for binary operators.  If a specific LLVM module contained no or
+few binary operators, the abbreviation does not need to be emitted.</p>
+<div class="section" id="define-abbrev-encoding">
+<span id="define-abbrev"></span><h4><a class="toc-backref" href="#id26">DEFINE_ABBREV Encoding</a><a class="headerlink" href="#define-abbrev-encoding" title="Permalink to this headline">¶</a></h4>
+<p><span class="raw-html"><tt></span>
+[DEFINE_ABBREV, numabbrevops<sub>vbr5</sub>, abbrevop0, abbrevop1, ...]
+<span class="raw-html"></tt></span></p>
+<p>A <code class="docutils literal"><span class="pre">DEFINE_ABBREV</span></code> record adds an abbreviation to the list of currently defined
+abbreviations in the scope of this block.  This definition only exists inside
+this immediate block — it is not visible in subblocks or enclosing blocks.
+Abbreviations are implicitly assigned IDs sequentially starting from 4 (the
+first application-defined abbreviation ID).  Any abbreviations defined in a
+<code class="docutils literal"><span class="pre">BLOCKINFO</span></code> record for the particular block type receive IDs first, in order,
+followed by any abbreviations defined within the block itself.  Abbreviated data
+records reference this ID to indicate what abbreviation they are invoking.</p>
+<p>An abbreviation definition consists of the <code class="docutils literal"><span class="pre">DEFINE_ABBREV</span></code> abbrevid followed
+by a VBR that specifies the number of abbrev operands, then the abbrev operands
+themselves.  Abbreviation operands come in three forms.  They all start with a
+single bit that indicates whether the abbrev operand is a literal operand (when
+the bit is 1) or an encoding operand (when the bit is 0).</p>
+<ol class="arabic simple">
+<li>Literal operands — <span class="raw-html"><tt></span> [1<sub>1</sub>, litvalue<sub>vbr8</sub>] <span class="raw-html"></tt></span> — Literal operands specify that the value in
+the result is always a single specific value.  This specific value is emitted
+as a vbr8 after the bit indicating that it is a literal operand.</li>
+<li>Encoding info without data — <span class="raw-html"><tt></span> [0<sub>1</sub>, encoding<sub>3</sub>] <span class="raw-html"></tt></span> — Operand encodings that do not have extra data
+are just emitted as their code.</li>
+<li>Encoding info with data — <span class="raw-html"><tt></span> [0<sub>1</sub>, encoding<sub>3</sub>, value<sub>vbr5</sub>] <span class="raw-html"></tt></span> — Operand encodings that do
+have extra data are emitted as their code, followed by the extra data.</li>
+</ol>
+<p>The possible operand encodings are:</p>
+<ul class="simple">
+<li>Fixed (code 1): The field should be emitted as a <a class="reference internal" href="#fixed-width-value">fixed-width value</a>, whose
+width is specified by the operand’s extra data.</li>
+<li>VBR (code 2): The field should be emitted as a <a class="reference internal" href="#variable-width-value">variable-width value</a>, whose
+width is specified by the operand’s extra data.</li>
+<li>Array (code 3): This field is an array of values.  The array operand has no
+extra data, but expects another operand to follow it, indicating the element
+type of the array.  When reading an array in an abbreviated record, the first
+integer is a vbr6 that indicates the array length, followed by the encoded
+elements of the array.  An array may only occur as the last operand of an
+abbreviation (except for the one final operand that gives the array’s
+type).</li>
+<li>Char6 (code 4): This field should be emitted as a <a class="reference internal" href="#char6-encoded-value">char6-encoded value</a>.
+This operand type takes no extra data. Char6 encoding is normally used as an
+array element type.</li>
+<li>Blob (code 5): This field is emitted as a vbr6, followed by padding to a
+32-bit boundary (for alignment) and an array of 8-bit objects.  The array of
+bytes is further followed by tail padding to ensure that its total length is a
+multiple of 4 bytes.  This makes it very efficient for the reader to decode
+the data without having to make a copy of it: it can use a pointer to the data
+in the mapped in file and poke directly at it.  A blob may only occur as the
+last operand of an abbreviation.</li>
+</ul>
+<p>For example, target triples in LLVM modules are encoded as a record of the form
+<code class="docutils literal"><span class="pre">[TRIPLE,</span> <span class="pre">'a',</span> <span class="pre">'b',</span> <span class="pre">'c',</span> <span class="pre">'d']</span></code>.  Consider if the bitstream emitted the
+following abbrev entry:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">Fixed</span><span class="p">,</span> <span class="mi">4</span><span class="p">]</span>
+<span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">Array</span><span class="p">]</span>
+<span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">Char6</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>When emitting a record with this abbreviation, the above entry would be emitted
+as:</p>
+<p><span class="raw-html"><tt><blockquote></span>
+[4<sub>abbrevwidth</sub>, 2<sub>4</sub>, 4<sub>vbr6</sub>, 0<sub>6</sub>, 1<sub>6</sub>, 2<sub>6</sub>, 3<sub>6</sub>]
+<span class="raw-html"></blockquote></tt></span></p>
+<p>These values are:</p>
+<ol class="arabic simple">
+<li>The first value, 4, is the abbreviation ID for this abbreviation.</li>
+<li>The second value, 2, is the record code for <code class="docutils literal"><span class="pre">TRIPLE</span></code> records within LLVM IR
+file <code class="docutils literal"><span class="pre">MODULE_BLOCK</span></code> blocks.</li>
+<li>The third value, 4, is the length of the array.</li>
+<li>The rest of the values are the char6 encoded values for <code class="docutils literal"><span class="pre">"abcd"</span></code>.</li>
+</ol>
+<p>With this abbreviation, the triple is emitted with only 37 bits (assuming a
+abbrev id width of 3).  Without the abbreviation, significantly more space would
+be required to emit the target triple.  Also, because the <code class="docutils literal"><span class="pre">TRIPLE</span></code> value is
+not emitted as a literal in the abbreviation, the abbreviation can also be used
+for any other string value.</p>
+</div>
+</div>
+<div class="section" id="standard-block">
+<span id="standard-blocks"></span><span id="id7"></span><h3><a class="toc-backref" href="#id27">Standard Blocks</a><a class="headerlink" href="#standard-block" title="Permalink to this headline">¶</a></h3>
+<p>In addition to the basic block structure and record encodings, the bitstream
+also defines specific built-in block types.  These block types specify how the
+stream is to be decoded or other metadata.  In the future, new standard blocks
+may be added.  Block IDs 0-7 are reserved for standard blocks.</p>
+<div class="section" id="blockinfo-block">
+<span id="blockinfo"></span><h4><a class="toc-backref" href="#id28">#0 - BLOCKINFO Block</a><a class="headerlink" href="#blockinfo-block" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal"><span class="pre">BLOCKINFO</span></code> block allows the description of metadata for other blocks.
+The currently specified records are:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="p">[</span><span class="n">SETBID</span> <span class="p">(</span><span class="c1">#1), blockid]</span>
+<span class="p">[</span><span class="n">DEFINE_ABBREV</span><span class="p">,</span> <span class="o">...</span><span class="p">]</span>
+<span class="p">[</span><span class="n">BLOCKNAME</span><span class="p">,</span> <span class="o">...</span><span class="n">name</span><span class="o">...</span><span class="p">]</span>
+<span class="p">[</span><span class="n">SETRECORDNAME</span><span class="p">,</span> <span class="n">RecordID</span><span class="p">,</span> <span class="o">...</span><span class="n">name</span><span class="o">...</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>The <code class="docutils literal"><span class="pre">SETBID</span></code> record (code 1) indicates which block ID is being described.
+<code class="docutils literal"><span class="pre">SETBID</span></code> records can occur multiple times throughout the block to change which
+block ID is being described.  There must be a <code class="docutils literal"><span class="pre">SETBID</span></code> record prior to any
+other records.</p>
+<p>Standard <code class="docutils literal"><span class="pre">DEFINE_ABBREV</span></code> records can occur inside <code class="docutils literal"><span class="pre">BLOCKINFO</span></code> blocks, but
+unlike their occurrence in normal blocks, the abbreviation is defined for blocks
+matching the block ID we are describing, <em>not</em> the <code class="docutils literal"><span class="pre">BLOCKINFO</span></code> block
+itself.  The abbreviations defined in <code class="docutils literal"><span class="pre">BLOCKINFO</span></code> blocks receive abbreviation
+IDs as described in <a class="reference internal" href="#define-abbrev">DEFINE_ABBREV</a>.</p>
+<p>The <code class="docutils literal"><span class="pre">BLOCKNAME</span></code> record (code 2) can optionally occur in this block.  The
+elements of the record are the bytes of the string name of the block.
+llvm-bcanalyzer can use this to dump out bitcode files symbolically.</p>
+<p>The <code class="docutils literal"><span class="pre">SETRECORDNAME</span></code> record (code 3) can also optionally occur in this block.
+The first operand value is a record ID number, and the rest of the elements of
+the record are the bytes for the string name of the record.  llvm-bcanalyzer can
+use this to dump out bitcode files symbolically.</p>
+<p>Note that although the data in <code class="docutils literal"><span class="pre">BLOCKINFO</span></code> blocks is described as “metadata,”
+the abbreviations they contain are essential for parsing records from the
+corresponding blocks.  It is not safe to skip them.</p>
+</div>
+</div>
+</div>
+<div class="section" id="bitcode-wrapper-format">
+<span id="wrapper"></span><h2><a class="toc-backref" href="#id29">Bitcode Wrapper Format</a><a class="headerlink" href="#bitcode-wrapper-format" title="Permalink to this headline">¶</a></h2>
+<p>Bitcode files for LLVM IR may optionally be wrapped in a simple wrapper
+structure.  This structure contains a simple header that indicates the offset
+and size of the embedded BC file.  This allows additional information to be
+stored alongside the BC file.  The structure of this file header is:</p>
+<p><span class="raw-html"><tt><blockquote></span>
+[Magic<sub>32</sub>, Version<sub>32</sub>, Offset<sub>32</sub>, Size<sub>32</sub>, CPUType<sub>32</sub>]
+<span class="raw-html"></blockquote></tt></span></p>
+<p>Each of the fields are 32-bit fields stored in little endian form (as with the
+rest of the bitcode file fields).  The Magic number is always <code class="docutils literal"><span class="pre">0x0B17C0DE</span></code> and
+the version is currently always <code class="docutils literal"><span class="pre">0</span></code>.  The Offset field is the offset in bytes
+to the start of the bitcode stream in the file, and the Size field is the size
+in bytes of the stream. CPUType is a target-specific value that can be used to
+encode the CPU of the target.</p>
+</div>
+<div class="section" id="native-object-file-wrapper-format">
+<span id="native-object-file"></span><h2><a class="toc-backref" href="#id30">Native Object File Wrapper Format</a><a class="headerlink" href="#native-object-file-wrapper-format" title="Permalink to this headline">¶</a></h2>
+<p>Bitcode files for LLVM IR may also be wrapped in a native object file
+(i.e. ELF, COFF, Mach-O).  The bitcode must be stored in a section of the object
+file named <code class="docutils literal"><span class="pre">__LLVM,__bitcode</span></code> for MachO and <code class="docutils literal"><span class="pre">.llvmbc</span></code> for the other object
+formats.  This wrapper format is useful for accommodating LTO in compilation
+pipelines where intermediate objects must be native object files which contain
+metadata in other sections.</p>
+<p>Not all tools support this format.</p>
+</div>
+<div class="section" id="llvm-ir-encoding">
+<span id="encoding-of-llvm-ir"></span><h2><a class="toc-backref" href="#id31">LLVM IR Encoding</a><a class="headerlink" href="#llvm-ir-encoding" title="Permalink to this headline">¶</a></h2>
+<p>LLVM IR is encoded into a bitstream by defining blocks and records.  It uses
+blocks for things like constant pools, functions, symbol tables, etc.  It uses
+records for things like instructions, global variable descriptors, type
+descriptions, etc.  This document does not describe the set of abbreviations
+that the writer uses, as these are fully self-described in the file, and the
+reader is not allowed to build in any knowledge of this.</p>
+<div class="section" id="basics">
+<h3><a class="toc-backref" href="#id32">Basics</a><a class="headerlink" href="#basics" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="llvm-ir-magic-number">
+<h4><a class="toc-backref" href="#id33">LLVM IR Magic Number</a><a class="headerlink" href="#llvm-ir-magic-number" title="Permalink to this headline">¶</a></h4>
+<p>The magic number for LLVM IR files is:</p>
+<p><span class="raw-html"><tt><blockquote></span>
+[0x0<sub>4</sub>, 0xC<sub>4</sub>, 0xE<sub>4</sub>, 0xD<sub>4</sub>]
+<span class="raw-html"></blockquote></tt></span></p>
+<p>When combined with the bitcode magic number and viewed as bytes, this is
+<code class="docutils literal"><span class="pre">"BC</span> <span class="pre">0xC0DE"</span></code>.</p>
+</div>
+<div class="section" id="signed-vbrs">
+<span id="id8"></span><h4><a class="toc-backref" href="#id34">Signed VBRs</a><a class="headerlink" href="#signed-vbrs" title="Permalink to this headline">¶</a></h4>
+<p><a class="reference internal" href="#variable-width-integer">Variable Width Integer</a> encoding is an efficient way to encode arbitrary sized
+unsigned values, but is an extremely inefficient for encoding signed values, as
+signed values are otherwise treated as maximally large unsigned values.</p>
+<p>As such, signed VBR values of a specific width are emitted as follows:</p>
+<ul class="simple">
+<li>Positive values are emitted as VBRs of the specified width, but with their
+value shifted left by one.</li>
+<li>Negative values are emitted as VBRs of the specified width, but the negated
+value is shifted left by one, and the low bit is set.</li>
+</ul>
+<p>With this encoding, small positive and small negative values can both be emitted
+efficiently. Signed VBR encoding is used in <code class="docutils literal"><span class="pre">CST_CODE_INTEGER</span></code> and
+<code class="docutils literal"><span class="pre">CST_CODE_WIDE_INTEGER</span></code> records within <code class="docutils literal"><span class="pre">CONSTANTS_BLOCK</span></code> blocks.
+It is also used for phi instruction operands in <a class="reference internal" href="#module-code-version">MODULE_CODE_VERSION</a> 1.</p>
+</div>
+<div class="section" id="llvm-ir-blocks">
+<h4><a class="toc-backref" href="#id35">LLVM IR Blocks</a><a class="headerlink" href="#llvm-ir-blocks" title="Permalink to this headline">¶</a></h4>
+<p>LLVM IR is defined with the following blocks:</p>
+<ul class="simple">
+<li>8 — <a class="reference internal" href="#module-block">MODULE_BLOCK</a> — This is the top-level block that contains the entire
+module, and describes a variety of per-module information.</li>
+<li>9 — <a class="reference internal" href="#paramattr-block">PARAMATTR_BLOCK</a> — This enumerates the parameter attributes.</li>
+<li>10 — <a class="reference internal" href="#paramattr-group-block">PARAMATTR_GROUP_BLOCK</a> — This describes the attribute group table.</li>
+<li>11 — <a class="reference internal" href="#constants-block">CONSTANTS_BLOCK</a> — This describes constants for a module or
+function.</li>
+<li>12 — <a class="reference internal" href="#function-block">FUNCTION_BLOCK</a> — This describes a function body.</li>
+<li>14 — <a class="reference internal" href="#value-symtab-block">VALUE_SYMTAB_BLOCK</a> — This describes a value symbol table.</li>
+<li>15 — <a class="reference internal" href="#metadata-block">METADATA_BLOCK</a> — This describes metadata items.</li>
+<li>16 — <a class="reference internal" href="#metadata-attachment">METADATA_ATTACHMENT</a> — This contains records associating metadata
+with function instruction values.</li>
+<li>17 — <a class="reference internal" href="#type-block">TYPE_BLOCK</a> — This describes all of the types in the module.</li>
+<li>23 — <a class="reference internal" href="#strtab-block">STRTAB_BLOCK</a> — The bitcode file’s string table.</li>
+</ul>
+</div>
+</div>
+<div class="section" id="module-block-contents">
+<span id="module-block"></span><h3><a class="toc-backref" href="#id36">MODULE_BLOCK Contents</a><a class="headerlink" href="#module-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">MODULE_BLOCK</span></code> block (id 8) is the top-level block for LLVM bitcode files,
+and each bitcode file must contain exactly one. In addition to records
+(described below) containing information about the module, a <code class="docutils literal"><span class="pre">MODULE_BLOCK</span></code>
+block may contain the following sub-blocks:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#blockinfo">BLOCKINFO</a></li>
+<li><a class="reference internal" href="#paramattr-block">PARAMATTR_BLOCK</a></li>
+<li><a class="reference internal" href="#paramattr-group-block">PARAMATTR_GROUP_BLOCK</a></li>
+<li><a class="reference internal" href="#type-block">TYPE_BLOCK</a></li>
+<li><a class="reference internal" href="#value-symtab-block">VALUE_SYMTAB_BLOCK</a></li>
+<li><a class="reference internal" href="#constants-block">CONSTANTS_BLOCK</a></li>
+<li><a class="reference internal" href="#function-block">FUNCTION_BLOCK</a></li>
+<li><a class="reference internal" href="#metadata-block">METADATA_BLOCK</a></li>
+</ul>
+<div class="section" id="module-code-version-record">
+<span id="module-code-version"></span><h4><a class="toc-backref" href="#id37">MODULE_CODE_VERSION Record</a><a class="headerlink" href="#module-code-version-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[VERSION,</span> <span class="pre">version#]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">VERSION</span></code> record (code 1) contains a single value indicating the format
+version. Versions 0, 1 and 2 are supported at this time. The difference between
+version 0 and 1 is in the encoding of instruction operands in
+each <a class="reference internal" href="#function-block">FUNCTION_BLOCK</a>.</p>
+<p>In version 0, each value defined by an instruction is assigned an ID
+unique to the function. Function-level value IDs are assigned starting from
+<code class="docutils literal"><span class="pre">NumModuleValues</span></code> since they share the same namespace as module-level
+values. The value enumerator resets after each function. When a value is
+an operand of an instruction, the value ID is used to represent the operand.
+For large functions or large modules, these operand values can be large.</p>
+<p>The encoding in version 1 attempts to avoid large operand values
+in common cases. Instead of using the value ID directly, operands are
+encoded as relative to the current instruction. Thus, if an operand
+is the value defined by the previous instruction, the operand
+will be encoded as 1.</p>
+<p>For example, instead of</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span>#n = load #n-1
+#n+1 = icmp eq #n, #const0
+br #n+1, label #(bb1), label #(bb2)
+</pre></div>
+</div>
+<p>version 1 will encode the instructions as</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span>#n = load #1
+#n+1 = icmp eq #1, (#n+1)-#const0
+br #1, label #(bb1), label #(bb2)
+</pre></div>
+</div>
+<p>Note in the example that operands which are constants also use
+the relative encoding, while operands like basic block labels
+do not use the relative encoding.</p>
+<p>Forward references will result in a negative value.
+This can be inefficient, as operands are normally encoded
+as unsigned VBRs. However, forward references are rare, except in the
+case of phi instructions. For phi instructions, operands are encoded as
+<a class="reference internal" href="#signed-vbrs">Signed VBRs</a> to deal with forward references.</p>
+<p>In version 2, the meaning of module records <code class="docutils literal"><span class="pre">FUNCTION</span></code>, <code class="docutils literal"><span class="pre">GLOBALVAR</span></code>,
+<code class="docutils literal"><span class="pre">ALIAS</span></code>, <code class="docutils literal"><span class="pre">IFUNC</span></code> and <code class="docutils literal"><span class="pre">COMDAT</span></code> change such that the first two operands
+specify an offset and size of a string in a string table (see <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK
+Contents</a>), the function name is removed from the <code class="docutils literal"><span class="pre">FNENTRY</span></code> record in the
+value symbol table, and the top-level <code class="docutils literal"><span class="pre">VALUE_SYMTAB_BLOCK</span></code> may only contain
+<code class="docutils literal"><span class="pre">FNENTRY</span></code> records.</p>
+</div>
+<div class="section" id="module-code-triple-record">
+<h4><a class="toc-backref" href="#id38">MODULE_CODE_TRIPLE Record</a><a class="headerlink" href="#module-code-triple-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[TRIPLE,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">TRIPLE</span></code> record (code 2) contains a variable number of values representing
+the bytes of the <code class="docutils literal"><span class="pre">target</span> <span class="pre">triple</span></code> specification string.</p>
+</div>
+<div class="section" id="module-code-datalayout-record">
+<h4><a class="toc-backref" href="#id39">MODULE_CODE_DATALAYOUT Record</a><a class="headerlink" href="#module-code-datalayout-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[DATALAYOUT,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">DATALAYOUT</span></code> record (code 3) contains a variable number of values
+representing the bytes of the <code class="docutils literal"><span class="pre">target</span> <span class="pre">datalayout</span></code> specification string.</p>
+</div>
+<div class="section" id="module-code-asm-record">
+<h4><a class="toc-backref" href="#id40">MODULE_CODE_ASM Record</a><a class="headerlink" href="#module-code-asm-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[ASM,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">ASM</span></code> record (code 4) contains a variable number of values representing
+the bytes of <code class="docutils literal"><span class="pre">module</span> <span class="pre">asm</span></code> strings, with individual assembly blocks separated
+by newline (ASCII 10) characters.</p>
+</div>
+<div class="section" id="module-code-sectionname-record">
+<span id="module-code-sectionname"></span><h4><a class="toc-backref" href="#id41">MODULE_CODE_SECTIONNAME Record</a><a class="headerlink" href="#module-code-sectionname-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[SECTIONNAME,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">SECTIONNAME</span></code> record (code 5) contains a variable number of values
+representing the bytes of a single section name string. There should be one
+<code class="docutils literal"><span class="pre">SECTIONNAME</span></code> record for each section name referenced (e.g., in global
+variable or function <code class="docutils literal"><span class="pre">section</span></code> attributes) within the module. These records
+can be referenced by the 1-based index in the <em>section</em> fields of <code class="docutils literal"><span class="pre">GLOBALVAR</span></code>
+or <code class="docutils literal"><span class="pre">FUNCTION</span></code> records.</p>
+</div>
+<div class="section" id="module-code-deplib-record">
+<h4><a class="toc-backref" href="#id42">MODULE_CODE_DEPLIB Record</a><a class="headerlink" href="#module-code-deplib-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[DEPLIB,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">DEPLIB</span></code> record (code 6) contains a variable number of values representing
+the bytes of a single dependent library name string, one of the libraries
+mentioned in a <code class="docutils literal"><span class="pre">deplibs</span></code> declaration.  There should be one <code class="docutils literal"><span class="pre">DEPLIB</span></code> record
+for each library name referenced.</p>
+</div>
+<div class="section" id="module-code-globalvar-record">
+<h4><a class="toc-backref" href="#id43">MODULE_CODE_GLOBALVAR Record</a><a class="headerlink" href="#module-code-globalvar-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[GLOBALVAR,</span> <span class="pre">strtab</span> <span class="pre">offset,</span> <span class="pre">strtab</span> <span class="pre">size,</span> <span class="pre">pointer</span> <span class="pre">type,</span> <span class="pre">isconst,</span> <span class="pre">initid,</span> <span class="pre">linkage,</span> <span class="pre">alignment,</span> <span class="pre">section,</span> <span class="pre">visibility,</span> <span class="pre">threadlocal,</span> <span class="pre">unnamed_addr,</span> <span class="pre">externally_initialized,</span> <span class="pre">dllstorageclass,</span> <span class="pre">comdat,</span> <span class="pre">attributes,</span> <span class="pre">preemptionspecifier]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">GLOBALVAR</span></code> record (code 7) marks the declaration or definition of a
+global variable. The operand fields are:</p>
+<ul class="simple">
+<li><em>strtab offset</em>, <em>strtab size</em>: Specifies the name of the global variable.
+See <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK Contents</a>.</li>
+<li><em>pointer type</em>: The type index of the pointer type used to point to this
+global variable</li>
+<li><em>isconst</em>: Non-zero if the variable is treated as constant within the module,
+or zero if it is not</li>
+<li><em>initid</em>: If non-zero, the value index of the initializer for this variable,
+plus 1.</li>
+</ul>
+<ul class="simple" id="linkage-type">
+<li><em>linkage</em>: An encoding of the linkage type for this variable:<ul>
+<li><code class="docutils literal"><span class="pre">external</span></code>: code 0</li>
+<li><code class="docutils literal"><span class="pre">weak</span></code>: code 1</li>
+<li><code class="docutils literal"><span class="pre">appending</span></code>: code 2</li>
+<li><code class="docutils literal"><span class="pre">internal</span></code>: code 3</li>
+<li><code class="docutils literal"><span class="pre">linkonce</span></code>: code 4</li>
+<li><code class="docutils literal"><span class="pre">dllimport</span></code>: code 5</li>
+<li><code class="docutils literal"><span class="pre">dllexport</span></code>: code 6</li>
+<li><code class="docutils literal"><span class="pre">extern_weak</span></code>: code 7</li>
+<li><code class="docutils literal"><span class="pre">common</span></code>: code 8</li>
+<li><code class="docutils literal"><span class="pre">private</span></code>: code 9</li>
+<li><code class="docutils literal"><span class="pre">weak_odr</span></code>: code 10</li>
+<li><code class="docutils literal"><span class="pre">linkonce_odr</span></code>: code 11</li>
+<li><code class="docutils literal"><span class="pre">available_externally</span></code>: code 12</li>
+<li>deprecated : code 13</li>
+<li>deprecated : code 14</li>
+</ul>
+</li>
+<li>alignment*: The logarithm base 2 of the variable’s requested alignment, plus 1</li>
+<li><em>section</em>: If non-zero, the 1-based section index in the table of
+<a class="reference internal" href="#module-code-sectionname">MODULE_CODE_SECTIONNAME</a> entries.</li>
+</ul>
+<ul class="simple" id="visibility">
+<li><em>visibility</em>: If present, an encoding of the visibility of this variable:<ul>
+<li><code class="docutils literal"><span class="pre">default</span></code>: code 0</li>
+<li><code class="docutils literal"><span class="pre">hidden</span></code>: code 1</li>
+<li><code class="docutils literal"><span class="pre">protected</span></code>: code 2</li>
+</ul>
+</li>
+</ul>
+<ul class="simple" id="bcthreadlocal">
+<li><em>threadlocal</em>: If present, an encoding of the thread local storage mode of the
+variable:<ul>
+<li><code class="docutils literal"><span class="pre">not</span> <span class="pre">thread</span> <span class="pre">local</span></code>: code 0</li>
+<li><code class="docutils literal"><span class="pre">thread</span> <span class="pre">local;</span> <span class="pre">default</span> <span class="pre">TLS</span> <span class="pre">model</span></code>: code 1</li>
+<li><code class="docutils literal"><span class="pre">localdynamic</span></code>: code 2</li>
+<li><code class="docutils literal"><span class="pre">initialexec</span></code>: code 3</li>
+<li><code class="docutils literal"><span class="pre">localexec</span></code>: code 4</li>
+</ul>
+</li>
+</ul>
+<ul class="simple" id="bcunnamedaddr">
+<li><em>unnamed_addr</em>: If present, an encoding of the <code class="docutils literal"><span class="pre">unnamed_addr</span></code> attribute of this
+variable:<ul>
+<li>not <code class="docutils literal"><span class="pre">unnamed_addr</span></code>: code 0</li>
+<li><code class="docutils literal"><span class="pre">unnamed_addr</span></code>: code 1</li>
+<li><code class="docutils literal"><span class="pre">local_unnamed_addr</span></code>: code 2</li>
+</ul>
+</li>
+</ul>
+<ul class="simple" id="bcdllstorageclass">
+<li><em>dllstorageclass</em>: If present, an encoding of the DLL storage class of this variable:<ul>
+<li><code class="docutils literal"><span class="pre">default</span></code>: code 0</li>
+<li><code class="docutils literal"><span class="pre">dllimport</span></code>: code 1</li>
+<li><code class="docutils literal"><span class="pre">dllexport</span></code>: code 2</li>
+</ul>
+</li>
+<li><em>comdat</em>: An encoding of the COMDAT of this function</li>
+<li><em>attributes</em>: If nonzero, the 1-based index into the table of AttributeLists.</li>
+</ul>
+<ul class="simple" id="bcpreemptionspecifier">
+<li><em>preemptionspecifier</em>: If present, an encoding of the runtime preemption specifier of this variable:<ul>
+<li><code class="docutils literal"><span class="pre">dso_preemptable</span></code>: code 0</li>
+<li><code class="docutils literal"><span class="pre">dso_local</span></code>: code 1</li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="module-code-function-record">
+<span id="function"></span><h4><a class="toc-backref" href="#id44">MODULE_CODE_FUNCTION Record</a><a class="headerlink" href="#module-code-function-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[FUNCTION,</span> <span class="pre">strtab</span> <span class="pre">offset,</span> <span class="pre">strtab</span> <span class="pre">size,</span> <span class="pre">type,</span> <span class="pre">callingconv,</span> <span class="pre">isproto,</span> <span class="pre">linkage,</span> <span class="pre">paramattr,</span> <span class="pre">alignment,</span> <span class="pre">section,</span> <span class="pre">visibility,</span> <span class="pre">gc,</span> <span class="pre">prologuedata,</span> <span class="pre">dllstorageclass,</span> <span class="pre">comdat,</span> <span class="pre">prefixdata,</span> <span class="pre">personalityfn,</span> <span class="pre">preemptionspecifier]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">FUNCTION</span></code> record (code 8) marks the declaration or definition of a
+function. The operand fields are:</p>
+<ul class="simple">
+<li><em>strtab offset</em>, <em>strtab size</em>: Specifies the name of the function.
+See <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK Contents</a>.</li>
+<li><em>type</em>: The type index of the function type describing this function</li>
+<li><em>callingconv</em>: The calling convention number:
+* <code class="docutils literal"><span class="pre">ccc</span></code>: code 0
+* <code class="docutils literal"><span class="pre">fastcc</span></code>: code 8
+* <code class="docutils literal"><span class="pre">coldcc</span></code>: code 9
+* <code class="docutils literal"><span class="pre">webkit_jscc</span></code>: code 12
+* <code class="docutils literal"><span class="pre">anyregcc</span></code>: code 13
+* <code class="docutils literal"><span class="pre">preserve_mostcc</span></code>: code 14
+* <code class="docutils literal"><span class="pre">preserve_allcc</span></code>: code 15
+* <code class="docutils literal"><span class="pre">swiftcc</span></code> : code 16
+* <code class="docutils literal"><span class="pre">cxx_fast_tlscc</span></code>: code 17
+* <code class="docutils literal"><span class="pre">x86_stdcallcc</span></code>: code 64
+* <code class="docutils literal"><span class="pre">x86_fastcallcc</span></code>: code 65
+* <code class="docutils literal"><span class="pre">arm_apcscc</span></code>: code 66
+* <code class="docutils literal"><span class="pre">arm_aapcscc</span></code>: code 67
+* <code class="docutils literal"><span class="pre">arm_aapcs_vfpcc</span></code>: code 68</li>
+<li>isproto*: Non-zero if this entry represents a declaration rather than a
+definition</li>
+<li><em>linkage</em>: An encoding of the <a class="reference internal" href="#linkage-type">linkage type</a> for this function</li>
+<li><em>paramattr</em>: If nonzero, the 1-based parameter attribute index into the table
+of <a class="reference internal" href="#paramattr-code-entry">PARAMATTR_CODE_ENTRY</a> entries.</li>
+<li><em>alignment</em>: The logarithm base 2 of the function’s requested alignment, plus
+1</li>
+<li><em>section</em>: If non-zero, the 1-based section index in the table of
+<a class="reference internal" href="#module-code-sectionname">MODULE_CODE_SECTIONNAME</a> entries.</li>
+<li><em>visibility</em>: An encoding of the <a class="reference internal" href="#visibility">visibility</a> of this function</li>
+<li><em>gc</em>: If present and nonzero, the 1-based garbage collector index in the table
+of <a class="reference internal" href="#module-code-gcname">MODULE_CODE_GCNAME</a> entries.</li>
+<li><em>unnamed_addr</em>: If present, an encoding of the
+<a class="reference internal" href="#bcunnamedaddr"><span class="std std-ref">unnamed_addr</span></a> attribute of this function</li>
+<li><em>prologuedata</em>: If non-zero, the value index of the prologue data for this function,
+plus 1.</li>
+<li><em>dllstorageclass</em>: An encoding of the
+<a class="reference internal" href="#bcdllstorageclass"><span class="std std-ref">dllstorageclass</span></a> of this function</li>
+<li><em>comdat</em>: An encoding of the COMDAT of this function</li>
+<li><em>prefixdata</em>: If non-zero, the value index of the prefix data for this function,
+plus 1.</li>
+<li><em>personalityfn</em>: If non-zero, the value index of the personality function for this function,
+plus 1.</li>
+<li><em>preemptionspecifier</em>: If present, an encoding of the <a class="reference internal" href="#bcpreemptionspecifier"><span class="std std-ref">runtime preemption specifier</span></a>  of this function.</li>
+</ul>
+</div>
+<div class="section" id="module-code-alias-record">
+<h4><a class="toc-backref" href="#id45">MODULE_CODE_ALIAS Record</a><a class="headerlink" href="#module-code-alias-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[ALIAS,</span> <span class="pre">strtab</span> <span class="pre">offset,</span> <span class="pre">strtab</span> <span class="pre">size,</span> <span class="pre">alias</span> <span class="pre">type,</span> <span class="pre">aliasee</span> <span class="pre">val#,</span> <span class="pre">linkage,</span> <span class="pre">visibility,</span> <span class="pre">dllstorageclass,</span> <span class="pre">threadlocal,</span> <span class="pre">unnamed_addr,</span> <span class="pre">preemptionspecifier]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">ALIAS</span></code> record (code 9) marks the definition of an alias. The operand
+fields are</p>
+<ul class="simple">
+<li><em>strtab offset</em>, <em>strtab size</em>: Specifies the name of the alias.
+See <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK Contents</a>.</li>
+<li><em>alias type</em>: The type index of the alias</li>
+<li><em>aliasee val#</em>: The value index of the aliased value</li>
+<li><em>linkage</em>: An encoding of the <a class="reference internal" href="#linkage-type">linkage type</a> for this alias</li>
+<li><em>visibility</em>: If present, an encoding of the <a class="reference internal" href="#visibility">visibility</a> of the alias</li>
+<li><em>dllstorageclass</em>: If present, an encoding of the
+<a class="reference internal" href="#bcdllstorageclass"><span class="std std-ref">dllstorageclass</span></a> of the alias</li>
+<li><em>threadlocal</em>: If present, an encoding of the
+<a class="reference internal" href="#bcthreadlocal"><span class="std std-ref">thread local property</span></a> of the alias</li>
+<li><em>unnamed_addr</em>: If present, an encoding of the
+<a class="reference internal" href="#bcunnamedaddr"><span class="std std-ref">unnamed_addr</span></a> attribute of this alias</li>
+<li><em>preemptionspecifier</em>: If present, an encoding of the <a class="reference internal" href="#bcpreemptionspecifier"><span class="std std-ref">runtime preemption specifier</span></a>  of this alias.</li>
+</ul>
+</div>
+<div class="section" id="module-code-gcname-record">
+<span id="module-code-gcname"></span><h4><a class="toc-backref" href="#id46">MODULE_CODE_GCNAME Record</a><a class="headerlink" href="#module-code-gcname-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[GCNAME,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">GCNAME</span></code> record (code 11) contains a variable number of values
+representing the bytes of a single garbage collector name string. There should
+be one <code class="docutils literal"><span class="pre">GCNAME</span></code> record for each garbage collector name referenced in function
+<code class="docutils literal"><span class="pre">gc</span></code> attributes within the module. These records can be referenced by 1-based
+index in the <em>gc</em> fields of <code class="docutils literal"><span class="pre">FUNCTION</span></code> records.</p>
+</div>
+</div>
+<div class="section" id="paramattr-block-contents">
+<span id="paramattr-block"></span><h3><a class="toc-backref" href="#id47">PARAMATTR_BLOCK Contents</a><a class="headerlink" href="#paramattr-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">PARAMATTR_BLOCK</span></code> block (id 9) contains a table of entries describing the
+attributes of function parameters. These entries are referenced by 1-based index
+in the <em>paramattr</em> field of module block <a class="reference internal" href="#function">FUNCTION</a> records, or within the
+<em>attr</em> field of function block <code class="docutils literal"><span class="pre">INST_INVOKE</span></code> and <code class="docutils literal"><span class="pre">INST_CALL</span></code> records.</p>
+<p>Entries within <code class="docutils literal"><span class="pre">PARAMATTR_BLOCK</span></code> are constructed to ensure that each is unique
+(i.e., no two indices represent equivalent attribute lists).</p>
+<div class="section" id="paramattr-code-entry-record">
+<span id="paramattr-code-entry"></span><h4><a class="toc-backref" href="#id48">PARAMATTR_CODE_ENTRY Record</a><a class="headerlink" href="#paramattr-code-entry-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[ENTRY,</span> <span class="pre">attrgrp0,</span> <span class="pre">attrgrp1,</span> <span class="pre">...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">ENTRY</span></code> record (code 2) contains a variable number of values describing a
+unique set of function parameter attributes. Each <em>attrgrp</em> value is used as a
+key with which to look up an entry in the the attribute group table described
+in the <code class="docutils literal"><span class="pre">PARAMATTR_GROUP_BLOCK</span></code> block.</p>
+</div>
+<div class="section" id="paramattr-code-entry-old-record">
+<span id="paramattr-code-entry-old"></span><h4><a class="toc-backref" href="#id49">PARAMATTR_CODE_ENTRY_OLD Record</a><a class="headerlink" href="#paramattr-code-entry-old-record" title="Permalink to this headline">¶</a></h4>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">This is a legacy encoding for attributes, produced by LLVM versions 3.2 and
+earlier. It is guaranteed to be understood by the current LLVM version, as
+specified in the <a class="reference internal" href="DeveloperPolicy.html#ir-backwards-compatibility"><span class="std std-ref">IR Backwards Compatibility</span></a> policy.</p>
+</div>
+<p><code class="docutils literal"><span class="pre">[ENTRY,</span> <span class="pre">paramidx0,</span> <span class="pre">attr0,</span> <span class="pre">paramidx1,</span> <span class="pre">attr1...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">ENTRY</span></code> record (code 1) contains an even number of values describing a
+unique set of function parameter attributes. Each <em>paramidx</em> value indicates
+which set of attributes is represented, with 0 representing the return value
+attributes, 0xFFFFFFFF representing function attributes, and other values
+representing 1-based function parameters. Each <em>attr</em> value is a bitmap with the
+following interpretation:</p>
+<ul class="simple">
+<li>bit 0: <code class="docutils literal"><span class="pre">zeroext</span></code></li>
+<li>bit 1: <code class="docutils literal"><span class="pre">signext</span></code></li>
+<li>bit 2: <code class="docutils literal"><span class="pre">noreturn</span></code></li>
+<li>bit 3: <code class="docutils literal"><span class="pre">inreg</span></code></li>
+<li>bit 4: <code class="docutils literal"><span class="pre">sret</span></code></li>
+<li>bit 5: <code class="docutils literal"><span class="pre">nounwind</span></code></li>
+<li>bit 6: <code class="docutils literal"><span class="pre">noalias</span></code></li>
+<li>bit 7: <code class="docutils literal"><span class="pre">byval</span></code></li>
+<li>bit 8: <code class="docutils literal"><span class="pre">nest</span></code></li>
+<li>bit 9: <code class="docutils literal"><span class="pre">readnone</span></code></li>
+<li>bit 10: <code class="docutils literal"><span class="pre">readonly</span></code></li>
+<li>bit 11: <code class="docutils literal"><span class="pre">noinline</span></code></li>
+<li>bit 12: <code class="docutils literal"><span class="pre">alwaysinline</span></code></li>
+<li>bit 13: <code class="docutils literal"><span class="pre">optsize</span></code></li>
+<li>bit 14: <code class="docutils literal"><span class="pre">ssp</span></code></li>
+<li>bit 15: <code class="docutils literal"><span class="pre">sspreq</span></code></li>
+<li>bits 16-31: <code class="docutils literal"><span class="pre">align</span> <span class="pre">n</span></code></li>
+<li>bit 32: <code class="docutils literal"><span class="pre">nocapture</span></code></li>
+<li>bit 33: <code class="docutils literal"><span class="pre">noredzone</span></code></li>
+<li>bit 34: <code class="docutils literal"><span class="pre">noimplicitfloat</span></code></li>
+<li>bit 35: <code class="docutils literal"><span class="pre">naked</span></code></li>
+<li>bit 36: <code class="docutils literal"><span class="pre">inlinehint</span></code></li>
+<li>bits 37-39: <code class="docutils literal"><span class="pre">alignstack</span> <span class="pre">n</span></code>, represented as the logarithm
+base 2 of the requested alignment, plus 1</li>
+</ul>
+</div>
+</div>
+<div class="section" id="paramattr-group-block-contents">
+<span id="paramattr-group-block"></span><h3><a class="toc-backref" href="#id50">PARAMATTR_GROUP_BLOCK Contents</a><a class="headerlink" href="#paramattr-group-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">PARAMATTR_GROUP_BLOCK</span></code> block (id 10) contains a table of entries
+describing the attribute groups present in the module. These entries can be
+referenced within <code class="docutils literal"><span class="pre">PARAMATTR_CODE_ENTRY</span></code> entries.</p>
+<div class="section" id="paramattr-grp-code-entry-record">
+<span id="paramattr-grp-code-entry"></span><h4><a class="toc-backref" href="#id51">PARAMATTR_GRP_CODE_ENTRY Record</a><a class="headerlink" href="#paramattr-grp-code-entry-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[ENTRY,</span> <span class="pre">grpid,</span> <span class="pre">paramidx,</span> <span class="pre">attr0,</span> <span class="pre">attr1,</span> <span class="pre">...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">ENTRY</span></code> record (code 3) contains <em>grpid</em> and <em>paramidx</em> values, followed
+by a variable number of values describing a unique group of attributes. The
+<em>grpid</em> value is a unique key for the attribute group, which can be referenced
+within <code class="docutils literal"><span class="pre">PARAMATTR_CODE_ENTRY</span></code> entries. The <em>paramidx</em> value indicates which
+set of attributes is represented, with 0 representing the return value
+attributes, 0xFFFFFFFF representing function attributes, and other values
+representing 1-based function parameters.</p>
+<p>Each <em>attr</em> is itself represented as a variable number of values:</p>
+<p><code class="docutils literal"><span class="pre">kind,</span> <span class="pre">key</span> <span class="pre">[,</span> <span class="pre">...],</span> <span class="pre">[value</span> <span class="pre">[,</span> <span class="pre">...]]</span></code></p>
+<p>Each attribute is either a well-known LLVM attribute (possibly with an integer
+value associated with it), or an arbitrary string (possibly with an arbitrary
+string value associated with it). The <em>kind</em> value is an integer code
+distinguishing between these possibilities:</p>
+<ul class="simple">
+<li>code 0: well-known attribute</li>
+<li>code 1: well-known attribute with an integer value</li>
+<li>code 3: string attribute</li>
+<li>code 4: string attribute with a string value</li>
+</ul>
+<p>For well-known attributes (code 0 or 1), the <em>key</em> value is an integer code
+identifying the attribute. For attributes with an integer argument (code 1),
+the <em>value</em> value indicates the argument.</p>
+<p>For string attributes (code 3 or 4), the <em>key</em> value is actually a variable
+number of values representing the bytes of a null-terminated string. For
+attributes with a string argument (code 4), the <em>value</em> value is similarly a
+variable number of values representing the bytes of a null-terminated string.</p>
+<p>The integer codes are mapped to well-known attributes as follows.</p>
+<ul class="simple">
+<li>code 1: <code class="docutils literal"><span class="pre">align(<n>)</span></code></li>
+<li>code 2: <code class="docutils literal"><span class="pre">alwaysinline</span></code></li>
+<li>code 3: <code class="docutils literal"><span class="pre">byval</span></code></li>
+<li>code 4: <code class="docutils literal"><span class="pre">inlinehint</span></code></li>
+<li>code 5: <code class="docutils literal"><span class="pre">inreg</span></code></li>
+<li>code 6: <code class="docutils literal"><span class="pre">minsize</span></code></li>
+<li>code 7: <code class="docutils literal"><span class="pre">naked</span></code></li>
+<li>code 8: <code class="docutils literal"><span class="pre">nest</span></code></li>
+<li>code 9: <code class="docutils literal"><span class="pre">noalias</span></code></li>
+<li>code 10: <code class="docutils literal"><span class="pre">nobuiltin</span></code></li>
+<li>code 11: <code class="docutils literal"><span class="pre">nocapture</span></code></li>
+<li>code 12: <code class="docutils literal"><span class="pre">noduplicates</span></code></li>
+<li>code 13: <code class="docutils literal"><span class="pre">noimplicitfloat</span></code></li>
+<li>code 14: <code class="docutils literal"><span class="pre">noinline</span></code></li>
+<li>code 15: <code class="docutils literal"><span class="pre">nonlazybind</span></code></li>
+<li>code 16: <code class="docutils literal"><span class="pre">noredzone</span></code></li>
+<li>code 17: <code class="docutils literal"><span class="pre">noreturn</span></code></li>
+<li>code 18: <code class="docutils literal"><span class="pre">nounwind</span></code></li>
+<li>code 19: <code class="docutils literal"><span class="pre">optsize</span></code></li>
+<li>code 20: <code class="docutils literal"><span class="pre">readnone</span></code></li>
+<li>code 21: <code class="docutils literal"><span class="pre">readonly</span></code></li>
+<li>code 22: <code class="docutils literal"><span class="pre">returned</span></code></li>
+<li>code 23: <code class="docutils literal"><span class="pre">returns_twice</span></code></li>
+<li>code 24: <code class="docutils literal"><span class="pre">signext</span></code></li>
+<li>code 25: <code class="docutils literal"><span class="pre">alignstack(<n>)</span></code></li>
+<li>code 26: <code class="docutils literal"><span class="pre">ssp</span></code></li>
+<li>code 27: <code class="docutils literal"><span class="pre">sspreq</span></code></li>
+<li>code 28: <code class="docutils literal"><span class="pre">sspstrong</span></code></li>
+<li>code 29: <code class="docutils literal"><span class="pre">sret</span></code></li>
+<li>code 30: <code class="docutils literal"><span class="pre">sanitize_address</span></code></li>
+<li>code 31: <code class="docutils literal"><span class="pre">sanitize_thread</span></code></li>
+<li>code 32: <code class="docutils literal"><span class="pre">sanitize_memory</span></code></li>
+<li>code 33: <code class="docutils literal"><span class="pre">uwtable</span></code></li>
+<li>code 34: <code class="docutils literal"><span class="pre">zeroext</span></code></li>
+<li>code 35: <code class="docutils literal"><span class="pre">builtin</span></code></li>
+<li>code 36: <code class="docutils literal"><span class="pre">cold</span></code></li>
+<li>code 37: <code class="docutils literal"><span class="pre">optnone</span></code></li>
+<li>code 38: <code class="docutils literal"><span class="pre">inalloca</span></code></li>
+<li>code 39: <code class="docutils literal"><span class="pre">nonnull</span></code></li>
+<li>code 40: <code class="docutils literal"><span class="pre">jumptable</span></code></li>
+<li>code 41: <code class="docutils literal"><span class="pre">dereferenceable(<n>)</span></code></li>
+<li>code 42: <code class="docutils literal"><span class="pre">dereferenceable_or_null(<n>)</span></code></li>
+<li>code 43: <code class="docutils literal"><span class="pre">convergent</span></code></li>
+<li>code 44: <code class="docutils literal"><span class="pre">safestack</span></code></li>
+<li>code 45: <code class="docutils literal"><span class="pre">argmemonly</span></code></li>
+<li>code 46: <code class="docutils literal"><span class="pre">swiftself</span></code></li>
+<li>code 47: <code class="docutils literal"><span class="pre">swifterror</span></code></li>
+<li>code 48: <code class="docutils literal"><span class="pre">norecurse</span></code></li>
+<li>code 49: <code class="docutils literal"><span class="pre">inaccessiblememonly</span></code></li>
+<li>code 50: <code class="docutils literal"><span class="pre">inaccessiblememonly_or_argmemonly</span></code></li>
+<li>code 51: <code class="docutils literal"><span class="pre">allocsize(<EltSizeParam>[,</span> <span class="pre"><NumEltsParam>])</span></code></li>
+<li>code 52: <code class="docutils literal"><span class="pre">writeonly</span></code></li>
+<li>code 53: <code class="docutils literal"><span class="pre">speculatable</span></code></li>
+<li>code 54: <code class="docutils literal"><span class="pre">strictfp</span></code></li>
+<li>code 55: <code class="docutils literal"><span class="pre">sanitize_hwaddress</span></code></li>
+</ul>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">The <code class="docutils literal"><span class="pre">allocsize</span></code> attribute has a special encoding for its arguments. Its two
+arguments, which are 32-bit integers, are packed into one 64-bit integer value
+(i.e. <code class="docutils literal"><span class="pre">(EltSizeParam</span> <span class="pre"><<</span> <span class="pre">32)</span> <span class="pre">|</span> <span class="pre">NumEltsParam</span></code>), with <code class="docutils literal"><span class="pre">NumEltsParam</span></code> taking on
+the sentinel value -1 if it is not specified.</p>
+</div>
+</div>
+</div>
+<div class="section" id="type-block-contents">
+<span id="type-block"></span><h3><a class="toc-backref" href="#id52">TYPE_BLOCK Contents</a><a class="headerlink" href="#type-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">TYPE_BLOCK</span></code> block (id 17) contains records which constitute a table of
+type operator entries used to represent types referenced within an LLVM
+module. Each record (with the exception of <a class="reference internal" href="#numentry">NUMENTRY</a>) generates a single type
+table entry, which may be referenced by 0-based index from instructions,
+constants, metadata, type symbol table entries, or other type operator records.</p>
+<p>Entries within <code class="docutils literal"><span class="pre">TYPE_BLOCK</span></code> are constructed to ensure that each entry is
+unique (i.e., no two indices represent structurally equivalent types).</p>
+<div class="section" id="type-code-numentry-record">
+<span id="numentry"></span><span id="type-code-numentry"></span><h4><a class="toc-backref" href="#id53">TYPE_CODE_NUMENTRY Record</a><a class="headerlink" href="#type-code-numentry-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[NUMENTRY,</span> <span class="pre">numentries]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">NUMENTRY</span></code> record (code 1) contains a single value which indicates the
+total number of type code entries in the type table of the module. If present,
+<code class="docutils literal"><span class="pre">NUMENTRY</span></code> should be the first record in the block.</p>
+</div>
+<div class="section" id="type-code-void-record">
+<h4><a class="toc-backref" href="#id54">TYPE_CODE_VOID Record</a><a class="headerlink" href="#type-code-void-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[VOID]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">VOID</span></code> record (code 2) adds a <code class="docutils literal"><span class="pre">void</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-half-record">
+<h4><a class="toc-backref" href="#id55">TYPE_CODE_HALF Record</a><a class="headerlink" href="#type-code-half-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[HALF]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">HALF</span></code> record (code 10) adds a <code class="docutils literal"><span class="pre">half</span></code> (16-bit floating point) type to
+the type table.</p>
+</div>
+<div class="section" id="type-code-float-record">
+<h4><a class="toc-backref" href="#id56">TYPE_CODE_FLOAT Record</a><a class="headerlink" href="#type-code-float-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[FLOAT]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">FLOAT</span></code> record (code 3) adds a <code class="docutils literal"><span class="pre">float</span></code> (32-bit floating point) type to
+the type table.</p>
+</div>
+<div class="section" id="type-code-double-record">
+<h4><a class="toc-backref" href="#id57">TYPE_CODE_DOUBLE Record</a><a class="headerlink" href="#type-code-double-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[DOUBLE]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">DOUBLE</span></code> record (code 4) adds a <code class="docutils literal"><span class="pre">double</span></code> (64-bit floating point) type to
+the type table.</p>
+</div>
+<div class="section" id="type-code-label-record">
+<h4><a class="toc-backref" href="#id58">TYPE_CODE_LABEL Record</a><a class="headerlink" href="#type-code-label-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[LABEL]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">LABEL</span></code> record (code 5) adds a <code class="docutils literal"><span class="pre">label</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-opaque-record">
+<h4><a class="toc-backref" href="#id59">TYPE_CODE_OPAQUE Record</a><a class="headerlink" href="#type-code-opaque-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[OPAQUE]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">OPAQUE</span></code> record (code 6) adds an <code class="docutils literal"><span class="pre">opaque</span></code> type to the type table, with
+a name defined by a previously encountered <code class="docutils literal"><span class="pre">STRUCT_NAME</span></code> record. Note that
+distinct <code class="docutils literal"><span class="pre">opaque</span></code> types are not unified.</p>
+</div>
+<div class="section" id="type-code-integer-record">
+<h4><a class="toc-backref" href="#id60">TYPE_CODE_INTEGER Record</a><a class="headerlink" href="#type-code-integer-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[INTEGER,</span> <span class="pre">width]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">INTEGER</span></code> record (code 7) adds an integer type to the type table. The
+single <em>width</em> field indicates the width of the integer type.</p>
+</div>
+<div class="section" id="type-code-pointer-record">
+<h4><a class="toc-backref" href="#id61">TYPE_CODE_POINTER Record</a><a class="headerlink" href="#type-code-pointer-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[POINTER,</span> <span class="pre">pointee</span> <span class="pre">type,</span> <span class="pre">address</span> <span class="pre">space]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">POINTER</span></code> record (code 8) adds a pointer type to the type table. The
+operand fields are</p>
+<ul class="simple">
+<li><em>pointee type</em>: The type index of the pointed-to type</li>
+<li><em>address space</em>: If supplied, the target-specific numbered address space where
+the pointed-to object resides. Otherwise, the default address space is zero.</li>
+</ul>
+</div>
+<div class="section" id="type-code-function-old-record">
+<h4><a class="toc-backref" href="#id62">TYPE_CODE_FUNCTION_OLD Record</a><a class="headerlink" href="#type-code-function-old-record" title="Permalink to this headline">¶</a></h4>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">This is a legacy encoding for functions, produced by LLVM versions 3.0 and
+earlier. It is guaranteed to be understood by the current LLVM version, as
+specified in the <a class="reference internal" href="DeveloperPolicy.html#ir-backwards-compatibility"><span class="std std-ref">IR Backwards Compatibility</span></a> policy.</p>
+</div>
+<p><code class="docutils literal"><span class="pre">[FUNCTION_OLD,</span> <span class="pre">vararg,</span> <span class="pre">ignored,</span> <span class="pre">retty,</span> <span class="pre">...paramty...</span> <span class="pre">]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">FUNCTION_OLD</span></code> record (code 9) adds a function type to the type table.
+The operand fields are</p>
+<ul class="simple">
+<li><em>vararg</em>: Non-zero if the type represents a varargs function</li>
+<li><em>ignored</em>: This value field is present for backward compatibility only, and is
+ignored</li>
+<li><em>retty</em>: The type index of the function’s return type</li>
+<li><em>paramty</em>: Zero or more type indices representing the parameter types of the
+function</li>
+</ul>
+</div>
+<div class="section" id="type-code-array-record">
+<h4><a class="toc-backref" href="#id63">TYPE_CODE_ARRAY Record</a><a class="headerlink" href="#type-code-array-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[ARRAY,</span> <span class="pre">numelts,</span> <span class="pre">eltty]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">ARRAY</span></code> record (code 11) adds an array type to the type table.  The
+operand fields are</p>
+<ul class="simple">
+<li><em>numelts</em>: The number of elements in arrays of this type</li>
+<li><em>eltty</em>: The type index of the array element type</li>
+</ul>
+</div>
+<div class="section" id="type-code-vector-record">
+<h4><a class="toc-backref" href="#id64">TYPE_CODE_VECTOR Record</a><a class="headerlink" href="#type-code-vector-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[VECTOR,</span> <span class="pre">numelts,</span> <span class="pre">eltty]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">VECTOR</span></code> record (code 12) adds a vector type to the type table.  The
+operand fields are</p>
+<ul class="simple">
+<li><em>numelts</em>: The number of elements in vectors of this type</li>
+<li><em>eltty</em>: The type index of the vector element type</li>
+</ul>
+</div>
+<div class="section" id="type-code-x86-fp80-record">
+<h4><a class="toc-backref" href="#id65">TYPE_CODE_X86_FP80 Record</a><a class="headerlink" href="#type-code-x86-fp80-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[X86_FP80]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">X86_FP80</span></code> record (code 13) adds an <code class="docutils literal"><span class="pre">x86_fp80</span></code> (80-bit floating point)
+type to the type table.</p>
+</div>
+<div class="section" id="type-code-fp128-record">
+<h4><a class="toc-backref" href="#id66">TYPE_CODE_FP128 Record</a><a class="headerlink" href="#type-code-fp128-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[FP128]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">FP128</span></code> record (code 14) adds an <code class="docutils literal"><span class="pre">fp128</span></code> (128-bit floating point) type
+to the type table.</p>
+</div>
+<div class="section" id="type-code-ppc-fp128-record">
+<h4><a class="toc-backref" href="#id67">TYPE_CODE_PPC_FP128 Record</a><a class="headerlink" href="#type-code-ppc-fp128-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[PPC_FP128]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">PPC_FP128</span></code> record (code 15) adds a <code class="docutils literal"><span class="pre">ppc_fp128</span></code> (128-bit floating point)
+type to the type table.</p>
+</div>
+<div class="section" id="type-code-metadata-record">
+<h4><a class="toc-backref" href="#id68">TYPE_CODE_METADATA Record</a><a class="headerlink" href="#type-code-metadata-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[METADATA]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">METADATA</span></code> record (code 16) adds a <code class="docutils literal"><span class="pre">metadata</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-x86-mmx-record">
+<h4><a class="toc-backref" href="#id69">TYPE_CODE_X86_MMX Record</a><a class="headerlink" href="#type-code-x86-mmx-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[X86_MMX]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">X86_MMX</span></code> record (code 17) adds an <code class="docutils literal"><span class="pre">x86_mmx</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-struct-anon-record">
+<h4><a class="toc-backref" href="#id70">TYPE_CODE_STRUCT_ANON Record</a><a class="headerlink" href="#type-code-struct-anon-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[STRUCT_ANON,</span> <span class="pre">ispacked,</span> <span class="pre">...eltty...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">STRUCT_ANON</span></code> record (code 18) adds a literal struct type to the type
+table. The operand fields are</p>
+<ul class="simple">
+<li><em>ispacked</em>: Non-zero if the type represents a packed structure</li>
+<li><em>eltty</em>: Zero or more type indices representing the element types of the
+structure</li>
+</ul>
+</div>
+<div class="section" id="type-code-struct-name-record">
+<h4><a class="toc-backref" href="#id71">TYPE_CODE_STRUCT_NAME Record</a><a class="headerlink" href="#type-code-struct-name-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[STRUCT_NAME,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">STRUCT_NAME</span></code> record (code 19) contains a variable number of values
+representing the bytes of a struct name. The next <code class="docutils literal"><span class="pre">OPAQUE</span></code> or
+<code class="docutils literal"><span class="pre">STRUCT_NAMED</span></code> record will use this name.</p>
+</div>
+<div class="section" id="type-code-struct-named-record">
+<h4><a class="toc-backref" href="#id72">TYPE_CODE_STRUCT_NAMED Record</a><a class="headerlink" href="#type-code-struct-named-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[STRUCT_NAMED,</span> <span class="pre">ispacked,</span> <span class="pre">...eltty...]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">STRUCT_NAMED</span></code> record (code 20) adds an identified struct type to the
+type table, with a name defined by a previously encountered <code class="docutils literal"><span class="pre">STRUCT_NAME</span></code>
+record. The operand fields are</p>
+<ul class="simple">
+<li><em>ispacked</em>: Non-zero if the type represents a packed structure</li>
+<li><em>eltty</em>: Zero or more type indices representing the element types of the
+structure</li>
+</ul>
+</div>
+<div class="section" id="type-code-function-record">
+<h4><a class="toc-backref" href="#id73">TYPE_CODE_FUNCTION Record</a><a class="headerlink" href="#type-code-function-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal"><span class="pre">[FUNCTION,</span> <span class="pre">vararg,</span> <span class="pre">retty,</span> <span class="pre">...paramty...</span> <span class="pre">]</span></code></p>
+<p>The <code class="docutils literal"><span class="pre">FUNCTION</span></code> record (code 21) adds a function type to the type table. The
+operand fields are</p>
+<ul class="simple">
+<li><em>vararg</em>: Non-zero if the type represents a varargs function</li>
+<li><em>retty</em>: The type index of the function’s return type</li>
+<li><em>paramty</em>: Zero or more type indices representing the parameter types of the
+function</li>
+</ul>
+</div>
+</div>
+<div class="section" id="constants-block-contents">
+<span id="constants-block"></span><h3><a class="toc-backref" href="#id74">CONSTANTS_BLOCK Contents</a><a class="headerlink" href="#constants-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">CONSTANTS_BLOCK</span></code> block (id 11) ...</p>
+</div>
+<div class="section" id="function-block-contents">
+<span id="function-block"></span><h3><a class="toc-backref" href="#id75">FUNCTION_BLOCK Contents</a><a class="headerlink" href="#function-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">FUNCTION_BLOCK</span></code> block (id 12) ...</p>
+<p>In addition to the record types described below, a <code class="docutils literal"><span class="pre">FUNCTION_BLOCK</span></code> block may
+contain the following sub-blocks:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#constants-block">CONSTANTS_BLOCK</a></li>
+<li><a class="reference internal" href="#value-symtab-block">VALUE_SYMTAB_BLOCK</a></li>
+<li><a class="reference internal" href="#metadata-attachment">METADATA_ATTACHMENT</a></li>
+</ul>
+</div>
+<div class="section" id="value-symtab-block-contents">
+<span id="value-symtab-block"></span><h3><a class="toc-backref" href="#id76">VALUE_SYMTAB_BLOCK Contents</a><a class="headerlink" href="#value-symtab-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">VALUE_SYMTAB_BLOCK</span></code> block (id 14) ...</p>
+</div>
+<div class="section" id="metadata-block-contents">
+<span id="metadata-block"></span><h3><a class="toc-backref" href="#id77">METADATA_BLOCK Contents</a><a class="headerlink" href="#metadata-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">METADATA_BLOCK</span></code> block (id 15) ...</p>
+</div>
+<div class="section" id="metadata-attachment-contents">
+<span id="metadata-attachment"></span><h3><a class="toc-backref" href="#id78">METADATA_ATTACHMENT Contents</a><a class="headerlink" href="#metadata-attachment-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">METADATA_ATTACHMENT</span></code> block (id 16) ...</p>
+</div>
+<div class="section" id="strtab-block-contents">
+<span id="strtab-block"></span><h3><a class="toc-backref" href="#id79">STRTAB_BLOCK Contents</a><a class="headerlink" href="#strtab-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">STRTAB</span></code> block (id 23) contains a single record (<code class="docutils literal"><span class="pre">STRTAB_BLOB</span></code>, id 1)
+with a single blob operand containing the bitcode file’s string table.</p>
+<p>Strings in the string table are not null terminated. A record’s <em>strtab
+offset</em> and <em>strtab size</em> operands specify the byte offset and size of a
+string within the string table.</p>
+<p>The string table is used by all preceding blocks in the bitcode file that are
+not succeeded by another intervening <code class="docutils literal"><span class="pre">STRTAB</span></code> block. Normally a bitcode
+file will have a single string table, but it may have more than one if it
+was created by binary concatenation of multiple bitcode files.</p>
+</div>
+</div>
+</div>
+
+
+          </div>
+      </div>
+      <div class="clearer"></div>
+    </div>
+    <div class="related" role="navigation" aria-label="related navigation">
+      <h3>Navigation</h3>
+      <ul>
+        <li class="right" style="margin-right: 10px">
+          <a href="genindex.html" title="General Index"
+             >index</a></li>
+        <li class="right" >
+          <a href="BlockFrequencyTerminology.html" title="LLVM Block Frequency Terminology"
+             >next</a> |</li>
+        <li class="right" >
+          <a href="MemorySSA.html" title="MemorySSA"
+             >previous</a> |</li>
+  <li><a href="http://llvm.org/">LLVM Home</a> | </li>
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+        © Copyright 2003-2018, LLVM Project.
+      Last updated on 2018-03-02.
+      Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.5.6.
+    </div>
+  </body>
+</html>
\ No newline at end of file

Added: www-releases/trunk/6.0.0/docs/BlockFrequencyTerminology.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/6.0.0/docs/BlockFrequencyTerminology.html?rev=326992&view=auto
==============================================================================
--- www-releases/trunk/6.0.0/docs/BlockFrequencyTerminology.html (added)
+++ www-releases/trunk/6.0.0/docs/BlockFrequencyTerminology.html Thu Mar  8 02:24:44 2018
@@ -0,0 +1,216 @@
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
+  "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+  <head>
+    <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
+    
+    <title>LLVM Block Frequency Terminology — LLVM 6 documentation</title>
+    
+    <link rel="stylesheet" href="_static/llvm-theme.css" type="text/css" />
+    <link rel="stylesheet" href="_static/pygments.css" type="text/css" />
+    
+    <script type="text/javascript">
+      var DOCUMENTATION_OPTIONS = {
+        URL_ROOT:    './',
+        VERSION:     '6',
+        COLLAPSE_INDEX: false,
+        FILE_SUFFIX: '.html',
+        HAS_SOURCE:  true,
+        SOURCELINK_SUFFIX: '.txt'
+      };
+    </script>
+    <script type="text/javascript" src="_static/jquery.js"></script>
+    <script type="text/javascript" src="_static/underscore.js"></script>
+    <script type="text/javascript" src="_static/doctools.js"></script>
+    <link rel="index" title="Index" href="genindex.html" />
+    <link rel="search" title="Search" href="search.html" />
+    <link rel="next" title="LLVM Branch Weight Metadata" href="BranchWeightMetadata.html" />
+    <link rel="prev" title="LLVM Bitcode File Format" href="BitCodeFormat.html" />
+<style type="text/css">
+  table.right { float: right; margin-left: 20px; }
+  table.right td { border: 1px solid #ccc; }
+</style>
+
+  </head>
+  <body role="document">
+<div class="logo">
+  <a href="index.html">
+    <img src="_static/logo.png"
+         alt="LLVM Logo" width="250" height="88"/></a>
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+      <h3>Navigation</h3>
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+        <li class="right" >
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+        <li class="right" >
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+  <li><a href="index.html">Documentation</a>»</li>
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+      </ul>
+    </div>
+
+
+    <div class="document">
+      <div class="documentwrapper">
+          <div class="body" role="main">
+            
+  <div class="section" id="llvm-block-frequency-terminology">
+<h1>LLVM Block Frequency Terminology<a class="headerlink" href="#llvm-block-frequency-terminology" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#branch-probability" id="id2">Branch Probability</a></li>
+<li><a class="reference internal" href="#branch-weight" id="id3">Branch Weight</a></li>
+<li><a class="reference internal" href="#block-frequency" id="id4">Block Frequency</a></li>
+<li><a class="reference internal" href="#implementation-a-series-of-dags" id="id5">Implementation: a series of DAGs</a></li>
+<li><a class="reference internal" href="#block-mass" id="id6">Block Mass</a></li>
+<li><a class="reference internal" href="#loop-scale" id="id7">Loop Scale</a></li>
+<li><a class="reference internal" href="#implementation-getting-from-mass-and-scale-to-frequency" id="id8">Implementation: Getting from mass and scale to frequency</a></li>
+<li><a class="reference internal" href="#block-bias" id="id9">Block Bias</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Block Frequency is a metric for estimating the relative frequency of different
+basic blocks.  This document describes the terminology that the
+<code class="docutils literal"><span class="pre">BlockFrequencyInfo</span></code> and <code class="docutils literal"><span class="pre">MachineBlockFrequencyInfo</span></code> analysis passes use.</p>
+</div>
+<div class="section" id="branch-probability">
+<h2><a class="toc-backref" href="#id2">Branch Probability</a><a class="headerlink" href="#branch-probability" title="Permalink to this headline">¶</a></h2>
+<p>Blocks with multiple successors have probabilities associated with each
+outgoing edge.  These are called branch probabilities.  For a given block, the
+sum of its outgoing branch probabilities should be 1.0.</p>
+</div>
+<div class="section" id="branch-weight">
+<h2><a class="toc-backref" href="#id3">Branch Weight</a><a class="headerlink" href="#branch-weight" title="Permalink to this headline">¶</a></h2>
+<p>Rather than storing fractions on each edge, we store an integer weight.
+Weights are relative to the other edges of a given predecessor block.  The
+branch probability associated with a given edge is its own weight divided by
+the sum of the weights on the predecessor’s outgoing edges.</p>
+<p>For example, consider this IR:</p>
+<div class="highlight-llvm"><div class="highlight"><pre><span></span><span class="k">define</span> <span class="kt">void</span> <span class="vg">@foo</span><span class="p">()</span> <span class="p">{</span>
+    <span class="c">; ...</span>
+    <span class="nl">A:</span>
+        <span class="k">br</span> <span class="k">i1</span> <span class="nv">%cond</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%B</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%C</span><span class="p">,</span> <span class="nv">!prof</span> <span class="nv nv-Anonymous">!0</span>
+    <span class="c">; ...</span>
+<span class="p">}</span>
+<span class="nv nv-Anonymous">!0</span> <span class="p">=</span> <span class="kt">metadata</span> <span class="p">!{</span><span class="kt">metadata</span> <span class="nv">!"branch_weights"</span><span class="p">,</span> <span class="k">i32</span> <span class="m">7</span><span class="p">,</span> <span class="k">i32</span> <span class="m">8</span><span class="p">}</span>
+</pre></div>
+</div>
+<p>and this simple graph representation:</p>
+<div class="highlight-default"><div class="highlight"><pre><span></span><span class="n">A</span> <span class="o">-></span> <span class="n">B</span>  <span class="p">(</span><span class="n">edge</span><span class="o">-</span><span class="n">weight</span><span class="p">:</span> <span class="mi">7</span><span class="p">)</span>
+<span class="n">A</span> <span class="o">-></span> <span class="n">C</span>  <span class="p">(</span><span class="n">edge</span><span class="o">-</span><span class="n">weight</span><span class="p">:</span> <span class="mi">8</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>The probability of branching from block A to block B is 7/15, and the
+probability of branching from block A to block C is 8/15.</p>
+<p>See <a class="reference internal" href="BranchWeightMetadata.html"><span class="doc">LLVM Branch Weight Metadata</span></a> for details about the branch weight IR
+representation.</p>
+</div>
+<div class="section" id="block-frequency">
+<h2><a class="toc-backref" href="#id4">Block Frequency</a><a class="headerlink" href="#block-frequency" title="Permalink to this headline">¶</a></h2>
+<p>Block frequency is a relative metric that represents the number of times a
+block executes.  The ratio of a block frequency to the entry block frequency is
+the expected number of times the block will execute per entry to the function.</p>
+<p>Block frequency is the main output of the <code class="docutils literal"><span class="pre">BlockFrequencyInfo</span></code> and
+<code class="docutils literal"><span class="pre">MachineBlockFrequencyInfo</span></code> analysis passes.</p>
+</div>
+<div class="section" id="implementation-a-series-of-dags">
+<h2><a class="toc-backref" href="#id5">Implementation: a series of DAGs</a><a class="headerlink" href="#implementation-a-series-of-dags" title="Permalink to this headline">¶</a></h2>
+<p>The implementation of the block frequency calculation analyses each loop,
+bottom-up, ignoring backedges; i.e., as a DAG.  After each loop is processed,
+it’s packaged up to act as a pseudo-node in its parent loop’s (or the
+function’s) DAG analysis.</p>
+</div>
+<div class="section" id="block-mass">
+<h2><a class="toc-backref" href="#id6">Block Mass</a><a class="headerlink" href="#block-mass" title="Permalink to this headline">¶</a></h2>
+<p>For each DAG, the entry node is assigned a mass of <code class="docutils literal"><span class="pre">UINT64_MAX</span></code> and mass is
+distributed to successors according to branch weights.  Block Mass uses a
+fixed-point representation where <code class="docutils literal"><span class="pre">UINT64_MAX</span></code> represents <code class="docutils literal"><span class="pre">1.0</span></code> and <code class="docutils literal"><span class="pre">0</span></code>
+represents a number just above <code class="docutils literal"><span class="pre">0.0</span></code>.</p>
+<p>After mass is fully distributed, in any cut of the DAG that separates the exit
+nodes from the entry node, the sum of the block masses of the nodes succeeded
+by a cut edge should equal <code class="docutils literal"><span class="pre">UINT64_MAX</span></code>.  In other words, mass is conserved
+as it “falls” through the DAG.</p>
+<p>If a function’s basic block graph is a DAG, then block masses are valid block
+frequencies.  This works poorly in practise though, since downstream users rely
+on adding block frequencies together without hitting the maximum.</p>
+</div>
+<div class="section" id="loop-scale">
+<h2><a class="toc-backref" href="#id7">Loop Scale</a><a class="headerlink" href="#loop-scale" title="Permalink to this headline">¶</a></h2>
+<p>Loop scale is a metric that indicates how many times a loop iterates per entry.
+As mass is distributed through the loop’s DAG, the (otherwise ignored) backedge
+mass is collected.  This backedge mass is used to compute the exit frequency,
+and thus the loop scale.</p>
+</div>
+<div class="section" id="implementation-getting-from-mass-and-scale-to-frequency">
+<h2><a class="toc-backref" href="#id8">Implementation: Getting from mass and scale to frequency</a><a class="headerlink" href="#implementation-getting-from-mass-and-scale-to-frequency" title="Permalink to this headline">¶</a></h2>
+<p>After analysing the complete series of DAGs, each block has a mass (local to
+its containing loop, if any), and each loop pseudo-node has a loop scale and
+its own mass (from its parent’s DAG).</p>
+<p>We can get an initial frequency assignment (with entry frequency of 1.0) by
+multiplying these masses and loop scales together.  A given block’s frequency
+is the product of its mass, the mass of containing loops’ pseudo nodes, and the
+containing loops’ loop scales.</p>
+<p>Since downstream users need integers (not floating point), this initial
+frequency assignment is shifted as necessary into the range of <code class="docutils literal"><span class="pre">uint64_t</span></code>.</p>
+</div>
+<div class="section" id="block-bias">
+<h2><a class="toc-backref" href="#id9">Block Bias</a><a class="headerlink" href="#block-bias" title="Permalink to this headline">¶</a></h2>
+<p>Block bias is a proposed <em>absolute</em> metric to indicate a bias toward or away
+from a given block during a function’s execution.  The idea is that bias can be
+used in isolation to indicate whether a block is relatively hot or cold, or to
+compare two blocks to indicate whether one is hotter or colder than the other.</p>
+<p>The proposed calculation involves calculating a <em>reference</em> block frequency,
+where:</p>
+<ul class="simple">
+<li>every branch weight is assumed to be 1 (i.e., every branch probability
+distribution is even) and</li>
+<li>loop scales are ignored.</li>
+</ul>
+<p>This reference frequency represents what the block frequency would be in an
+unbiased graph.</p>
+<p>The bias is the ratio of the block frequency to this reference block frequency.</p>
+</div>
+</div>
+
+
+          </div>
+      </div>
+      <div class="clearer"></div>
+    </div>
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+          <a href="BranchWeightMetadata.html" title="LLVM Branch Weight Metadata"
+             >next</a> |</li>
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+            
+  <div class="section" id="llvm-branch-weight-metadata">
+<h1>LLVM Branch Weight Metadata<a class="headerlink" href="#llvm-branch-weight-metadata" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#supported-instructions" id="id2">Supported Instructions</a><ul>
+<li><a class="reference internal" href="#branchinst" id="id3"><code class="docutils literal"><span class="pre">BranchInst</span></code></a></li>
+<li><a class="reference internal" href="#switchinst" id="id4"><code class="docutils literal"><span class="pre">SwitchInst</span></code></a></li>
+<li><a class="reference internal" href="#indirectbrinst" id="id5"><code class="docutils literal"><span class="pre">IndirectBrInst</span></code></a></li>
+<li><a class="reference internal" href="#callinst" id="id6"><code class="docutils literal"><span class="pre">CallInst</span></code></a></li>
+<li><a class="reference internal" href="#other" id="id7">Other</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#built-in-expect-instructions" id="id8">Built-in <code class="docutils literal"><span class="pre">expect</span></code> Instructions</a><ul>
+<li><a class="reference internal" href="#if-statement" id="id9"><code class="docutils literal"><span class="pre">if</span></code> statement</a></li>
+<li><a class="reference internal" href="#switch-statement" id="id10"><code class="docutils literal"><span class="pre">switch</span></code> statement</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#cfg-modifications" id="id11">CFG Modifications</a></li>
+<li><a class="reference internal" href="#function-entry-counts" id="id12">Function Entry Counts</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Branch Weight Metadata represents branch weights as its likeliness to be taken
+(see <a class="reference internal" href="BlockFrequencyTerminology.html"><span class="doc">LLVM Block Frequency Terminology</span></a>). Metadata is assigned to the
+<code class="docutils literal"><span class="pre">TerminatorInst</span></code> as a <code class="docutils literal"><span class="pre">MDNode</span></code> of the <code class="docutils literal"><span class="pre">MD_prof</span></code> kind. The first operator
+is always a <code class="docutils literal"><span class="pre">MDString</span></code> node with the string “branch_weights”.  Number of
+operators depends on the terminator type.</p>
+<p>Branch weights might be fetch from the profiling file, or generated based on
+<a class="reference internal" href="#builtin-expect">__builtin_expect</a> instruction.</p>
+<p>All weights are represented as an unsigned 32-bit values, where higher value
+indicates greater chance to be taken.</p>
+</div>
+<div class="section" id="supported-instructions">
+<h2><a class="toc-backref" href="#id2">Supported Instructions</a><a class="headerlink" href="#supported-instructions" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="branchinst">
+<h3><a class="toc-backref" href="#id3"><code class="docutils literal"><span class="pre">BranchInst</span></code></a><a class="headerlink" href="#branchinst" title="Permalink to this headline">¶</a></h3>
+<p>Metadata is only assigned to the conditional branches. There are two extra
+operands for the true and the false branch.</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span>!0 = metadata !{
+  metadata !"branch_weights",
+  i32 <TRUE_BRANCH_WEIGHT>,
+  i32 <FALSE_BRANCH_WEIGHT>
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="switchinst">
+<h3><a class="toc-backref" href="#id4"><code class="docutils literal"><span class="pre">SwitchInst</span></code></a><a class="headerlink" href="#switchinst" title="Permalink to this headline">¶</a></h3>
+<p>Branch weights are assigned to every case (including the <code class="docutils literal"><span class="pre">default</span></code> case which
+is always case #0).</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span>!0 = metadata !{
+  metadata !"branch_weights",
+  i32 <DEFAULT_BRANCH_WEIGHT>
+  [ , i32 <CASE_BRANCH_WEIGHT> ... ]
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="indirectbrinst">
+<h3><a class="toc-backref" href="#id5"><code class="docutils literal"><span class="pre">IndirectBrInst</span></code></a><a class="headerlink" href="#indirectbrinst" title="Permalink to this headline">¶</a></h3>
+<p>Branch weights are assigned to every destination.</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span>!0 = metadata !{
+  metadata !"branch_weights",
+  i32 <LABEL_BRANCH_WEIGHT>
+  [ , i32 <LABEL_BRANCH_WEIGHT> ... ]
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="callinst">
+<h3><a class="toc-backref" href="#id6"><code class="docutils literal"><span class="pre">CallInst</span></code></a><a class="headerlink" href="#callinst" title="Permalink to this headline">¶</a></h3>
+<p>Calls may have branch weight metadata, containing the execution count of
+the call. It is currently used in SamplePGO mode only, to augment the
+block and entry counts which may not be accurate with sampling.</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span>!0 = metadata !{
+  metadata !"branch_weights",
+  i32 <CALL_BRANCH_WEIGHT>
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="other">
+<h3><a class="toc-backref" href="#id7">Other</a><a class="headerlink" href="#other" title="Permalink to this headline">¶</a></h3>
+<p>Other terminator instructions are not allowed to contain Branch Weight Metadata.</p>
+</div>
+</div>
+<div class="section" id="built-in-expect-instructions">
+<span id="builtin-expect"></span><h2><a class="toc-backref" href="#id8">Built-in <code class="docutils literal"><span class="pre">expect</span></code> Instructions</a><a class="headerlink" href="#built-in-expect-instructions" title="Permalink to this headline">¶</a></h2>
+<p><code class="docutils literal"><span class="pre">__builtin_expect(long</span> <span class="pre">exp,</span> <span class="pre">long</span> <span class="pre">c)</span></code> instruction provides branch prediction
+information. The return value is the value of <code class="docutils literal"><span class="pre">exp</span></code>.</p>
+<p>It is especially useful in conditional statements. Currently Clang supports two
+conditional statements:</p>
+<div class="section" id="if-statement">
+<h3><a class="toc-backref" href="#id9"><code class="docutils literal"><span class="pre">if</span></code> statement</a><a class="headerlink" href="#if-statement" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">exp</span></code> parameter is the condition. The <code class="docutils literal"><span class="pre">c</span></code> parameter is the expected
+comparison value. If it is equal to 1 (true), the condition is likely to be
+true, in other case condition is likely to be false. For example:</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="k">if</span> <span class="p">(</span><span class="n">__builtin_expect</span><span class="p">(</span><span class="n">x</span> <span class="o">></span> <span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">))</span> <span class="p">{</span>
+  <span class="c1">// This block is likely to be taken.</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="switch-statement">
+<h3><a class="toc-backref" href="#id10"><code class="docutils literal"><span class="pre">switch</span></code> statement</a><a class="headerlink" href="#switch-statement" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal"><span class="pre">exp</span></code> parameter is the value. The <code class="docutils literal"><span class="pre">c</span></code> parameter is the expected
+value. If the expected value doesn’t show on the cases list, the <code class="docutils literal"><span class="pre">default</span></code>
+case is assumed to be likely taken.</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="k">switch</span> <span class="p">(</span><span class="n">__builtin_expect</span><span class="p">(</span><span class="n">x</span><span class="p">,</span> <span class="mi">5</span><span class="p">))</span> <span class="p">{</span>
+<span class="k">default</span><span class="o">:</span> <span class="k">break</span><span class="p">;</span>
+<span class="k">case</span> <span class="mi">0</span><span class="o">:</span>  <span class="c1">// ...</span>
+<span class="k">case</span> <span class="mi">3</span><span class="o">:</span>  <span class="c1">// ...</span>
+<span class="k">case</span> <span class="mi">5</span><span class="o">:</span>  <span class="c1">// This case is likely to be taken.</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="cfg-modifications">
+<h2><a class="toc-backref" href="#id11">CFG Modifications</a><a class="headerlink" href="#cfg-modifications" title="Permalink to this headline">¶</a></h2>
+<p>Branch Weight Metatada is not proof against CFG changes. If terminator operands’
+are changed some action should be taken. In other case some misoptimizations may
+occur due to incorrect branch prediction information.</p>
+</div>
+<div class="section" id="function-entry-counts">
+<h2><a class="toc-backref" href="#id12">Function Entry Counts</a><a class="headerlink" href="#function-entry-counts" title="Permalink to this headline">¶</a></h2>
+<p>To allow comparing different functions during inter-procedural analysis and
+optimization, <code class="docutils literal"><span class="pre">MD_prof</span></code> nodes can also be assigned to a function definition.
+The first operand is a string indicating the name of the associated counter.</p>
+<p>Currently, one counter is supported: “function_entry_count”. The second operand
+is a 64-bit counter that indicates the number of times that this function was
+invoked (in the case of instrumentation-based profiles). In the case of
+sampling-based profiles, this operand is an approximation of how many times
+the function was invoked.</p>
+<p>For example, in the code below, the instrumentation for function foo()
+indicates that it was called 2,590 times at runtime.</p>
+<div class="highlight-llvm"><div class="highlight"><pre><span></span><span class="k">define</span> <span class="k">i32</span> <span class="vg">@foo</span><span class="p">()</span> <span class="nv">!prof</span> <span class="nv nv-Anonymous">!1</span> <span class="p">{</span>
+  <span class="k">ret</span> <span class="k">i32</span> <span class="m">0</span>
+<span class="p">}</span>
+<span class="nv nv-Anonymous">!1</span> <span class="p">=</span> <span class="p">!{</span><span class="nv">!"function_entry_count"</span><span class="p">,</span> <span class="k">i64</span> <span class="m">2590</span><span class="p">}</span>
+</pre></div>
+</div>
+<p>If “function_entry_count” has more than 2 operands, the later operands are
+the GUID of the functions that needs to be imported by ThinLTO. This is only
+set by sampling based profile. It is needed because the sampling based profile
+was collected on a binary that had already imported and inlined these functions,
+and we need to ensure the IR matches in the ThinLTO backends for profile
+annotation. The reason why we cannot annotate this on the callsite is that it
+can only goes down 1 level in the call chain. For the cases where
+foo_in_a_cc()->bar_in_b_cc()->baz_in_c_cc(), we will need to go down 2 levels
+in the call chain to import both bar_in_b_cc and baz_in_c_cc.</p>
+</div>
+</div>
+
+
+          </div>
+      </div>
+      <div class="clearer"></div>
+    </div>
+    <div class="related" role="navigation" aria-label="related navigation">
+      <h3>Navigation</h3>
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+             >index</a></li>
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+          <a href="Bugpoint.html" title="LLVM bugpoint tool: design and usage"
+             >next</a> |</li>
+        <li class="right" >
+          <a href="BlockFrequencyTerminology.html" title="LLVM Block Frequency Terminology"
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+  <div class="section" id="llvm-bugpoint-tool-design-and-usage">
+<h1>LLVM bugpoint tool: design and usage<a class="headerlink" href="#llvm-bugpoint-tool-design-and-usage" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#description" id="id4">Description</a></li>
+<li><a class="reference internal" href="#design-philosophy" id="id5">Design Philosophy</a><ul>
+<li><a class="reference internal" href="#automatic-debugger-selection" id="id6">Automatic Debugger Selection</a></li>
+<li><a class="reference internal" href="#crash-debugger" id="id7">Crash debugger</a></li>
+<li><a class="reference internal" href="#code-generator-debugger" id="id8">Code generator debugger</a></li>
+<li><a class="reference internal" href="#miscompilation-debugger" id="id9">Miscompilation debugger</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#advice-for-using-bugpoint" id="id10">Advice for using bugpoint</a></li>
+<li><a class="reference internal" href="#what-to-do-when-bugpoint-isn-t-enough" id="id11">What to do when bugpoint isn’t enough</a></li>
+</ul>
+</div>
+<div class="section" id="description">
+<h2><a class="toc-backref" href="#id4">Description</a><a class="headerlink" href="#description" title="Permalink to this headline">¶</a></h2>
+<p><code class="docutils literal"><span class="pre">bugpoint</span></code> narrows down the source of problems in LLVM tools and passes.  It
+can be used to debug three types of failures: optimizer crashes, miscompilations
+by optimizers, or bad native code generation (including problems in the static
+and JIT compilers).  It aims to reduce large test cases to small, useful ones.
+For example, if <code class="docutils literal"><span class="pre">opt</span></code> crashes while optimizing a file, it will identify the
+optimization (or combination of optimizations) that causes the crash, and reduce
+the file down to a small example which triggers the crash.</p>
+<p>For detailed case scenarios, such as debugging <code class="docutils literal"><span class="pre">opt</span></code>, or one of the LLVM code
+generators, see <a class="reference internal" href="HowToSubmitABug.html"><span class="doc">How to submit an LLVM bug report</span></a>.</p>
+</div>
+<div class="section" id="design-philosophy">
+<h2><a class="toc-backref" href="#id5">Design Philosophy</a><a class="headerlink" href="#design-philosophy" title="Permalink to this headline">¶</a></h2>
+<p><code class="docutils literal"><span class="pre">bugpoint</span></code> is designed to be a useful tool without requiring any hooks into
+the LLVM infrastructure at all.  It works with any and all LLVM passes and code
+generators, and does not need to “know” how they work.  Because of this, it may
+appear to do stupid things or miss obvious simplifications.  <code class="docutils literal"><span class="pre">bugpoint</span></code> is
+also designed to trade off programmer time for computer time in the
+compiler-debugging process; consequently, it may take a long period of
+(unattended) time to reduce a test case, but we feel it is still worth it. Note
+that <code class="docutils literal"><span class="pre">bugpoint</span></code> is generally very quick unless debugging a miscompilation
+where each test of the program (which requires executing it) takes a long time.</p>
+<div class="section" id="automatic-debugger-selection">
+<h3><a class="toc-backref" href="#id6">Automatic Debugger Selection</a><a class="headerlink" href="#automatic-debugger-selection" title="Permalink to this headline">¶</a></h3>
+<p><code class="docutils literal"><span class="pre">bugpoint</span></code> reads each <code class="docutils literal"><span class="pre">.bc</span></code> or <code class="docutils literal"><span class="pre">.ll</span></code> file specified on the command line
+and links them together into a single module, called the test program.  If any
+LLVM passes are specified on the command line, it runs these passes on the test
+program.  If any of the passes crash, or if they produce malformed output (which
+causes the verifier to abort), <code class="docutils literal"><span class="pre">bugpoint</span></code> starts the <a class="reference internal" href="#crash-debugger">crash debugger</a>.</p>
+<p>Otherwise, if the <code class="docutils literal"><span class="pre">-output</span></code> option was not specified, <code class="docutils literal"><span class="pre">bugpoint</span></code> runs the
+test program with the “safe” backend (which is assumed to generate good code) to
+generate a reference output.  Once <code class="docutils literal"><span class="pre">bugpoint</span></code> has a reference output for the
+test program, it tries executing it with the selected code generator.  If the
+selected code generator crashes, <code class="docutils literal"><span class="pre">bugpoint</span></code> starts the <a class="reference internal" href="#crash-debugger">crash debugger</a> on
+the code generator.  Otherwise, if the resulting output differs from the
+reference output, it assumes the difference resulted from a code generator
+failure, and starts the <a class="reference internal" href="#code-generator-debugger">code generator debugger</a>.</p>
+<p>Finally, if the output of the selected code generator matches the reference
+output, <code class="docutils literal"><span class="pre">bugpoint</span></code> runs the test program after all of the LLVM passes have
+been applied to it.  If its output differs from the reference output, it assumes
+the difference resulted from a failure in one of the LLVM passes, and enters the
+<a class="reference internal" href="#miscompilation-debugger">miscompilation debugger</a>.  Otherwise, there is no problem <code class="docutils literal"><span class="pre">bugpoint</span></code> can
+debug.</p>
+</div>
+<div class="section" id="crash-debugger">
+<span id="id1"></span><h3><a class="toc-backref" href="#id7">Crash debugger</a><a class="headerlink" href="#crash-debugger" title="Permalink to this headline">¶</a></h3>
+<p>If an optimizer or code generator crashes, <code class="docutils literal"><span class="pre">bugpoint</span></code> will try as hard as it
+can to reduce the list of passes (for optimizer crashes) and the size of the
+test program.  First, <code class="docutils literal"><span class="pre">bugpoint</span></code> figures out which combination of optimizer
+passes triggers the bug. This is useful when debugging a problem exposed by
+<code class="docutils literal"><span class="pre">opt</span></code>, for example, because it runs over 38 passes.</p>
+<p>Next, <code class="docutils literal"><span class="pre">bugpoint</span></code> tries removing functions from the test program, to reduce its
+size.  Usually it is able to reduce a test program to a single function, when
+debugging intraprocedural optimizations.  Once the number of functions has been
+reduced, it attempts to delete various edges in the control flow graph, to
+reduce the size of the function as much as possible.  Finally, <code class="docutils literal"><span class="pre">bugpoint</span></code>
+deletes any individual LLVM instructions whose absence does not eliminate the
+failure.  At the end, <code class="docutils literal"><span class="pre">bugpoint</span></code> should tell you what passes crash, give you a
+bitcode file, and give you instructions on how to reproduce the failure with
+<code class="docutils literal"><span class="pre">opt</span></code> or <code class="docutils literal"><span class="pre">llc</span></code>.</p>
+</div>
+<div class="section" id="code-generator-debugger">
+<span id="id2"></span><h3><a class="toc-backref" href="#id8">Code generator debugger</a><a class="headerlink" href="#code-generator-debugger" title="Permalink to this headline">¶</a></h3>
+<p>The code generator debugger attempts to narrow down the amount of code that is
+being miscompiled by the selected code generator.  To do this, it takes the test
+program and partitions it into two pieces: one piece which it compiles with the
+“safe” backend (into a shared object), and one piece which it runs with either
+the JIT or the static LLC compiler.  It uses several techniques to reduce the
+amount of code pushed through the LLVM code generator, to reduce the potential
+scope of the problem.  After it is finished, it emits two bitcode files (called
+“test” [to be compiled with the code generator] and “safe” [to be compiled with
+the “safe” backend], respectively), and instructions for reproducing the
+problem.  The code generator debugger assumes that the “safe” backend produces
+good code.</p>
+</div>
+<div class="section" id="miscompilation-debugger">
+<span id="id3"></span><h3><a class="toc-backref" href="#id9">Miscompilation debugger</a><a class="headerlink" href="#miscompilation-debugger" title="Permalink to this headline">¶</a></h3>
+<p>The miscompilation debugger works similarly to the code generator debugger.  It
+works by splitting the test program into two pieces, running the optimizations
+specified on one piece, linking the two pieces back together, and then executing
+the result.  It attempts to narrow down the list of passes to the one (or few)
+which are causing the miscompilation, then reduce the portion of the test
+program which is being miscompiled.  The miscompilation debugger assumes that
+the selected code generator is working properly.</p>
+</div>
+</div>
+<div class="section" id="advice-for-using-bugpoint">
+<h2><a class="toc-backref" href="#id10">Advice for using bugpoint</a><a class="headerlink" href="#advice-for-using-bugpoint" title="Permalink to this headline">¶</a></h2>
+<p><code class="docutils literal"><span class="pre">bugpoint</span></code> can be a remarkably useful tool, but it sometimes works in
+non-obvious ways.  Here are some hints and tips:</p>
+<ul>
+<li><p class="first">In the code generator and miscompilation debuggers, <code class="docutils literal"><span class="pre">bugpoint</span></code> only works
+with programs that have deterministic output.  Thus, if the program outputs
+<code class="docutils literal"><span class="pre">argv[0]</span></code>, the date, time, or any other “random” data, <code class="docutils literal"><span class="pre">bugpoint</span></code> may
+misinterpret differences in these data, when output, as the result of a
+miscompilation.  Programs should be temporarily modified to disable outputs
+that are likely to vary from run to run.</p>
+</li>
+<li><p class="first">In the code generator and miscompilation debuggers, debugging will go faster
+if you manually modify the program or its inputs to reduce the runtime, but
+still exhibit the problem.</p>
+</li>
+<li><p class="first"><code class="docutils literal"><span class="pre">bugpoint</span></code> is extremely useful when working on a new optimization: it helps
+track down regressions quickly.  To avoid having to relink <code class="docutils literal"><span class="pre">bugpoint</span></code> every
+time you change your optimization however, have <code class="docutils literal"><span class="pre">bugpoint</span></code> dynamically load
+your optimization with the <code class="docutils literal"><span class="pre">-load</span></code> option.</p>
+</li>
+<li><p class="first"><code class="docutils literal"><span class="pre">bugpoint</span></code> can generate a lot of output and run for a long period of time.
+It is often useful to capture the output of the program to file.  For example,
+in the C shell, you can run:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> bugpoint  ... <span class="p">|&</span> tee bugpoint.log
+</pre></div>
+</div>
+<p>to get a copy of <code class="docutils literal"><span class="pre">bugpoint</span></code>‘s output in the file <code class="docutils literal"><span class="pre">bugpoint.log</span></code>, as well
+as on your terminal.</p>
+</li>
+<li><p class="first"><code class="docutils literal"><span class="pre">bugpoint</span></code> cannot debug problems with the LLVM linker. If <code class="docutils literal"><span class="pre">bugpoint</span></code>
+crashes before you see its “All input ok” message, you might try <code class="docutils literal"><span class="pre">llvm-link</span>
+<span class="pre">-v</span></code> on the same set of input files. If that also crashes, you may be
+experiencing a linker bug.</p>
+</li>
+<li><p class="first"><code class="docutils literal"><span class="pre">bugpoint</span></code> is useful for proactively finding bugs in LLVM.  Invoking
+<code class="docutils literal"><span class="pre">bugpoint</span></code> with the <code class="docutils literal"><span class="pre">-find-bugs</span></code> option will cause the list of specified
+optimizations to be randomized and applied to the program. This process will
+repeat until a bug is found or the user kills <code class="docutils literal"><span class="pre">bugpoint</span></code>.</p>
+</li>
+<li><p class="first"><code class="docutils literal"><span class="pre">bugpoint</span></code> can produce IR which contains long names. Run <code class="docutils literal"><span class="pre">opt</span>
+<span class="pre">-metarenamer</span></code> over the IR to rename everything using easy-to-read,
+metasyntactic names. Alternatively, run <code class="docutils literal"><span class="pre">opt</span> <span class="pre">-strip</span> <span class="pre">-instnamer</span></code> to rename
+everything with very short (often purely numeric) names.</p>
+</li>
+</ul>
+</div>
+<div class="section" id="what-to-do-when-bugpoint-isn-t-enough">
+<h2><a class="toc-backref" href="#id11">What to do when bugpoint isn’t enough</a><a class="headerlink" href="#what-to-do-when-bugpoint-isn-t-enough" title="Permalink to this headline">¶</a></h2>
+<p>Sometimes, <code class="docutils literal"><span class="pre">bugpoint</span></code> is not enough. In particular, InstCombine and
+TargetLowering both have visitor structured code with lots of potential
+transformations.  If the process of using bugpoint has left you with still too
+much code to figure out and the problem seems to be in instcombine, the
+following steps may help.  These same techniques are useful with TargetLowering
+as well.</p>
+<p>Turn on <code class="docutils literal"><span class="pre">-debug-only=instcombine</span></code> and see which transformations within
+instcombine are firing by selecting out lines with “<code class="docutils literal"><span class="pre">IC</span></code>” in them.</p>
+<p>At this point, you have a decision to make.  Is the number of transformations
+small enough to step through them using a debugger?  If so, then try that.</p>
+<p>If there are too many transformations, then a source modification approach may
+be helpful.  In this approach, you can modify the source code of instcombine to
+disable just those transformations that are being performed on your test input
+and perform a binary search over the set of transformations.  One set of places
+to modify are the “<code class="docutils literal"><span class="pre">visit*</span></code>” methods of <code class="docutils literal"><span class="pre">InstCombiner</span></code> (<em>e.g.</em>
+<code class="docutils literal"><span class="pre">visitICmpInst</span></code>) by adding a “<code class="docutils literal"><span class="pre">return</span> <span class="pre">false</span></code>” as the first line of the
+method.</p>
+<p>If that still doesn’t remove enough, then change the caller of
+<code class="docutils literal"><span class="pre">InstCombiner::DoOneIteration</span></code>, <code class="docutils literal"><span class="pre">InstCombiner::runOnFunction</span></code> to limit the
+number of iterations.</p>
+<p>You may also find it useful to use “<code class="docutils literal"><span class="pre">-stats</span></code>” now to see what parts of
+instcombine are firing.  This can guide where to put additional reporting code.</p>
+<p>At this point, if the amount of transformations is still too large, then
+inserting code to limit whether or not to execute the body of the code in the
+visit function can be helpful.  Add a static counter which is incremented on
+every invocation of the function.  Then add code which simply returns false on
+desired ranges.  For example:</p>
+<div class="highlight-c++"><div class="highlight"><pre><span></span><span class="k">static</span> <span class="kt">int</span> <span class="n">calledCount</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span>
+<span class="n">calledCount</span><span class="o">++</span><span class="p">;</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="k">if</span> <span class="p">(</span><span class="n">calledCount</span> <span class="o"><</span> <span class="mi">212</span><span class="p">)</span> <span class="k">return</span> <span class="nb">false</span><span class="p">);</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="k">if</span> <span class="p">(</span><span class="n">calledCount</span> <span class="o">></span> <span class="mi">217</span><span class="p">)</span> <span class="k">return</span> <span class="nb">false</span><span class="p">);</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="k">if</span> <span class="p">(</span><span class="n">calledCount</span> <span class="o">==</span> <span class="mi">213</span><span class="p">)</span> <span class="k">return</span> <span class="nb">false</span><span class="p">);</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="k">if</span> <span class="p">(</span><span class="n">calledCount</span> <span class="o">==</span> <span class="mi">214</span><span class="p">)</span> <span class="k">return</span> <span class="nb">false</span><span class="p">);</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="k">if</span> <span class="p">(</span><span class="n">calledCount</span> <span class="o">==</span> <span class="mi">215</span><span class="p">)</span> <span class="k">return</span> <span class="nb">false</span><span class="p">);</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="k">if</span> <span class="p">(</span><span class="n">calledCount</span> <span class="o">==</span> <span class="mi">216</span><span class="p">)</span> <span class="k">return</span> <span class="nb">false</span><span class="p">);</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="n">dbgs</span><span class="p">()</span> <span class="o"><<</span> <span class="s">"visitXOR calledCount: "</span> <span class="o"><<</span> <span class="n">calledCount</span> <span class="o"><<</span> <span class="s">"</span><span class="se">\n</span><span class="s">"</span><span class="p">);</span>
+<span class="n">DEBUG</span><span class="p">(</span><span class="n">dbgs</span><span class="p">()</span> <span class="o"><<</span> <span class="s">"I: "</span><span class="p">;</span> <span class="n">I</span><span class="o">-></span><span class="n">dump</span><span class="p">());</span>
+</pre></div>
+</div>
+<p>could be added to <code class="docutils literal"><span class="pre">visitXOR</span></code> to limit <code class="docutils literal"><span class="pre">visitXor</span></code> to being applied only to
+calls 212 and 217. This is from an actual test case and raises an important
+point—a simple binary search may not be sufficient, as transformations that
+interact may require isolating more than one call.  In TargetLowering, use
+<code class="docutils literal"><span class="pre">return</span> <span class="pre">SDNode();</span></code> instead of <code class="docutils literal"><span class="pre">return</span> <span class="pre">false;</span></code>.</p>
+<p>Now that the number of transformations is down to a manageable number, try
+examining the output to see if you can figure out which transformations are
+being done.  If that can be figured out, then do the usual debugging.  If which
+code corresponds to the transformation being performed isn’t obvious, set a
+breakpoint after the call count based disabling and step through the code.
+Alternatively, you can use “<code class="docutils literal"><span class="pre">printf</span></code>” style debugging to report waypoints.</p>
+</div>
+</div>
+
+
+          </div>
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+<div class="logo">
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+
+    <div class="related" role="navigation" aria-label="related navigation">
+      <h3>Navigation</h3>
+      <ul>
+        <li class="right" style="margin-right: 10px">
+          <a href="genindex.html" title="General Index"
+             accesskey="I">index</a></li>
+        <li class="right" >
+          <a href="DeveloperPolicy.html" title="LLVM Developer Policy"
+             accesskey="N">next</a> |</li>
+        <li class="right" >
+          <a href="PDB/CodeViewTypes.html" title="CodeView Type Records"
+             accesskey="P">previous</a> |</li>
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+  <li><a href="index.html">Documentation</a>»</li>
+ 
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+    </div>
+
+
+    <div class="document">
+      <div class="documentwrapper">
+          <div class="body" role="main">
+            
+  <div class="section" id="control-flow-verification-tool-design-document">
+<h1>Control Flow Verification Tool Design Document<a class="headerlink" href="#control-flow-verification-tool-design-document" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#objective" id="id1">Objective</a></li>
+<li><a class="reference internal" href="#location" id="id2">Location</a></li>
+<li><a class="reference internal" href="#background" id="id3">Background</a></li>
+<li><a class="reference internal" href="#design-ideas" id="id4">Design Ideas</a><ul>
+<li><a class="reference internal" href="#other-design-notes" id="id5">Other Design Notes</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="objective">
+<h2><a class="toc-backref" href="#id1">Objective</a><a class="headerlink" href="#objective" title="Permalink to this headline">¶</a></h2>
+<p>This document provides an overview of an external tool to verify the protection
+mechanisms implemented by Clang’s <em>Control Flow Integrity</em> (CFI) schemes
+(<code class="docutils literal"><span class="pre">-fsanitize=cfi</span></code>). This tool, provided a binary or DSO, should infer whether
+indirect control flow operations are protected by CFI, and should output these
+results in a human-readable form.</p>
+<p>This tool should also be added as part of Clang’s continuous integration testing
+framework, where modifications to the compiler ensure that CFI protection
+schemes are still present in the final binary.</p>
+</div>
+<div class="section" id="location">
+<h2><a class="toc-backref" href="#id2">Location</a><a class="headerlink" href="#location" title="Permalink to this headline">¶</a></h2>
+<p>This tool will be present as a part of the LLVM toolchain, and will reside in
+the “/llvm/tools/llvm-cfi-verify” directory, relative to the LLVM trunk. It will
+be tested in two methods:</p>
+<ul class="simple">
+<li>Unit tests to validate code sections, present in “/llvm/unittests/llvm-cfi-
+verify”.</li>
+<li>Integration tests, present in “/llvm/tools/clang/test/LLVMCFIVerify”. These
+integration tests are part of clang as part of a continuous integration
+framework, ensuring updates to the compiler that reduce CFI coverage on
+indirect control flow instructions are identified.</li>
+</ul>
+</div>
+<div class="section" id="background">
+<h2><a class="toc-backref" href="#id3">Background</a><a class="headerlink" href="#background" title="Permalink to this headline">¶</a></h2>
+<p>This tool will continuously validate that CFI directives are properly
+implemented around all indirect control flows by analysing the output machine
+code. The analysis of machine code is important as it ensures that any bugs
+present in linker or compiler do not subvert CFI protections in the final
+shipped binary.</p>
+<p>Unprotected indirect control flow instructions will be flagged for manual
+review. These unexpected control flows may simply have not been accounted for in
+the compiler implementation of CFI (e.g. indirect jumps to facilitate switch
+statements may not be fully protected).</p>
+<p>It may be possible in the future to extend this tool to flag unnecessary CFI
+directives (e.g. CFI directives around a static call to a non-polymorphic base
+type). This type of directive has no security implications, but may present
+performance impacts.</p>
+</div>
+<div class="section" id="design-ideas">
+<h2><a class="toc-backref" href="#id4">Design Ideas</a><a class="headerlink" href="#design-ideas" title="Permalink to this headline">¶</a></h2>
+<p>This tool will disassemble binaries and DSO’s from their machine code format and
+analyse the disassembled machine code. The tool will inspect virtual calls and
+indirect function calls. This tool will also inspect indirect jumps, as inlined
+functions and jump tables should also be subject to CFI protections. Non-virtual
+calls (<code class="docutils literal"><span class="pre">-fsanitize=cfi-nvcall</span></code>) and cast checks (<code class="docutils literal"><span class="pre">-fsanitize=cfi-*cast*</span></code>)
+are not implemented due to a lack of information provided by the bytecode.</p>
+<p>The tool would operate by searching for indirect control flow instructions in
+the disassembly. A control flow graph would be generated from a small buffer of
+the instructions surrounding the ‘target’ control flow instruction. If the
+target instruction is branched-to, the fallthrough of the branch should be the
+CFI trap (on x86, this is a <code class="docutils literal"><span class="pre">ud2</span></code> instruction). If the target instruction is
+the fallthrough (i.e. immediately succeeds) of a conditional jump, the
+conditional jump target should be the CFI trap. If an indirect control flow
+instruction does not conform to one of these formats, the target will be noted
+as being CFI-unprotected.</p>
+<p>Note that in the second case outlined above (where the target instruction is the
+fallthrough of a conditional jump), if the target represents a vcall that takes
+arguments, these arguments may be pushed to the stack after the branch but
+before the target instruction. In these cases, a secondary ‘spill graph’ in
+constructed, to ensure the register argument used by the indirect jump/call is
+not spilled from the stack at any point in the interim period. If there are no
+spills that affect the target register, the target is marked as CFI-protected.</p>
+<div class="section" id="other-design-notes">
+<h3><a class="toc-backref" href="#id5">Other Design Notes</a><a class="headerlink" href="#other-design-notes" title="Permalink to this headline">¶</a></h3>
+<p>Only machine code sections that are marked as executable will be subject to this
+analysis. Non-executable sections do not require analysis as any execution
+present in these sections has already violated the control flow integrity.</p>
+<p>Suitable extensions may be made at a later date to include anaylsis for indirect
+control flow operations across DSO boundaries. Currently, these CFI features are
+only experimental with an unstable ABI, making them unsuitable for analysis.</p>
+</div>
+</div>
+</div>
+
+
+          </div>
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+      <div class="clearer"></div>
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+            
+  <div class="section" id="building-llvm-with-cmake">
+<h1>Building LLVM with CMake<a class="headerlink" href="#building-llvm-with-cmake" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id5">Introduction</a></li>
+<li><a class="reference internal" href="#quick-start" id="id6">Quick start</a></li>
+<li><a class="reference internal" href="#usage" id="id7">Basic CMake usage</a></li>
+<li><a class="reference internal" href="#options-and-variables" id="id8">Options and variables</a><ul>
+<li><a class="reference internal" href="#frequently-used-cmake-variables" id="id9">Frequently-used CMake variables</a></li>
+<li><a class="reference internal" href="#llvm-specific-variables" id="id10">LLVM-specific variables</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#cmake-caches" id="id11">CMake Caches</a></li>
+<li><a class="reference internal" href="#executing-the-test-suite" id="id12">Executing the test suite</a></li>
+<li><a class="reference internal" href="#cross-compiling" id="id13">Cross compiling</a></li>
+<li><a class="reference internal" href="#embedding-llvm-in-your-project" id="id14">Embedding LLVM in your project</a><ul>
+<li><a class="reference internal" href="#developing-llvm-passes-out-of-source" id="id15">Developing LLVM passes out of source</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#compiler-platform-specific-topics" id="id16">Compiler/Platform-specific topics</a><ul>
+<li><a class="reference internal" href="#microsoft-visual-c" id="id17">Microsoft Visual C++</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id5">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p><a class="reference external" href="http://www.cmake.org/">CMake</a> is a cross-platform build-generator tool. CMake
+does not build the project, it generates the files needed by your build tool
+(GNU make, Visual Studio, etc.) for building LLVM.</p>
+<p>If <strong>you are a new contributor</strong>, please start with the <a class="reference internal" href="GettingStarted.html"><span class="doc">Getting Started with the LLVM System</span></a>
+page.  This page is geared for existing contributors moving from the
+legacy configure/make system.</p>
+<p>If you are really anxious about getting a functional LLVM build, go to the
+<a class="reference internal" href="#quick-start">Quick start</a> section. If you are a CMake novice, start with <a class="reference internal" href="#basic-cmake-usage">Basic CMake usage</a>
+and then go back to the <a class="reference internal" href="#quick-start">Quick start</a> section once you know what you are doing. The
+<a class="reference internal" href="#options-and-variables">Options and variables</a> section is a reference for customizing your build. If
+you already have experience with CMake, this is the recommended starting point.</p>
+<p>This page is geared towards users of the LLVM CMake build. If you’re looking for
+information about modifying the LLVM CMake build system you may want to see the
+<a class="reference internal" href="CMakePrimer.html"><span class="doc">CMake Primer</span></a> page. It has a basic overview of the CMake language.</p>
+</div>
+<div class="section" id="quick-start">
+<span id="id1"></span><h2><a class="toc-backref" href="#id6">Quick start</a><a class="headerlink" href="#quick-start" title="Permalink to this headline">¶</a></h2>
+<p>We use here the command-line, non-interactive CMake interface.</p>
+<ol class="arabic">
+<li><p class="first"><a class="reference external" href="http://www.cmake.org/cmake/resources/software.html">Download</a> and install
+CMake. Version 3.4.3 is the minimum required.</p>
+</li>
+<li><p class="first">Open a shell. Your development tools must be reachable from this shell
+through the PATH environment variable.</p>
+</li>
+<li><p class="first">Create a build directory. Building LLVM in the source
+directory is not supported. cd to this directory:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> mkdir mybuilddir
+<span class="gp">$</span> <span class="nb">cd</span> mybuilddir
+</pre></div>
+</div>
+</li>
+<li><p class="first">Execute this command in the shell replacing <cite>path/to/llvm/source/root</cite> with
+the path to the root of your LLVM source tree:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake path/to/llvm/source/root
+</pre></div>
+</div>
+<p>CMake will detect your development environment, perform a series of tests, and
+generate the files required for building LLVM. CMake will use default values
+for all build parameters. See the <a class="reference internal" href="#options-and-variables">Options and variables</a> section for
+a list of build parameters that you can modify.</p>
+<p>This can fail if CMake can’t detect your toolset, or if it thinks that the
+environment is not sane enough. In this case, make sure that the toolset that
+you intend to use is the only one reachable from the shell, and that the shell
+itself is the correct one for your development environment. CMake will refuse
+to build MinGW makefiles if you have a POSIX shell reachable through the PATH
+environment variable, for instance. You can force CMake to use a given build
+tool; for instructions, see the <a class="reference internal" href="#usage">Usage</a> section, below.</p>
+</li>
+<li><p class="first">After CMake has finished running, proceed to use IDE project files, or start
+the build from the build directory:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake --build .
+</pre></div>
+</div>
+<p>The <code class="docutils literal"><span class="pre">--build</span></code> option tells <code class="docutils literal"><span class="pre">cmake</span></code> to invoke the underlying build
+tool (<code class="docutils literal"><span class="pre">make</span></code>, <code class="docutils literal"><span class="pre">ninja</span></code>, <code class="docutils literal"><span class="pre">xcodebuild</span></code>, <code class="docutils literal"><span class="pre">msbuild</span></code>, etc.)</p>
+<p>The underlying build tool can be invoked directly, of course, but
+the <code class="docutils literal"><span class="pre">--build</span></code> option is portable.</p>
+</li>
+<li><p class="first">After LLVM has finished building, install it from the build directory:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake --build . --target install
+</pre></div>
+</div>
+<p>The <code class="docutils literal"><span class="pre">--target</span></code> option with <code class="docutils literal"><span class="pre">install</span></code> parameter in addition to
+the <code class="docutils literal"><span class="pre">--build</span></code> option tells <code class="docutils literal"><span class="pre">cmake</span></code> to build the <code class="docutils literal"><span class="pre">install</span></code> target.</p>
+<p>It is possible to set a different install prefix at installation time
+by invoking the <code class="docutils literal"><span class="pre">cmake_install.cmake</span></code> script generated in the
+build directory:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -DCMAKE_INSTALL_PREFIX<span class="o">=</span>/tmp/llvm -P cmake_install.cmake
+</pre></div>
+</div>
+</li>
+</ol>
+</div>
+<div class="section" id="usage">
+<span id="basic-cmake-usage"></span><span id="id2"></span><h2><a class="toc-backref" href="#id7">Basic CMake usage</a><a class="headerlink" href="#usage" title="Permalink to this headline">¶</a></h2>
+<p>This section explains basic aspects of CMake
+which you may need in your day-to-day usage.</p>
+<p>CMake comes with extensive documentation, in the form of html files, and as
+online help accessible via the <code class="docutils literal"><span class="pre">cmake</span></code> executable itself. Execute <code class="docutils literal"><span class="pre">cmake</span>
+<span class="pre">--help</span></code> for further help options.</p>
+<p>CMake allows you to specify a build tool (e.g., GNU make, Visual Studio,
+or Xcode). If not specified on the command line, CMake tries to guess which
+build tool to use, based on your environment. Once it has identified your
+build tool, CMake uses the corresponding <em>Generator</em> to create files for your
+build tool (e.g., Makefiles or Visual Studio or Xcode project files). You can
+explicitly specify the generator with the command line option <code class="docutils literal"><span class="pre">-G</span> <span class="pre">"Name</span> <span class="pre">of</span> <span class="pre">the</span>
+<span class="pre">generator"</span></code>. To see a list of the available generators on your system, execute</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake --help
+</pre></div>
+</div>
+<p>This will list the generator names at the end of the help text.</p>
+<p>Generators’ names are case-sensitive, and may contain spaces. For this reason,
+you should enter them exactly as they are listed in the <code class="docutils literal"><span class="pre">cmake</span> <span class="pre">--help</span></code>
+output, in quotes. For example, to generate project files specifically for
+Visual Studio 12, you can execute:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G <span class="s2">"Visual Studio 12"</span> path/to/llvm/source/root
+</pre></div>
+</div>
+<p>For a given development platform there can be more than one adequate
+generator. If you use Visual Studio, “NMake Makefiles” is a generator you can use
+for building with NMake. By default, CMake chooses the most specific generator
+supported by your development environment. If you want an alternative generator,
+you must tell this to CMake with the <code class="docutils literal"><span class="pre">-G</span></code> option.</p>
+</div>
+<div class="section" id="options-and-variables">
+<span id="id3"></span><h2><a class="toc-backref" href="#id8">Options and variables</a><a class="headerlink" href="#options-and-variables" title="Permalink to this headline">¶</a></h2>
+<p>Variables customize how the build will be generated. Options are boolean
+variables, with possible values ON/OFF. Options and variables are defined on the
+CMake command line like this:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -DVARIABLE<span class="o">=</span>value path/to/llvm/source
+</pre></div>
+</div>
+<p>You can set a variable after the initial CMake invocation to change its
+value. You can also undefine a variable:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -UVARIABLE path/to/llvm/source
+</pre></div>
+</div>
+<p>Variables are stored in the CMake cache. This is a file named <code class="docutils literal"><span class="pre">CMakeCache.txt</span></code>
+stored at the root of your build directory that is generated by <code class="docutils literal"><span class="pre">cmake</span></code>.
+Editing it yourself is not recommended.</p>
+<p>Variables are listed in the CMake cache and later in this document with
+the variable name and type separated by a colon. You can also specify the
+variable and type on the CMake command line:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -DVARIABLE:TYPE<span class="o">=</span>value path/to/llvm/source
+</pre></div>
+</div>
+<div class="section" id="frequently-used-cmake-variables">
+<h3><a class="toc-backref" href="#id9">Frequently-used CMake variables</a><a class="headerlink" href="#frequently-used-cmake-variables" title="Permalink to this headline">¶</a></h3>
+<p>Here are some of the CMake variables that are used often, along with a
+brief explanation and LLVM-specific notes. For full documentation, consult the
+CMake manual, or execute <code class="docutils literal"><span class="pre">cmake</span> <span class="pre">--help-variable</span> <span class="pre">VARIABLE_NAME</span></code>.</p>
+<dl class="docutils">
+<dt><strong>CMAKE_BUILD_TYPE</strong>:STRING</dt>
+<dd>Sets the build type for <code class="docutils literal"><span class="pre">make</span></code>-based generators. Possible values are
+Release, Debug, RelWithDebInfo and MinSizeRel. If you are using an IDE such as
+Visual Studio, you should use the IDE settings to set the build type.
+Be aware that Release and RelWithDebInfo use different optimization levels on
+most platforms.</dd>
+<dt><strong>CMAKE_INSTALL_PREFIX</strong>:PATH</dt>
+<dd>Path where LLVM will be installed if “make install” is invoked or the
+“install” target is built.</dd>
+<dt><strong>LLVM_LIBDIR_SUFFIX</strong>:STRING</dt>
+<dd>Extra suffix to append to the directory where libraries are to be
+installed. On a 64-bit architecture, one could use <code class="docutils literal"><span class="pre">-DLLVM_LIBDIR_SUFFIX=64</span></code>
+to install libraries to <code class="docutils literal"><span class="pre">/usr/lib64</span></code>.</dd>
+<dt><strong>CMAKE_C_FLAGS</strong>:STRING</dt>
+<dd>Extra flags to use when compiling C source files.</dd>
+<dt><strong>CMAKE_CXX_FLAGS</strong>:STRING</dt>
+<dd>Extra flags to use when compiling C++ source files.</dd>
+</dl>
+</div>
+<div class="section" id="llvm-specific-variables">
+<span id="id4"></span><h3><a class="toc-backref" href="#id10">LLVM-specific variables</a><a class="headerlink" href="#llvm-specific-variables" title="Permalink to this headline">¶</a></h3>
+<dl class="docutils">
+<dt><strong>LLVM_TARGETS_TO_BUILD</strong>:STRING</dt>
+<dd>Semicolon-separated list of targets to build, or <em>all</em> for building all
+targets. Case-sensitive. Defaults to <em>all</em>. Example:
+<code class="docutils literal"><span class="pre">-DLLVM_TARGETS_TO_BUILD="X86;PowerPC"</span></code>.</dd>
+<dt><strong>LLVM_BUILD_TOOLS</strong>:BOOL</dt>
+<dd>Build LLVM tools. Defaults to ON. Targets for building each tool are generated
+in any case. You can build a tool separately by invoking its target. For
+example, you can build <em>llvm-as</em> with a Makefile-based system by executing <em>make
+llvm-as</em> at the root of your build directory.</dd>
+<dt><strong>LLVM_INCLUDE_TOOLS</strong>:BOOL</dt>
+<dd>Generate build targets for the LLVM tools. Defaults to ON. You can use this
+option to disable the generation of build targets for the LLVM tools.</dd>
+<dt><strong>LLVM_INSTALL_BINUTILS_SYMLINKS</strong>:BOOL</dt>
+<dd>Install symlinks from the binutils tool names to the corresponding LLVM tools.
+For example, ar will be symlinked to llvm-ar.</dd>
+<dt><strong>LLVM_BUILD_EXAMPLES</strong>:BOOL</dt>
+<dd>Build LLVM examples. Defaults to OFF. Targets for building each example are
+generated in any case. See documentation for <em>LLVM_BUILD_TOOLS</em> above for more
+details.</dd>
+<dt><strong>LLVM_INCLUDE_EXAMPLES</strong>:BOOL</dt>
+<dd>Generate build targets for the LLVM examples. Defaults to ON. You can use this
+option to disable the generation of build targets for the LLVM examples.</dd>
+<dt><strong>LLVM_BUILD_TESTS</strong>:BOOL</dt>
+<dd>Build LLVM unit tests. Defaults to OFF. Targets for building each unit test
+are generated in any case. You can build a specific unit test using the
+targets defined under <em>unittests</em>, such as ADTTests, IRTests, SupportTests,
+etc. (Search for <code class="docutils literal"><span class="pre">add_llvm_unittest</span></code> in the subdirectories of <em>unittests</em>
+for a complete list of unit tests.) It is possible to build all unit tests
+with the target <em>UnitTests</em>.</dd>
+<dt><strong>LLVM_INCLUDE_TESTS</strong>:BOOL</dt>
+<dd>Generate build targets for the LLVM unit tests. Defaults to ON. You can use
+this option to disable the generation of build targets for the LLVM unit
+tests.</dd>
+<dt><strong>LLVM_APPEND_VC_REV</strong>:BOOL</dt>
+<dd>Embed version control revision info (svn revision number or Git revision id).
+The version info is provided by the <code class="docutils literal"><span class="pre">LLVM_REVISION</span></code> macro in
+<code class="docutils literal"><span class="pre">llvm/include/llvm/Support/VCSRevision.h</span></code>. Developers using git who don’t
+need revision info can disable this option to avoid re-linking most binaries
+after a branch switch. Defaults to ON.</dd>
+<dt><strong>LLVM_ENABLE_THREADS</strong>:BOOL</dt>
+<dd>Build with threads support, if available. Defaults to ON.</dd>
+<dt><strong>LLVM_ENABLE_CXX1Y</strong>:BOOL</dt>
+<dd>Build in C++1y mode, if available. Defaults to OFF.</dd>
+<dt><strong>LLVM_ENABLE_ASSERTIONS</strong>:BOOL</dt>
+<dd>Enables code assertions. Defaults to ON if and only if <code class="docutils literal"><span class="pre">CMAKE_BUILD_TYPE</span></code>
+is <em>Debug</em>.</dd>
+<dt><strong>LLVM_ENABLE_EH</strong>:BOOL</dt>
+<dd>Build LLVM with exception-handling support. This is necessary if you wish to
+link against LLVM libraries and make use of C++ exceptions in your own code
+that need to propagate through LLVM code. Defaults to OFF.</dd>
+<dt><strong>LLVM_ENABLE_EXPENSIVE_CHECKS</strong>:BOOL</dt>
+<dd>Enable additional time/memory expensive checking. Defaults to OFF.</dd>
+<dt><strong>LLVM_ENABLE_PIC</strong>:BOOL</dt>
+<dd>Add the <code class="docutils literal"><span class="pre">-fPIC</span></code> flag to the compiler command-line, if the compiler supports
+this flag. Some systems, like Windows, do not need this flag. Defaults to ON.</dd>
+<dt><strong>LLVM_ENABLE_RTTI</strong>:BOOL</dt>
+<dd>Build LLVM with run-time type information. Defaults to OFF.</dd>
+<dt><strong>LLVM_ENABLE_WARNINGS</strong>:BOOL</dt>
+<dd>Enable all compiler warnings. Defaults to ON.</dd>
+<dt><strong>LLVM_ENABLE_PEDANTIC</strong>:BOOL</dt>
+<dd>Enable pedantic mode. This disables compiler-specific extensions, if
+possible. Defaults to ON.</dd>
+<dt><strong>LLVM_ENABLE_WERROR</strong>:BOOL</dt>
+<dd>Stop and fail the build, if a compiler warning is triggered. Defaults to OFF.</dd>
+<dt><strong>LLVM_ABI_BREAKING_CHECKS</strong>:STRING</dt>
+<dd>Used to decide if LLVM should be built with ABI breaking checks or
+not.  Allowed values are <cite>WITH_ASSERTS</cite> (default), <cite>FORCE_ON</cite> and
+<cite>FORCE_OFF</cite>.  <cite>WITH_ASSERTS</cite> turns on ABI breaking checks in an
+assertion enabled build.  <cite>FORCE_ON</cite> (<cite>FORCE_OFF</cite>) turns them on
+(off) irrespective of whether normal (<cite>NDEBUG</cite>-based) assertions are
+enabled or not.  A version of LLVM built with ABI breaking checks
+is not ABI compatible with a version built without it.</dd>
+<dt><strong>LLVM_BUILD_32_BITS</strong>:BOOL</dt>
+<dd>Build 32-bit executables and libraries on 64-bit systems. This option is
+available only on some 64-bit Unix systems. Defaults to OFF.</dd>
+<dt><strong>LLVM_TARGET_ARCH</strong>:STRING</dt>
+<dd>LLVM target to use for native code generation. This is required for JIT
+generation. It defaults to “host”, meaning that it shall pick the architecture
+of the machine where LLVM is being built. If you are cross-compiling, set it
+to the target architecture name.</dd>
+<dt><strong>LLVM_TABLEGEN</strong>:STRING</dt>
+<dd>Full path to a native TableGen executable (usually named <code class="docutils literal"><span class="pre">llvm-tblgen</span></code>). This is
+intended for cross-compiling: if the user sets this variable, no native
+TableGen will be created.</dd>
+<dt><strong>LLVM_LIT_ARGS</strong>:STRING</dt>
+<dd>Arguments given to lit.  <code class="docutils literal"><span class="pre">make</span> <span class="pre">check</span></code> and <code class="docutils literal"><span class="pre">make</span> <span class="pre">clang-test</span></code> are affected.
+By default, <code class="docutils literal"><span class="pre">'-sv</span> <span class="pre">--no-progress-bar'</span></code> on Visual C++ and Xcode, <code class="docutils literal"><span class="pre">'-sv'</span></code> on
+others.</dd>
+<dt><strong>LLVM_LIT_TOOLS_DIR</strong>:PATH</dt>
+<dd>The path to GnuWin32 tools for tests. Valid on Windows host.  Defaults to
+the empty string, in which case lit will look for tools needed for tests
+(e.g. <code class="docutils literal"><span class="pre">grep</span></code>, <code class="docutils literal"><span class="pre">sort</span></code>, etc.) in your %PATH%. If GnuWin32 is not in your
+%PATH%, then you can set this variable to the GnuWin32 directory so that
+lit can find tools needed for tests in that directory.</dd>
+<dt><strong>LLVM_ENABLE_FFI</strong>:BOOL</dt>
+<dd>Indicates whether the LLVM Interpreter will be linked with the Foreign Function
+Interface library (libffi) in order to enable calling external functions.
+If the library or its headers are installed in a custom
+location, you can also set the variables FFI_INCLUDE_DIR and
+FFI_LIBRARY_DIR to the directories where ffi.h and libffi.so can be found,
+respectively. Defaults to OFF.</dd>
+<dt><strong>LLVM_EXTERNAL_{CLANG,LLD,POLLY}_SOURCE_DIR</strong>:PATH</dt>
+<dd>These variables specify the path to the source directory for the external
+LLVM projects Clang, lld, and Polly, respectively, relative to the top-level
+source directory.  If the in-tree subdirectory for an external project
+exists (e.g., llvm/tools/clang for Clang), then the corresponding variable
+will not be used.  If the variable for an external project does not point
+to a valid path, then that project will not be built.</dd>
+<dt><strong>LLVM_ENABLE_PROJECTS</strong>:STRING</dt>
+<dd>Semicolon-separated list of projects to build, or <em>all</em> for building all
+(clang, libcxx, libcxxabi, lldb, compiler-rt, lld, polly) projects.
+This flag assumes that projects are checked out side-by-side and not nested,
+i.e. clang needs to be in parallel of llvm instead of nested in <cite>llvm/tools</cite>.
+This feature allows to have one build for only LLVM and another for clang+llvm
+using the same source checkout.</dd>
+<dt><strong>LLVM_EXTERNAL_PROJECTS</strong>:STRING</dt>
+<dd>Semicolon-separated list of additional external projects to build as part of
+llvm. For each project LLVM_EXTERNAL_<NAME>_SOURCE_DIR have to be specified
+with the path for the source code of the project. Example:
+<code class="docutils literal"><span class="pre">-DLLVM_EXTERNAL_PROJECTS="Foo;Bar"</span>
+<span class="pre">-DLLVM_EXTERNAL_FOO_SOURCE_DIR=/src/foo</span>
+<span class="pre">-DLLVM_EXTERNAL_BAR_SOURCE_DIR=/src/bar</span></code>.</dd>
+<dt><strong>LLVM_USE_OPROFILE</strong>:BOOL</dt>
+<dd>Enable building OProfile JIT support. Defaults to OFF.</dd>
+<dt><strong>LLVM_PROFDATA_FILE</strong>:PATH</dt>
+<dd>Path to a profdata file to pass into clang’s -fprofile-instr-use flag. This
+can only be specified if you’re building with clang.</dd>
+<dt><strong>LLVM_USE_INTEL_JITEVENTS</strong>:BOOL</dt>
+<dd>Enable building support for Intel JIT Events API. Defaults to OFF.</dd>
+<dt><strong>LLVM_ENABLE_ZLIB</strong>:BOOL</dt>
+<dd>Enable building with zlib to support compression/uncompression in LLVM tools.
+Defaults to ON.</dd>
+<dt><strong>LLVM_ENABLE_DIA_SDK</strong>:BOOL</dt>
+<dd>Enable building with MSVC DIA SDK for PDB debugging support. Available
+only with MSVC. Defaults to ON.</dd>
+<dt><strong>LLVM_USE_SANITIZER</strong>:STRING</dt>
+<dd>Define the sanitizer used to build LLVM binaries and tests. Possible values
+are <code class="docutils literal"><span class="pre">Address</span></code>, <code class="docutils literal"><span class="pre">Memory</span></code>, <code class="docutils literal"><span class="pre">MemoryWithOrigins</span></code>, <code class="docutils literal"><span class="pre">Undefined</span></code>, <code class="docutils literal"><span class="pre">Thread</span></code>,
+and <code class="docutils literal"><span class="pre">Address;Undefined</span></code>. Defaults to empty string.</dd>
+<dt><strong>LLVM_ENABLE_LTO</strong>:STRING</dt>
+<dd>Add <code class="docutils literal"><span class="pre">-flto</span></code> or <code class="docutils literal"><span class="pre">-flto=</span></code> flags to the compile and link command
+lines, enabling link-time optimization. Possible values are <code class="docutils literal"><span class="pre">Off</span></code>,
+<code class="docutils literal"><span class="pre">On</span></code>, <code class="docutils literal"><span class="pre">Thin</span></code> and <code class="docutils literal"><span class="pre">Full</span></code>. Defaults to OFF.</dd>
+<dt><strong>LLVM_USE_LINKER</strong>:STRING</dt>
+<dd>Add <code class="docutils literal"><span class="pre">-fuse-ld={name}</span></code> to the link invocation. The possible value depend on
+your compiler, for clang the value can be an absolute path to your custom
+linker, otherwise clang will prefix the name with <code class="docutils literal"><span class="pre">ld.</span></code> and apply its usual
+search. For example to link LLVM with the Gold linker, cmake can be invoked
+with <code class="docutils literal"><span class="pre">-DLLVM_USE_LINKER=gold</span></code>.</dd>
+<dt><strong>LLVM_ENABLE_LLD</strong>:BOOL</dt>
+<dd>This option is equivalent to <cite>-DLLVM_USE_LINKER=lld</cite>, except during a 2-stage
+build where a dependency is added from the first stage to the second ensuring
+that lld is built before stage2 begins.</dd>
+<dt><strong>LLVM_PARALLEL_COMPILE_JOBS</strong>:STRING</dt>
+<dd>Define the maximum number of concurrent compilation jobs.</dd>
+<dt><strong>LLVM_PARALLEL_LINK_JOBS</strong>:STRING</dt>
+<dd>Define the maximum number of concurrent link jobs.</dd>
+<dt><strong>LLVM_BUILD_DOCS</strong>:BOOL</dt>
+<dd>Adds all <em>enabled</em> documentation targets (i.e. Doxgyen and Sphinx targets) as
+dependencies of the default build targets.  This results in all of the (enabled)
+documentation targets being as part of a normal build.  If the <code class="docutils literal"><span class="pre">install</span></code>
+target is run then this also enables all built documentation targets to be
+installed. Defaults to OFF.  To enable a particular documentation target, see
+see LLVM_ENABLE_SPHINX and LLVM_ENABLE_DOXYGEN.</dd>
+<dt><strong>LLVM_ENABLE_DOXYGEN</strong>:BOOL</dt>
+<dd>Enables the generation of browsable HTML documentation using doxygen.
+Defaults to OFF.</dd>
+<dt><strong>LLVM_ENABLE_DOXYGEN_QT_HELP</strong>:BOOL</dt>
+<dd>Enables the generation of a Qt Compressed Help file. Defaults to OFF.
+This affects the make target <code class="docutils literal"><span class="pre">doxygen-llvm</span></code>. When enabled, apart from
+the normal HTML output generated by doxygen, this will produce a QCH file
+named <code class="docutils literal"><span class="pre">org.llvm.qch</span></code>. You can then load this file into Qt Creator.
+This option is only useful in combination with <code class="docutils literal"><span class="pre">-DLLVM_ENABLE_DOXYGEN=ON</span></code>;
+otherwise this has no effect.</dd>
+<dt><strong>LLVM_DOXYGEN_QCH_FILENAME</strong>:STRING</dt>
+<dd>The filename of the Qt Compressed Help file that will be generated when
+<code class="docutils literal"><span class="pre">-DLLVM_ENABLE_DOXYGEN=ON</span></code> and
+<code class="docutils literal"><span class="pre">-DLLVM_ENABLE_DOXYGEN_QT_HELP=ON</span></code> are given. Defaults to
+<code class="docutils literal"><span class="pre">org.llvm.qch</span></code>.
+This option is only useful in combination with
+<code class="docutils literal"><span class="pre">-DLLVM_ENABLE_DOXYGEN_QT_HELP=ON</span></code>;
+otherwise it has no effect.</dd>
+<dt><strong>LLVM_DOXYGEN_QHP_NAMESPACE</strong>:STRING</dt>
+<dd>Namespace under which the intermediate Qt Help Project file lives. See <a class="reference external" href="http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-filters">Qt
+Help Project</a>
+for more information. Defaults to “org.llvm”. This option is only useful in
+combination with <code class="docutils literal"><span class="pre">-DLLVM_ENABLE_DOXYGEN_QT_HELP=ON</span></code>; otherwise
+it has no effect.</dd>
+<dt><strong>LLVM_DOXYGEN_QHP_CUST_FILTER_NAME</strong>:STRING</dt>
+<dd>See <a class="reference external" href="http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-filters">Qt Help Project</a> for
+more information. Defaults to the CMake variable <code class="docutils literal"><span class="pre">${PACKAGE_STRING}</span></code> which
+is a combination of the package name and version string. This filter can then
+be used in Qt Creator to select only documentation from LLVM when browsing
+through all the help files that you might have loaded. This option is only
+useful in combination with <code class="docutils literal"><span class="pre">-DLLVM_ENABLE_DOXYGEN_QT_HELP=ON</span></code>;
+otherwise it has no effect.</dd>
+</dl>
+<dl class="docutils">
+<dt><strong>LLVM_DOXYGEN_QHELPGENERATOR_PATH</strong>:STRING</dt>
+<dd>The path to the <code class="docutils literal"><span class="pre">qhelpgenerator</span></code> executable. Defaults to whatever CMake’s
+<code class="docutils literal"><span class="pre">find_program()</span></code> can find. This option is only useful in combination with
+<code class="docutils literal"><span class="pre">-DLLVM_ENABLE_DOXYGEN_QT_HELP=ON</span></code>; otherwise it has no
+effect.</dd>
+<dt><strong>LLVM_DOXYGEN_SVG</strong>:BOOL</dt>
+<dd>Uses .svg files instead of .png files for graphs in the Doxygen output.
+Defaults to OFF.</dd>
+<dt><strong>LLVM_INSTALL_DOXYGEN_HTML_DIR</strong>:STRING</dt>
+<dd>The path to install Doxygen-generated HTML documentation to. This path can
+either be absolute or relative to the CMAKE_INSTALL_PREFIX. Defaults to
+<cite>share/doc/llvm/doxygen-html</cite>.</dd>
+<dt><strong>LLVM_ENABLE_SPHINX</strong>:BOOL</dt>
+<dd>If specified, CMake will search for the <code class="docutils literal"><span class="pre">sphinx-build</span></code> executable and will make
+the <code class="docutils literal"><span class="pre">SPHINX_OUTPUT_HTML</span></code> and <code class="docutils literal"><span class="pre">SPHINX_OUTPUT_MAN</span></code> CMake options available.
+Defaults to OFF.</dd>
+<dt><strong>SPHINX_EXECUTABLE</strong>:STRING</dt>
+<dd>The path to the <code class="docutils literal"><span class="pre">sphinx-build</span></code> executable detected by CMake.
+For installation instructions, see
+<a class="reference external" href="http://www.sphinx-doc.org/en/latest/install.html">http://www.sphinx-doc.org/en/latest/install.html</a></dd>
+<dt><strong>SPHINX_OUTPUT_HTML</strong>:BOOL</dt>
+<dd>If enabled (and <code class="docutils literal"><span class="pre">LLVM_ENABLE_SPHINX</span></code> is enabled) then the targets for
+building the documentation as html are added (but not built by default unless
+<code class="docutils literal"><span class="pre">LLVM_BUILD_DOCS</span></code> is enabled). There is a target for each project in the
+source tree that uses sphinx (e.g.  <code class="docutils literal"><span class="pre">docs-llvm-html</span></code>, <code class="docutils literal"><span class="pre">docs-clang-html</span></code>
+and <code class="docutils literal"><span class="pre">docs-lld-html</span></code>). Defaults to ON.</dd>
+<dt><strong>SPHINX_OUTPUT_MAN</strong>:BOOL</dt>
+<dd>If enabled (and <code class="docutils literal"><span class="pre">LLVM_ENABLE_SPHINX</span></code> is enabled) the targets for building
+the man pages are added (but not built by default unless <code class="docutils literal"><span class="pre">LLVM_BUILD_DOCS</span></code>
+is enabled). Currently the only target added is <code class="docutils literal"><span class="pre">docs-llvm-man</span></code>. Defaults
+to ON.</dd>
+<dt><strong>SPHINX_WARNINGS_AS_ERRORS</strong>:BOOL</dt>
+<dd>If enabled then sphinx documentation warnings will be treated as
+errors. Defaults to ON.</dd>
+<dt><strong>LLVM_INSTALL_SPHINX_HTML_DIR</strong>:STRING</dt>
+<dd>The path to install Sphinx-generated HTML documentation to. This path can
+either be absolute or relative to the CMAKE_INSTALL_PREFIX. Defaults to
+<cite>share/doc/llvm/html</cite>.</dd>
+<dt><strong>LLVM_INSTALL_OCAMLDOC_HTML_DIR</strong>:STRING</dt>
+<dd>The path to install OCamldoc-generated HTML documentation to. This path can
+either be absolute or relative to the CMAKE_INSTALL_PREFIX. Defaults to
+<cite>share/doc/llvm/ocaml-html</cite>.</dd>
+<dt><strong>LLVM_CREATE_XCODE_TOOLCHAIN</strong>:BOOL</dt>
+<dd>OS X Only: If enabled CMake will generate a target named
+‘install-xcode-toolchain’. This target will create a directory at
+$CMAKE_INSTALL_PREFIX/Toolchains containing an xctoolchain directory which can
+be used to override the default system tools.</dd>
+<dt><strong>LLVM_BUILD_LLVM_DYLIB</strong>:BOOL</dt>
+<dd>If enabled, the target for building the libLLVM shared library is added.
+This library contains all of LLVM’s components in a single shared library.
+Defaults to OFF. This cannot be used in conjunction with BUILD_SHARED_LIBS.
+Tools will only be linked to the libLLVM shared library if LLVM_LINK_LLVM_DYLIB
+is also ON.
+The components in the library can be customised by setting LLVM_DYLIB_COMPONENTS
+to a list of the desired components.</dd>
+<dt><strong>LLVM_LINK_LLVM_DYLIB</strong>:BOOL</dt>
+<dd>If enabled, tools will be linked with the libLLVM shared library. Defaults
+to OFF. Setting LLVM_LINK_LLVM_DYLIB to ON also sets LLVM_BUILD_LLVM_DYLIB
+to ON.</dd>
+<dt><strong>BUILD_SHARED_LIBS</strong>:BOOL</dt>
+<dd><p class="first">Flag indicating if each LLVM component (e.g. Support) is built as a shared
+library (ON) or as a static library (OFF). Its default value is OFF. On
+Windows, shared libraries may be used when building with MinGW, including
+mingw-w64, but not when building with the Microsoft toolchain.</p>
+<div class="last admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">BUILD_SHARED_LIBS is only recommended for use by LLVM developers.
+If you want to build LLVM as a shared library, you should use the
+<code class="docutils literal"><span class="pre">LLVM_BUILD_LLVM_DYLIB</span></code> option.</p>
+</div>
+</dd>
+<dt><strong>LLVM_OPTIMIZED_TABLEGEN</strong>:BOOL</dt>
+<dd>If enabled and building a debug or asserts build the CMake build system will
+generate a Release build tree to build a fully optimized tablegen for use
+during the build. Enabling this option can significantly speed up build times
+especially when building LLVM in Debug configurations.</dd>
+<dt><strong>LLVM_REVERSE_ITERATION</strong>:BOOL</dt>
+<dd>If enabled, all supported unordered llvm containers would be iterated in
+reverse order. This is useful for uncovering non-determinism caused by
+iteration of unordered containers.</dd>
+<dt><strong>LLVM_BUILD_INSTRUMENTED_COVERAGE</strong>:BOOL</dt>
+<dd>If enabled, <a class="reference external" href="http://clang.llvm.org/docs/SourceBasedCodeCoverage.html">source-based code coverage</a> instrumentation
+is enabled while building llvm.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="cmake-caches">
+<h2><a class="toc-backref" href="#id11">CMake Caches</a><a class="headerlink" href="#cmake-caches" title="Permalink to this headline">¶</a></h2>
+<p>Recently LLVM and Clang have been adding some more complicated build system
+features. Utilizing these new features often involves a complicated chain of
+CMake variables passed on the command line. Clang provides a collection of CMake
+cache scripts to make these features more approachable.</p>
+<p>CMake cache files are utilized using CMake’s -C flag:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -C <path to cache file> <path to sources>
+</pre></div>
+</div>
+<p>CMake cache scripts are processed in an isolated scope, only cached variables
+remain set when the main configuration runs. CMake cached variables do not reset
+variables that are already set unless the FORCE option is specified.</p>
+<p>A few notes about CMake Caches:</p>
+<ul class="simple">
+<li>Order of command line arguments is important<ul>
+<li>-D arguments specified before -C are set before the cache is processed and
+can be read inside the cache file</li>
+<li>-D arguments specified after -C are set after the cache is processed and
+are unset inside the cache file</li>
+</ul>
+</li>
+<li>All -D arguments will override cache file settings</li>
+<li>CMAKE_TOOLCHAIN_FILE is evaluated after both the cache file and the command
+line arguments</li>
+<li>It is recommended that all -D options should be specified <em>before</em> -C</li>
+</ul>
+<p>For more information about some of the advanced build configurations supported
+via Cache files see <a class="reference internal" href="AdvancedBuilds.html"><span class="doc">Advanced Build Configurations</span></a>.</p>
+</div>
+<div class="section" id="executing-the-test-suite">
+<h2><a class="toc-backref" href="#id12">Executing the test suite</a><a class="headerlink" href="#executing-the-test-suite" title="Permalink to this headline">¶</a></h2>
+<p>Testing is performed when the <em>check-all</em> target is built. For instance, if you are
+using Makefiles, execute this command in the root of your build directory:</p>
+<div class="highlight-console"><div class="highlight"><pre><span></span><span class="gp">$</span> make check-all
+</pre></div>
+</div>
+<p>On Visual Studio, you may run tests by building the project “check-all”.
+For more information about testing, see the <a class="reference internal" href="TestingGuide.html"><span class="doc">LLVM Testing Infrastructure Guide</span></a>.</p>
+</div>
+<div class="section" id="cross-compiling">
+<h2><a class="toc-backref" href="#id13">Cross compiling</a><a class="headerlink" href="#cross-compiling" title="Permalink to this headline">¶</a></h2>
+<p>See <a class="reference external" href="http://www.vtk.org/Wiki/CMake_Cross_Compiling">this wiki page</a> for
+generic instructions on how to cross-compile with CMake. It goes into detailed
+explanations and may seem daunting, but it is not. On the wiki page there are
+several examples including toolchain files. Go directly to <a class="reference external" href="http://www.vtk.org/Wiki/CMake_Cross_Compiling#Information_how_to_set_up_various_cross_compiling_toolchains">this section</a>
+for a quick solution.</p>
+<p>Also see the <a class="reference internal" href="#llvm-specific-variables">LLVM-specific variables</a> section for variables used when
+cross-compiling.</p>
+</div>
+<div class="section" id="embedding-llvm-in-your-project">
+<h2><a class="toc-backref" href="#id14">Embedding LLVM in your project</a><a class="headerlink" href="#embedding-llvm-in-your-project" title="Permalink to this headline">¶</a></h2>
+<p>From LLVM 3.5 onwards both the CMake and autoconf/Makefile build systems export
+LLVM libraries as importable CMake targets. This means that clients of LLVM can
+now reliably use CMake to develop their own LLVM-based projects against an
+installed version of LLVM regardless of how it was built.</p>
+<p>Here is a simple example of a CMakeLists.txt file that imports the LLVM libraries
+and uses them to build a simple application <code class="docutils literal"><span class="pre">simple-tool</span></code>.</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">cmake_minimum_required</span><span class="p">(</span><span class="s">VERSION</span> <span class="s">3.4.3</span><span class="p">)</span>
+<span class="nb">project</span><span class="p">(</span><span class="s">SimpleProject</span><span class="p">)</span>
+
+<span class="nb">find_package</span><span class="p">(</span><span class="s">LLVM</span> <span class="s">REQUIRED</span> <span class="s">CONFIG</span><span class="p">)</span>
+
+<span class="nb">message</span><span class="p">(</span><span class="s">STATUS</span> <span class="s2">"Found LLVM ${LLVM_PACKAGE_VERSION}"</span><span class="p">)</span>
+<span class="nb">message</span><span class="p">(</span><span class="s">STATUS</span> <span class="s2">"Using LLVMConfig.cmake in: ${LLVM_DIR}"</span><span class="p">)</span>
+
+<span class="c"># Set your project compile flags.</span>
+<span class="c"># E.g. if using the C++ header files</span>
+<span class="c"># you will need to enable C++11 support</span>
+<span class="c"># for your compiler.</span>
+
+<span class="nb">include_directories</span><span class="p">(</span><span class="o">${</span><span class="nv">LLVM_INCLUDE_DIRS</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">add_definitions</span><span class="p">(</span><span class="o">${</span><span class="nv">LLVM_DEFINITIONS</span><span class="o">}</span><span class="p">)</span>
+
+<span class="c"># Now build our tools</span>
+<span class="nb">add_executable</span><span class="p">(</span><span class="s">simple-tool</span> <span class="s">tool.cpp</span><span class="p">)</span>
+
+<span class="c"># Find the libraries that correspond to the LLVM components</span>
+<span class="c"># that we wish to use</span>
+<span class="nb">llvm_map_components_to_libnames</span><span class="p">(</span><span class="s">llvm_libs</span> <span class="s">support</span> <span class="s">core</span> <span class="s">irreader</span><span class="p">)</span>
+
+<span class="c"># Link against LLVM libraries</span>
+<span class="nb">target_link_libraries</span><span class="p">(</span><span class="s">simple-tool</span> <span class="o">${</span><span class="nv">llvm_libs</span><span class="o">}</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>The <code class="docutils literal"><span class="pre">find_package(...)</span></code> directive when used in CONFIG mode (as in the above
+example) will look for the <code class="docutils literal"><span class="pre">LLVMConfig.cmake</span></code> file in various locations (see
+cmake manual for details).  It creates a <code class="docutils literal"><span class="pre">LLVM_DIR</span></code> cache entry to save the
+directory where <code class="docutils literal"><span class="pre">LLVMConfig.cmake</span></code> is found or allows the user to specify the
+directory (e.g. by passing <code class="docutils literal"><span class="pre">-DLLVM_DIR=/usr/lib/cmake/llvm</span></code> to
+the <code class="docutils literal"><span class="pre">cmake</span></code> command or by setting it directly in <code class="docutils literal"><span class="pre">ccmake</span></code> or <code class="docutils literal"><span class="pre">cmake-gui</span></code>).</p>
+<p>This file is available in two different locations.</p>
+<ul class="simple">
+<li><code class="docutils literal"><span class="pre"><INSTALL_PREFIX>/lib/cmake/llvm/LLVMConfig.cmake</span></code> where
+<code class="docutils literal"><span class="pre"><INSTALL_PREFIX></span></code> is the install prefix of an installed version of LLVM.
+On Linux typically this is <code class="docutils literal"><span class="pre">/usr/lib/cmake/llvm/LLVMConfig.cmake</span></code>.</li>
+<li><code class="docutils literal"><span class="pre"><LLVM_BUILD_ROOT>/lib/cmake/llvm/LLVMConfig.cmake</span></code> where
+<code class="docutils literal"><span class="pre"><LLVM_BUILD_ROOT></span></code> is the root of the LLVM build tree. <strong>Note: this is only
+available when building LLVM with CMake.</strong></li>
+</ul>
+<p>If LLVM is installed in your operating system’s normal installation prefix (e.g.
+on Linux this is usually <code class="docutils literal"><span class="pre">/usr/</span></code>) <code class="docutils literal"><span class="pre">find_package(LLVM</span> <span class="pre">...)</span></code> will
+automatically find LLVM if it is installed correctly. If LLVM is not installed
+or you wish to build directly against the LLVM build tree you can use
+<code class="docutils literal"><span class="pre">LLVM_DIR</span></code> as previously mentioned.</p>
+<p>The <code class="docutils literal"><span class="pre">LLVMConfig.cmake</span></code> file sets various useful variables. Notable variables
+include</p>
+<dl class="docutils">
+<dt><code class="docutils literal"><span class="pre">LLVM_CMAKE_DIR</span></code></dt>
+<dd>The path to the LLVM CMake directory (i.e. the directory containing
+LLVMConfig.cmake).</dd>
+<dt><code class="docutils literal"><span class="pre">LLVM_DEFINITIONS</span></code></dt>
+<dd>A list of preprocessor defines that should be used when building against LLVM.</dd>
+<dt><code class="docutils literal"><span class="pre">LLVM_ENABLE_ASSERTIONS</span></code></dt>
+<dd>This is set to ON if LLVM was built with assertions, otherwise OFF.</dd>
+<dt><code class="docutils literal"><span class="pre">LLVM_ENABLE_EH</span></code></dt>
+<dd>This is set to ON if LLVM was built with exception handling (EH) enabled,
+otherwise OFF.</dd>
+<dt><code class="docutils literal"><span class="pre">LLVM_ENABLE_RTTI</span></code></dt>
+<dd>This is set to ON if LLVM was built with run time type information (RTTI),
+otherwise OFF.</dd>
+<dt><code class="docutils literal"><span class="pre">LLVM_INCLUDE_DIRS</span></code></dt>
+<dd>A list of include paths to directories containing LLVM header files.</dd>
+<dt><code class="docutils literal"><span class="pre">LLVM_PACKAGE_VERSION</span></code></dt>
+<dd>The LLVM version. This string can be used with CMake conditionals, e.g., <code class="docutils literal"><span class="pre">if</span>
+<span class="pre">(${LLVM_PACKAGE_VERSION}</span> <span class="pre">VERSION_LESS</span> <span class="pre">"3.5")</span></code>.</dd>
+<dt><code class="docutils literal"><span class="pre">LLVM_TOOLS_BINARY_DIR</span></code></dt>
+<dd>The path to the directory containing the LLVM tools (e.g. <code class="docutils literal"><span class="pre">llvm-as</span></code>).</dd>
+</dl>
+<p>Notice that in the above example we link <code class="docutils literal"><span class="pre">simple-tool</span></code> against several LLVM
+libraries. The list of libraries is determined by using the
+<code class="docutils literal"><span class="pre">llvm_map_components_to_libnames()</span></code> CMake function. For a list of available
+components look at the output of running <code class="docutils literal"><span class="pre">llvm-config</span> <span class="pre">--components</span></code>.</p>
+<p>Note that for LLVM < 3.5 <code class="docutils literal"><span class="pre">llvm_map_components_to_libraries()</span></code> was
+used instead of <code class="docutils literal"><span class="pre">llvm_map_components_to_libnames()</span></code>. This is now deprecated
+and will be removed in a future version of LLVM.</p>
+<div class="section" id="developing-llvm-passes-out-of-source">
+<span id="cmake-out-of-source-pass"></span><h3><a class="toc-backref" href="#id15">Developing LLVM passes out of source</a><a class="headerlink" href="#developing-llvm-passes-out-of-source" title="Permalink to this headline">¶</a></h3>
+<p>It is possible to develop LLVM passes out of LLVM’s source tree (i.e. against an
+installed or built LLVM). An example of a project layout is provided below.</p>
+<div class="highlight-none"><div class="highlight"><pre><span></span><project dir>/
+    |
+    CMakeLists.txt
+    <pass name>/
+        |
+        CMakeLists.txt
+        Pass.cpp
+        ...
+</pre></div>
+</div>
+<p>Contents of <code class="docutils literal"><span class="pre"><project</span> <span class="pre">dir>/CMakeLists.txt</span></code>:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">find_package</span><span class="p">(</span><span class="s">LLVM</span> <span class="s">REQUIRED</span> <span class="s">CONFIG</span><span class="p">)</span>
+
+<span class="nb">add_definitions</span><span class="p">(</span><span class="o">${</span><span class="nv">LLVM_DEFINITIONS</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">include_directories</span><span class="p">(</span><span class="o">${</span><span class="nv">LLVM_INCLUDE_DIRS</span><span class="o">}</span><span class="p">)</span>
+
+<span class="nb">add_subdirectory</span><span class="p">(</span><span class="s"><pass</span> <span class="s">name></span><span class="p">)</span>
+</pre></div>
+</div>
+<p>Contents of <code class="docutils literal"><span class="pre"><project</span> <span class="pre">dir>/<pass</span> <span class="pre">name>/CMakeLists.txt</span></code>:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">add_library</span><span class="p">(</span><span class="s">LLVMPassname</span> <span class="s">MODULE</span> <span class="s">Pass.cpp</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>Note if you intend for this pass to be merged into the LLVM source tree at some
+point in the future it might make more sense to use LLVM’s internal
+<code class="docutils literal"><span class="pre">add_llvm_loadable_module</span></code> function instead by...</p>
+<p>Adding the following to <code class="docutils literal"><span class="pre"><project</span> <span class="pre">dir>/CMakeLists.txt</span></code> (after
+<code class="docutils literal"><span class="pre">find_package(LLVM</span> <span class="pre">...)</span></code>)</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">list</span><span class="p">(</span><span class="s">APPEND</span> <span class="s">CMAKE_MODULE_PATH</span> <span class="s2">"${LLVM_CMAKE_DIR}"</span><span class="p">)</span>
+<span class="nb">include</span><span class="p">(</span><span class="s">AddLLVM</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>And then changing <code class="docutils literal"><span class="pre"><project</span> <span class="pre">dir>/<pass</span> <span class="pre">name>/CMakeLists.txt</span></code> to</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">add_llvm_loadable_module</span><span class="p">(</span><span class="s">LLVMPassname</span>
+  <span class="s">Pass.cpp</span>
+  <span class="p">)</span>
+</pre></div>
+</div>
+<p>When you are done developing your pass, you may wish to integrate it
+into the LLVM source tree. You can achieve it in two easy steps:</p>
+<ol class="arabic simple">
+<li>Copying <code class="docutils literal"><span class="pre"><pass</span> <span class="pre">name></span></code> folder into <code class="docutils literal"><span class="pre"><LLVM</span> <span class="pre">root>/lib/Transform</span></code> directory.</li>
+<li>Adding <code class="docutils literal"><span class="pre">add_subdirectory(<pass</span> <span class="pre">name>)</span></code> line into
+<code class="docutils literal"><span class="pre"><LLVM</span> <span class="pre">root>/lib/Transform/CMakeLists.txt</span></code>.</li>
+</ol>
+</div>
+</div>
+<div class="section" id="compiler-platform-specific-topics">
+<h2><a class="toc-backref" href="#id16">Compiler/Platform-specific topics</a><a class="headerlink" href="#compiler-platform-specific-topics" title="Permalink to this headline">¶</a></h2>
+<p>Notes for specific compilers and/or platforms.</p>
+<div class="section" id="microsoft-visual-c">
+<h3><a class="toc-backref" href="#id17">Microsoft Visual C++</a><a class="headerlink" href="#microsoft-visual-c" title="Permalink to this headline">¶</a></h3>
+<dl class="docutils">
+<dt><strong>LLVM_COMPILER_JOBS</strong>:STRING</dt>
+<dd>Specifies the maximum number of parallel compiler jobs to use per project
+when building with msbuild or Visual Studio. Only supported for the Visual
+Studio 2010 CMake generator. 0 means use all processors. Default is 0.</dd>
+</dl>
+</div>
+</div>
+</div>
+
+
+          </div>
+      </div>
+      <div class="clearer"></div>
+    </div>
+    <div class="related" role="navigation" aria-label="related navigation">
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+    <div class="document">
+      <div class="documentwrapper">
+          <div class="body" role="main">
+            
+  <div class="section" id="cmake-primer">
+<h1>CMake Primer<a class="headerlink" href="#cmake-primer" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#ft-view" id="id2">10,000 ft View</a></li>
+<li><a class="reference internal" href="#scripting-overview" id="id3">Scripting Overview</a></li>
+<li><a class="reference internal" href="#variables-types-and-scope" id="id4">Variables, Types, and Scope</a><ul>
+<li><a class="reference internal" href="#dereferencing" id="id5">Dereferencing</a></li>
+<li><a class="reference internal" href="#lists" id="id6">Lists</a></li>
+<li><a class="reference internal" href="#lists-of-lists" id="id7">Lists of Lists</a></li>
+<li><a class="reference internal" href="#other-types" id="id8">Other Types</a></li>
+<li><a class="reference internal" href="#scope" id="id9">Scope</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#control-flow" id="id10">Control Flow</a><ul>
+<li><a class="reference internal" href="#if-elseif-else" id="id11">If, ElseIf, Else</a></li>
+<li><a class="reference internal" href="#loops" id="id12">Loops</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#modules-functions-and-macros" id="id13">Modules, Functions and Macros</a><ul>
+<li><a class="reference internal" href="#modules" id="id14">Modules</a></li>
+<li><a class="reference internal" href="#argument-handling" id="id15">Argument Handling</a></li>
+<li><a class="reference internal" href="#functions-vs-macros" id="id16">Functions Vs Macros</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#llvm-project-wrappers" id="id17">LLVM Project Wrappers</a></li>
+<li><a class="reference internal" href="#useful-built-in-commands" id="id18">Useful Built-in Commands</a></li>
+</ul>
+</div>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Disclaimer: This documentation is written by LLVM project contributors <cite>not</cite>
+anyone affiliated with the CMake project. This document may contain
+inaccurate terminology, phrasing, or technical details. It is provided with
+the best intentions.</p>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>The LLVM project and many of the core projects built on LLVM build using CMake.
+This document aims to provide a brief overview of CMake for developers modifying
+LLVM projects or building their own projects on top of LLVM.</p>
+<p>The official CMake language references is available in the cmake-language
+manpage and <a class="reference external" href="https://cmake.org/cmake/help/v3.4/manual/cmake-language.7.html">cmake-language online documentation</a>.</p>
+</div>
+<div class="section" id="ft-view">
+<h2><a class="toc-backref" href="#id2">10,000 ft View</a><a class="headerlink" href="#ft-view" title="Permalink to this headline">¶</a></h2>
+<p>CMake is a tool that reads script files in its own language that describe how a
+software project builds. As CMake evaluates the scripts it constructs an
+internal representation of the software project. Once the scripts have been
+fully processed, if there are no errors, CMake will generate build files to
+actually build the project. CMake supports generating build files for a variety
+of command line build tools as well as for popular IDEs.</p>
+<p>When a user runs CMake it performs a variety of checks similar to how autoconf
+worked historically. During the checks and the evaluation of the build
+description scripts CMake caches values into the CMakeCache. This is useful
+because it allows the build system to skip long-running checks during
+incremental development. CMake caching also has some drawbacks, but that will be
+discussed later.</p>
+</div>
+<div class="section" id="scripting-overview">
+<h2><a class="toc-backref" href="#id3">Scripting Overview</a><a class="headerlink" href="#scripting-overview" title="Permalink to this headline">¶</a></h2>
+<p>CMake’s scripting language has a very simple grammar. Every language construct
+is a command that matches the pattern _name_(_args_). Commands come in three
+primary types: language-defined (commands implemented in C++ in CMake), defined
+functions, and defined macros. The CMake distribution also contains a suite of
+CMake modules that contain definitions for useful functionality.</p>
+<p>The example below is the full CMake build for building a C++ “Hello World”
+program. The example uses only CMake language-defined functions.</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">cmake_minimum_required</span><span class="p">(</span><span class="s">VERSION</span> <span class="s">3.2</span><span class="p">)</span>
+<span class="nb">project</span><span class="p">(</span><span class="s">HelloWorld</span><span class="p">)</span>
+<span class="nb">add_executable</span><span class="p">(</span><span class="s">HelloWorld</span> <span class="s">HelloWorld.cpp</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>The CMake language provides control flow constructs in the form of foreach loops
+and if blocks. To make the example above more complicated you could add an if
+block to define “APPLE” when targeting Apple platforms:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">cmake_minimum_required</span><span class="p">(</span><span class="s">VERSION</span> <span class="s">3.2</span><span class="p">)</span>
+<span class="nb">project</span><span class="p">(</span><span class="s">HelloWorld</span><span class="p">)</span>
+<span class="nb">add_executable</span><span class="p">(</span><span class="s">HelloWorld</span> <span class="s">HelloWorld.cpp</span><span class="p">)</span>
+<span class="nb">if</span><span class="p">(</span><span class="s">APPLE</span><span class="p">)</span>
+  <span class="nb">target_compile_definitions</span><span class="p">(</span><span class="s">HelloWorld</span> <span class="s">PUBLIC</span> <span class="s">APPLE</span><span class="p">)</span>
+<span class="nb">endif</span><span class="p">()</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="variables-types-and-scope">
+<h2><a class="toc-backref" href="#id4">Variables, Types, and Scope</a><a class="headerlink" href="#variables-types-and-scope" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="dereferencing">
+<h3><a class="toc-backref" href="#id5">Dereferencing</a><a class="headerlink" href="#dereferencing" title="Permalink to this headline">¶</a></h3>
+<p>In CMake variables are “stringly” typed. All variables are represented as
+strings throughout evaluation. Wrapping a variable in <code class="docutils literal"><span class="pre">${}</span></code> dereferences it
+and results in a literal substitution of the name for the value. CMake refers to
+this as “variable evaluation” in their documentation. Dereferences are performed
+<em>before</em> the command being called receives the arguments. This means
+dereferencing a list results in multiple separate arguments being passed to the
+command.</p>
+<p>Variable dereferences can be nested and be used to model complex data. For
+example:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">set</span><span class="p">(</span><span class="s">var_name</span> <span class="s">var1</span><span class="p">)</span>
+<span class="nb">set</span><span class="p">(</span><span class="o">${</span><span class="nv">var_name</span><span class="o">}</span> <span class="s">foo</span><span class="p">)</span> <span class="c"># same as "set(var1 foo)"</span>
+<span class="nb">set</span><span class="p">(</span><span class="o">${</span><span class="nv">${var_name</span><span class="o">}</span><span class="s">}_var</span> <span class="s">bar</span><span class="p">)</span> <span class="c"># same as "set(foo_var bar)"</span>
+</pre></div>
+</div>
+<p>Dereferencing an unset variable results in an empty expansion. It is a common
+pattern in CMake to conditionally set variables knowing that it will be used in
+code paths that the variable isn’t set. There are examples of this throughout
+the LLVM CMake build system.</p>
+<p>An example of variable empty expansion is:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">if</span><span class="p">(</span><span class="s">APPLE</span><span class="p">)</span>
+  <span class="nb">set</span><span class="p">(</span><span class="s">extra_sources</span> <span class="s">Apple.cpp</span><span class="p">)</span>
+<span class="nb">endif</span><span class="p">()</span>
+<span class="nb">add_executable</span><span class="p">(</span><span class="s">HelloWorld</span> <span class="s">HelloWorld.cpp</span> <span class="o">${</span><span class="nv">extra_sources</span><span class="o">}</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>In this example the <code class="docutils literal"><span class="pre">extra_sources</span></code> variable is only defined if you’re
+targeting an Apple platform. For all other targets the <code class="docutils literal"><span class="pre">extra_sources</span></code> will be
+evaluated as empty before add_executable is given its arguments.</p>
+</div>
+<div class="section" id="lists">
+<h3><a class="toc-backref" href="#id6">Lists</a><a class="headerlink" href="#lists" title="Permalink to this headline">¶</a></h3>
+<p>In CMake lists are semi-colon delimited strings, and it is strongly advised that
+you avoid using semi-colons in lists; it doesn’t go smoothly. A few examples of
+defining lists:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="c"># Creates a list with members a, b, c, and d</span>
+<span class="nb">set</span><span class="p">(</span><span class="s">my_list</span> <span class="s">a</span> <span class="s">b</span> <span class="s">c</span> <span class="s">d</span><span class="p">)</span>
+<span class="nb">set</span><span class="p">(</span><span class="s">my_list</span> <span class="s2">"a;b;c;d"</span><span class="p">)</span>
+
+<span class="c"># Creates a string "a b c d"</span>
+<span class="nb">set</span><span class="p">(</span><span class="s">my_string</span> <span class="s2">"a b c d"</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="lists-of-lists">
+<h3><a class="toc-backref" href="#id7">Lists of Lists</a><a class="headerlink" href="#lists-of-lists" title="Permalink to this headline">¶</a></h3>
+<p>One of the more complicated patterns in CMake is lists of lists. Because a list
+cannot contain an element with a semi-colon to construct a list of lists you
+make a list of variable names that refer to other lists. For example:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">set</span><span class="p">(</span><span class="s">list_of_lists</span> <span class="s">a</span> <span class="s">b</span> <span class="s">c</span><span class="p">)</span>
+<span class="nb">set</span><span class="p">(</span><span class="s">a</span> <span class="s">1</span> <span class="s">2</span> <span class="s">3</span><span class="p">)</span>
+<span class="nb">set</span><span class="p">(</span><span class="s">b</span> <span class="s">4</span> <span class="s">5</span> <span class="s">6</span><span class="p">)</span>
+<span class="nb">set</span><span class="p">(</span><span class="s">c</span> <span class="s">7</span> <span class="s">8</span> <span class="s">9</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>With this layout you can iterate through the list of lists printing each value
+with the following code:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">foreach</span><span class="p">(</span><span class="s">list_name</span> <span class="s">IN</span> <span class="s">LISTS</span> <span class="s">list_of_lists</span><span class="p">)</span>
+  <span class="nb">foreach</span><span class="p">(</span><span class="s">value</span> <span class="s">IN</span> <span class="s">LISTS</span> <span class="o">${</span><span class="nv">list_name</span><span class="o">}</span><span class="p">)</span>
+    <span class="nb">message</span><span class="p">(</span><span class="o">${</span><span class="nv">value</span><span class="o">}</span><span class="p">)</span>
+  <span class="nb">endforeach</span><span class="p">()</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+</pre></div>
+</div>
+<p>You’ll notice that the inner foreach loop’s list is doubly dereferenced. This is
+because the first dereference turns <code class="docutils literal"><span class="pre">list_name</span></code> into the name of the sub-list
+(a, b, or c in the example), then the second dereference is to get the value of
+the list.</p>
+<p>This pattern is used throughout CMake, the most common example is the compiler
+flags options, which CMake refers to using the following variable expansions:
+CMAKE_${LANGUAGE}_FLAGS and CMAKE_${LANGUAGE}_FLAGS_${CMAKE_BUILD_TYPE}.</p>
+</div>
+<div class="section" id="other-types">
+<h3><a class="toc-backref" href="#id8">Other Types</a><a class="headerlink" href="#other-types" title="Permalink to this headline">¶</a></h3>
+<p>Variables that are cached or specified on the command line can have types
+associated with them. The variable’s type is used by CMake’s UI tool to display
+the right input field. A variable’s type generally doesn’t impact evaluation,
+however CMake does have special handling for some variables such as PATH.
+You can read more about the special handling in <a class="reference external" href="https://cmake.org/cmake/help/v3.5/command/set.html#set-cache-entry">CMake’s set documentation</a>.</p>
+</div>
+<div class="section" id="scope">
+<h3><a class="toc-backref" href="#id9">Scope</a><a class="headerlink" href="#scope" title="Permalink to this headline">¶</a></h3>
+<p>CMake inherently has a directory-based scoping. Setting a variable in a
+CMakeLists file, will set the variable for that file, and all subdirectories.
+Variables set in a CMake module that is included in a CMakeLists file will be
+set in the scope they are included from, and all subdirectories.</p>
+<p>When a variable that is already set is set again in a subdirectory it overrides
+the value in that scope and any deeper subdirectories.</p>
+<p>The CMake set command provides two scope-related options. PARENT_SCOPE sets a
+variable into the parent scope, and not the current scope. The CACHE option sets
+the variable in the CMakeCache, which results in it being set in all scopes. The
+CACHE option will not set a variable that already exists in the CACHE unless the
+FORCE option is specified.</p>
+<p>In addition to directory-based scope, CMake functions also have their own scope.
+This means variables set inside functions do not bleed into the parent scope.
+This is not true of macros, and it is for this reason LLVM prefers functions
+over macros whenever reasonable.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">Unlike C-based languages, CMake’s loop and control flow blocks do not have
+their own scopes.</p>
+</div>
+</div>
+</div>
+<div class="section" id="control-flow">
+<h2><a class="toc-backref" href="#id10">Control Flow</a><a class="headerlink" href="#control-flow" title="Permalink to this headline">¶</a></h2>
+<p>CMake features the same basic control flow constructs you would expect in any
+scripting language, but there are a few quirks because, as with everything in
+CMake, control flow constructs are commands.</p>
+<div class="section" id="if-elseif-else">
+<h3><a class="toc-backref" href="#id11">If, ElseIf, Else</a><a class="headerlink" href="#if-elseif-else" title="Permalink to this headline">¶</a></h3>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">For the full documentation on the CMake if command go
+<a class="reference external" href="https://cmake.org/cmake/help/v3.4/command/if.html">here</a>. That resource is
+far more complete.</p>
+</div>
+<p>In general CMake if blocks work the way you’d expect:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">if</span><span class="p">(</span><span class="s"><condition></span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="s2">"do stuff"</span><span class="p">)</span>
+<span class="nb">elseif</span><span class="p">(</span><span class="s"><condition></span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="s2">"do other stuff"</span><span class="p">)</span>
+<span class="nb">else</span><span class="p">()</span>
+  <span class="nb">message</span><span class="p">(</span><span class="s2">"do other other stuff"</span><span class="p">)</span>
+<span class="nb">endif</span><span class="p">()</span>
+</pre></div>
+</div>
+<p>The single most important thing to know about CMake’s if blocks coming from a C
+background is that they do not have their own scope. Variables set inside
+conditional blocks persist after the <code class="docutils literal"><span class="pre">endif()</span></code>.</p>
+</div>
+<div class="section" id="loops">
+<h3><a class="toc-backref" href="#id12">Loops</a><a class="headerlink" href="#loops" title="Permalink to this headline">¶</a></h3>
+<p>The most common form of the CMake <code class="docutils literal"><span class="pre">foreach</span></code> block is:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="s">...</span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="s2">"do stuff"</span><span class="p">)</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+</pre></div>
+</div>
+<p>The variable argument portion of the <code class="docutils literal"><span class="pre">foreach</span></code> block can contain dereferenced
+lists, values to iterate, or a mix of both:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="s">foo</span> <span class="s">bar</span> <span class="s">baz</span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="o">${</span><span class="nv">var</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+<span class="c"># prints:</span>
+<span class="c">#  foo</span>
+<span class="c">#  bar</span>
+<span class="c">#  baz</span>
+
+<span class="nb">set</span><span class="p">(</span><span class="s">my_list</span> <span class="s">1</span> <span class="s">2</span> <span class="s">3</span><span class="p">)</span>
+<span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="o">${</span><span class="nv">my_list</span><span class="o">}</span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="o">${</span><span class="nv">var</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+<span class="c"># prints:</span>
+<span class="c">#  1</span>
+<span class="c">#  2</span>
+<span class="c">#  3</span>
+
+<span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="o">${</span><span class="nv">my_list</span><span class="o">}</span> <span class="s">out_of_bounds</span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="o">${</span><span class="nv">var</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+<span class="c"># prints:</span>
+<span class="c">#  1</span>
+<span class="c">#  2</span>
+<span class="c">#  3</span>
+<span class="c">#  out_of_bounds</span>
+</pre></div>
+</div>
+<p>There is also a more modern CMake foreach syntax. The code below is equivalent
+to the code above:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="s">IN</span> <span class="s">ITEMS</span> <span class="s">foo</span> <span class="s">bar</span> <span class="s">baz</span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="o">${</span><span class="nv">var</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+<span class="c"># prints:</span>
+<span class="c">#  foo</span>
+<span class="c">#  bar</span>
+<span class="c">#  baz</span>
+
+<span class="nb">set</span><span class="p">(</span><span class="s">my_list</span> <span class="s">1</span> <span class="s">2</span> <span class="s">3</span><span class="p">)</span>
+<span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="s">IN</span> <span class="s">LISTS</span> <span class="s">my_list</span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="o">${</span><span class="nv">var</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+<span class="c"># prints:</span>
+<span class="c">#  1</span>
+<span class="c">#  2</span>
+<span class="c">#  3</span>
+
+<span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="s">IN</span> <span class="s">LISTS</span> <span class="s">my_list</span> <span class="s">ITEMS</span> <span class="s">out_of_bounds</span><span class="p">)</span>
+  <span class="nb">message</span><span class="p">(</span><span class="o">${</span><span class="nv">var</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">endforeach</span><span class="p">()</span>
+<span class="c"># prints:</span>
+<span class="c">#  1</span>
+<span class="c">#  2</span>
+<span class="c">#  3</span>
+<span class="c">#  out_of_bounds</span>
+</pre></div>
+</div>
+<p>Similar to the conditional statements, these generally behave how you would
+expect, and they do not have their own scope.</p>
+<p>CMake also supports <code class="docutils literal"><span class="pre">while</span></code> loops, although they are not widely used in LLVM.</p>
+</div>
+</div>
+<div class="section" id="modules-functions-and-macros">
+<h2><a class="toc-backref" href="#id13">Modules, Functions and Macros</a><a class="headerlink" href="#modules-functions-and-macros" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="modules">
+<h3><a class="toc-backref" href="#id14">Modules</a><a class="headerlink" href="#modules" title="Permalink to this headline">¶</a></h3>
+<p>Modules are CMake’s vehicle for enabling code reuse. CMake modules are just
+CMake script files. They can contain code to execute on include as well as
+definitions for commands.</p>
+<p>In CMake macros and functions are universally referred to as commands, and they
+are the primary method of defining code that can be called multiple times.</p>
+<p>In LLVM we have several CMake modules that are included as part of our
+distribution for developers who don’t build our project from source. Those
+modules are the fundamental pieces needed to build LLVM-based projects with
+CMake. We also rely on modules as a way of organizing the build system’s
+functionality for maintainability and re-use within LLVM projects.</p>
+</div>
+<div class="section" id="argument-handling">
+<h3><a class="toc-backref" href="#id15">Argument Handling</a><a class="headerlink" href="#argument-handling" title="Permalink to this headline">¶</a></h3>
+<p>When defining a CMake command handling arguments is very useful. The examples
+in this section will all use the CMake <code class="docutils literal"><span class="pre">function</span></code> block, but this all applies
+to the <code class="docutils literal"><span class="pre">macro</span></code> block as well.</p>
+<p>CMake commands can have named arguments that are requried at every call site. In
+addition, all commands will implicitly accept a variable number of extra
+arguments (In C parlance, all commands are varargs functions). When a command is
+invoked with extra arguments (beyond the named ones) CMake will store the full
+list of arguments (both named and unnamed) in a list named <code class="docutils literal"><span class="pre">ARGV</span></code>, and the
+sublist of unnamed arguments in <code class="docutils literal"><span class="pre">ARGN</span></code>. Below is a trivial example of
+providing a wrapper function for CMake’s built in function <code class="docutils literal"><span class="pre">add_dependencies</span></code>.</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">function</span><span class="p">(</span><span class="s">add_deps</span> <span class="s">target</span><span class="p">)</span>
+  <span class="nb">add_dependencies</span><span class="p">(</span><span class="o">${</span><span class="nv">target</span><span class="o">}</span> <span class="o">${</span><span class="nv">ARGN</span><span class="o">}</span><span class="p">)</span>
+<span class="nb">endfunction</span><span class="p">()</span>
+</pre></div>
+</div>
+<p>This example defines a new macro named <code class="docutils literal"><span class="pre">add_deps</span></code> which takes a required first
+argument, and just calls another function passing through the first argument and
+all trailing arguments.</p>
+<p>CMake provides a module <code class="docutils literal"><span class="pre">CMakeParseArguments</span></code> which provides an implementation
+of advanced argument parsing. We use this all over LLVM, and it is recommended
+for any function that has complex argument-based behaviors or optional
+arguments. CMake’s official documentation for the module is in the
+<code class="docutils literal"><span class="pre">cmake-modules</span></code> manpage, and is also available at the
+<a class="reference external" href="https://cmake.org/cmake/help/v3.4/module/CMakeParseArguments.html">cmake-modules online documentation</a>.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">As of CMake 3.5 the cmake_parse_arguments command has become a native command
+and the CMakeParseArguments module is empty and only left around for
+compatibility.</p>
+</div>
+</div>
+<div class="section" id="functions-vs-macros">
+<h3><a class="toc-backref" href="#id16">Functions Vs Macros</a><a class="headerlink" href="#functions-vs-macros" title="Permalink to this headline">¶</a></h3>
+<p>Functions and Macros look very similar in how they are used, but there is one
+fundamental difference between the two. Functions have their own scope, and
+macros don’t. This means variables set in macros will bleed out into the calling
+scope. That makes macros suitable for defining very small bits of functionality
+only.</p>
+<p>The other difference between CMake functions and macros is how arguments are
+passed. Arguments to macros are not set as variables, instead dereferences to
+the parameters are resolved across the macro before executing it. This can
+result in some unexpected behavior if using unreferenced variables. For example:</p>
+<div class="highlight-cmake"><div class="highlight"><pre><span></span><span class="nb">macro</span><span class="p">(</span><span class="s">print_list</span> <span class="s">my_list</span><span class="p">)</span>
+  <span class="nb">foreach</span><span class="p">(</span><span class="s">var</span> <span class="s">IN</span> <span class="s">LISTS</span> <span class="s">my_list</span><span class="p">)</span>
+    <span class="nb">message</span><span class="p">(</span><span class="s2">"${var}"</span><span class="p">)</span>
+  <span class="nb">endforeach</span><span class="p">()</span>
+<span class="nb">endmacro</span><span class="p">()</span>
+
+<span class="nb">set</span><span class="p">(</span><span class="s">my_list</span> <span class="s">a</span> <span class="s">b</span> <span class="s">c</span> <span class="s">d</span><span class="p">)</span>
+<span class="nb">set</span><span class="p">(</span><span class="s">my_list_of_numbers</span> <span class="s">1</span> <span class="s">2</span> <span class="s">3</span> <span class="s">4</span><span class="p">)</span>
+<span class="nb">print_list</span><span class="p">(</span><span class="s">my_list_of_numbers</span><span class="p">)</span>
+<span class="c"># prints:</span>
+<span class="c"># a</span>
+<span class="c"># b</span>
+<span class="c"># c</span>
+<span class="c"># d</span>
+</pre></div>
+</div>
+<p>Generally speaking this issue is uncommon because it requires using
+non-dereferenced variables with names that overlap in the parent scope, but it
+is important to be aware of because it can lead to subtle bugs.</p>
+</div>
+</div>
+<div class="section" id="llvm-project-wrappers">
+<h2><a class="toc-backref" href="#id17">LLVM Project Wrappers</a><a class="headerlink" href="#llvm-project-wrappers" title="Permalink to this headline">¶</a></h2>
+<p>LLVM projects provide lots of wrappers around critical CMake built-in commands.
+We use these wrappers to provide consistent behaviors across LLVM components
+and to reduce code duplication.</p>
+<p>We generally (but not always) follow the convention that commands prefaced with
+<code class="docutils literal"><span class="pre">llvm_</span></code> are intended to be used only as building blocks for other commands.
+Wrapper commands that are intended for direct use are generally named following
+with the project in the middle of the command name (i.e. <code class="docutils literal"><span class="pre">add_llvm_executable</span></code>
+is the wrapper for <code class="docutils literal"><span class="pre">add_executable</span></code>). The LLVM <code class="docutils literal"><span class="pre">add_*</span></code> wrapper functions are
+all defined in <code class="docutils literal"><span class="pre">AddLLVM.cmake</span></code> which is installed as part of the LLVM
+distribution. It can be included and used by any LLVM sub-project that requires
+LLVM.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">Not all LLVM projects require LLVM for all use cases. For example compiler-rt
+can be built without LLVM, and the compiler-rt sanitizer libraries are used
+with GCC.</p>
+</div>
+</div>
+<div class="section" id="useful-built-in-commands">
+<h2><a class="toc-backref" href="#id18">Useful Built-in Commands</a><a class="headerlink" href="#useful-built-in-commands" title="Permalink to this headline">¶</a></h2>
+<p>CMake has a bunch of useful built-in commands. This document isn’t going to
+go into details about them because The CMake project has excellent
+documentation. To highlight a few useful functions see:</p>
+<ul class="simple">
+<li><a class="reference external" href="https://cmake.org/cmake/help/v3.4/command/add_custom_command.html">add_custom_command</a></li>
+<li><a class="reference external" href="https://cmake.org/cmake/help/v3.4/command/add_custom_target.html">add_custom_target</a></li>
+<li><a class="reference external" href="https://cmake.org/cmake/help/v3.4/command/file.html">file</a></li>
+<li><a class="reference external" href="https://cmake.org/cmake/help/v3.4/command/list.html">list</a></li>
+<li><a class="reference external" href="https://cmake.org/cmake/help/v3.4/command/math.html">math</a></li>
+<li><a class="reference external" href="https://cmake.org/cmake/help/v3.4/command/string.html">string</a></li>
+</ul>
+<p>The full documentation for CMake commands is in the <code class="docutils literal"><span class="pre">cmake-commands</span></code> manpage
+and available on <a class="reference external" href="https://cmake.org/cmake/help/v3.4/manual/cmake-commands.7.html">CMake’s website</a></p>
+</div>
+</div>
+
+
+          </div>
+      </div>
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+    <div class="related" role="navigation" aria-label="related navigation">
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+             >index</a></li>
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