[PATCH] D44234: [AArch64] Fix UB about shift amount exceeds data bit-width

[Weiming Zhao via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL326969: [AArch64] Fix UB about shift amount exceeds data bit-width (authored by weimingz, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D44234?vs=137504&id=137509#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D44234

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp


Index: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1512,7 +1512,7 @@
 
   // Because of simplify-demanded-bits in DAGCombine, the mask may have been
   // simplified. Try to undo that
-  AndImm |= (1 << NumberOfIgnoredLowBits) - 1;
+  AndImm |= maskTrailingOnes<uint64_t>(NumberOfIgnoredLowBits);
 
   // The immediate is a mask of the low bits iff imm & (imm+1) == 0
   if (AndImm & (AndImm + 1))


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