[llvm] r326906 - [PowerPC] LSR tunings for PowerPC

[Stefan Pintilie via llvm-commits]

Author: stefanp
Date: Wed Mar  7 08:53:09 2018
New Revision: 326906

URL: http://llvm.org/viewvc/llvm-project?rev=326906&view=rev
Log:
[PowerPC] LSR tunings for PowerPC

The purpose of this patch is to have LSR generate better code on Power.
This is done by overriding isLSRCostLess.

Differential Revision: https://reviews.llvm.org/D40855

Added:
    llvm/trunk/test/Transforms/LoopStrengthReduce/PowerPC/
    llvm/trunk/test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp?rev=326906&r1=326905&r2=326906&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp Wed Mar  7 08:53:09 2018
@@ -256,6 +256,19 @@ bool PPCTTIImpl::enableInterleavedAccess
   return true;
 }
 
+bool PPCTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                               TargetTransformInfo::LSRCost &C2) {
+  // This is mainly the default cost calculation. The only difference
+  //  is that now the number of instructions is the most important
+  //  metric.
+  return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
+                  C1.NumIVMuls, C1.NumBaseAdds,
+                  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
+         std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
+                  C2.NumIVMuls, C2.NumBaseAdds,
+                  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
+}
+
 unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) {
   if (Vector && !ST->hasAltivec() && !ST->hasQPX())
     return 0;

Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h?rev=326906&r1=326905&r2=326906&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.h Wed Mar  7 08:53:09 2018
@@ -57,6 +57,9 @@ public:
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP);
 
+  bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                     TargetTransformInfo::LSRCost &C2);
+
   /// @}
 
   /// \name Vector TTI Implementations

Added: llvm/trunk/test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll?rev=326906&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll (added)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll Wed Mar  7 08:53:09 2018
@@ -0,0 +1,57 @@
+; RUN: llc < %s -O2 -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
+
+; LLC checks that LSR prefers less instructions to less induction variables
+; Without the PPC specific LSR cost model, extra addition instructions
+; will occur within the loop before the call to _ZN6myTypeC1Ev.
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+%struct.myType2 = type <{ i32, i8, %struct.myType, [2 x i8] }>
+%struct.myType = type { i8 }
+
+define nonnull %struct.myType2* @_Z6myIniti(i64 signext %n) local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+; CHECK-LABEL: _Z6myIniti:
+; CHECK:  [[LABEL1:.LBB[0-9A-Z_]+]]:
+; CHECK:    mr {{[0-9]+}}, [[REG1:[0-9]+]]
+; CHECK-NEXT:    bl _ZN6myTypeC1Ev
+; CHECK:    addi [[REG2:[0-9]+]], [[REG2]], -8
+; CHECK-NEXT:    addi [[REG1]], [[REG1]], 8
+; CHECK-NEXT:    cmpldi [[REG2]], 0
+; CHECK-NEXT:    bne 0, [[LABEL1]]
+
+entry:
+  %call = tail call i8* @_Znam(i64 %n) #5
+  %cast = bitcast i8* %call to %struct.myType2*
+  %arrayctor.end = getelementptr inbounds %struct.myType2, %struct.myType2* %cast, i64 %n
+  br label %arrayctor.loop
+
+arrayctor.loop:                                   ; preds = %invoke.cont, %new.ctorloop
+  %arrayctor.cur = phi %struct.myType2* [ %cast, %entry ], [ %arrayctor.next, %invoke.cont ]
+  %x.i = getelementptr inbounds %struct.myType2, %struct.myType2* %arrayctor.cur, i64 0, i32 2
+  invoke void @_ZN6myTypeC1Ev(%struct.myType* nonnull %x.i)
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %arrayctor.loop
+  %arrayctor.next = getelementptr inbounds %struct.myType2, %struct.myType2* %arrayctor.cur, i64 1
+  %arrayctor.done = icmp eq %struct.myType2* %arrayctor.next, %arrayctor.end
+  br i1 %arrayctor.done, label %arrayctor.cont, label %arrayctor.loop
+
+arrayctor.cont:                                   ; preds = %invoke.cont, %entry
+  ret %struct.myType2* %cast
+
+lpad:                                             ; preds = %arrayctor.loop
+  %landing = landingpad { i8*, i32 }
+          cleanup
+  tail call void @_ZdaPv(i8* nonnull %call) #6
+  resume { i8*, i32 } %landing
+}
+
+declare noalias nonnull i8* @_Znam(i64) local_unnamed_addr #2
+
+declare i32 @__gxx_personality_v0(...)
+
+declare void @_ZdaPv(i8*) local_unnamed_addr #3
+
+declare void @_ZN6myTypeC1Ev(%struct.myType*) unnamed_addr #4
+