[PATCH] D43973: [AArch64] define isExtractSubvectorCheap

[Sebastian Pop via Phabricator via llvm-commits]

sebpop added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/arm64-ext.ll:100
-; Essence: a vext is used on %A and something saner than stack load/store for final result.
-define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: test_interleaved:
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evandro wrote:
> Methinks that this test could stay.  Before, it resulted in a mix of `EXT`, `UZP1`, `ZIP1`.  With this patch, in a pair of `LDR`, `TBL`, which seems to be a good result.  Better yet,  were the shuffle index changed to `<i32 4, i32 8, i32 5, i32 9>`, then the result would be just like in the test below.
If I replace the pattern with <4,8,5,9> that is trivially matched as a ZIP1 pattern before and after the patch.
The testcase was crafted this way to force the compiler to use VEXT instructions instead of loads and stores on the stack.

As I tried to explain the the commit message, this testcase is fragile in the sense that it requires a BUILD_VECTOR to "survive" all DAG transforms until ISelLowering. The testcase is supposed to check that AArch64TargetLowering::ReconstructShuffle() works, and for that we need a BUILD_VECTOR in ISelLowering.  As we now transform the BUILD_VECTOR earlier into an VEXT + vector_shuffle, we don't have the BUILD_VECTOR pattern when we get to ISelLowering.


Repository:
  rL LLVM

https://reviews.llvm.org/D43973