[PATCH] D43982: [GlobalISel][ARM] Adding HRP and QPR regclasses to FPRB regbank

[Roman Tereshin via Phabricator via llvm-commits]

rtereshin created this revision.
rtereshin added reviewers: qcolombet, ab, dsanders, aditya_nandakumar, bogner, volkan, aemerson, t.p.northover, rovka.
Herald added subscribers: kristof.beyls, javed.absar.
rtereshin edited the summary of this revision.

Also bringing ARMRegisterBankInfo::getRegBankFromRegClass implementation up to speed with the *.td-definition.

Also improving greatly the InstructionSelect test coverage.

Requires https://reviews.llvm.org/D43962 and https://reviews.llvm.org/D43979, see the reviews for details.

The tests are re-generated by

  ../../utils/update_instruction_select_testgen_tests.sh ../../test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-testgend.mir ./bin/llc arm-- -testgen-exclude-rules=1010,1011

where the rule numbers of the rules breaking the Testgen found the following way:

  for i in `seq 0 1200`; do
    if ! echo | ./bin/llc -mtriple arm-- -run-pass instruction-select-testgen \
        -run-pass instruction-select -testgen-set-all-features \
        -disable-gisel-legality-check -verify-machineinstrs -simplify-mir \
        -o /dev/null 2> /dev/null -x mir -testgen-include-only=$i; then
      echo $i
    fi
  done


Repository:
  rL LLVM

https://reviews.llvm.org/D43982

Files:
  lib/Target/ARM/ARMInstructionSelector.cpp
  lib/Target/ARM/ARMRegisterBankInfo.cpp
  lib/Target/ARM/ARMRegisterBanks.td
  test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-selected.mir
  test/CodeGen/ARM/GlobalISel/arm-instruction-select-testgen-testgend.mir