[PATCH] D43973: [AArch64] define isExtractSubvectorCheap
Sebastian Pop via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 1 14:30:06 PST 2018
sebpop created this revision.
sebpop added reviewers: efriedma, SjoerdMeijer.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar, rengolin.
Following the ARM-neon backend, define isExtractSubvectorCheap to return true
when extracting low and high part of a neon register.
The patch disables a test in llvm/test/CodeGen/AArch64/arm64-ext.ll that was
checking that ReconstructShuffle in ISelLowering is working as expected. The
pattern to exercise ReconstructShuffle is a BUILD_VECTOR and the expected
pattern gets transformed earlier by the DAGCombiner into an extract_subvector +
vector_shuffle. As there is no way to disable the combiner to only exercise the
code in ISelLowering, the patch disables the testcase.
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