[llvm] r326466 - AMDGPU/GlobalISel: Make i32 xor legal

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Thu Mar  1 11:09:21 2018
New Revision: 326466

URL: http://llvm.org/viewvc/llvm-project?rev=326466&view=rev
Log:
AMDGPU/GlobalISel: Make i32 xor legal

Added:
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=326466&r1=326465&r2=326466&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Thu Mar  1 11:09:21 2018
@@ -35,6 +35,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
 
   setAction({G_ADD, S32}, Legal);
   setAction({G_AND, S32}, Legal);
+  setAction({G_OR, S32}, Legal);
+  setAction({G_XOR, S32}, Legal);
 
   setAction({G_BITCAST, V2S16}, Legal);
   setAction({G_BITCAST, 1, S32}, Legal);
@@ -79,8 +81,6 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
   setAction({G_LOAD, 1, P1}, Legal);
   setAction({G_LOAD, 1, P2}, Legal);
 
-  setAction({G_OR, S32}, Legal);
-
   setAction({G_SELECT, S32}, Legal);
   setAction({G_SELECT, 1, S1}, Legal);
 

Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir?rev=326466&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir Thu Mar  1 11:09:21 2018
@@ -0,0 +1,18 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+---
+name: test_xor
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: test_xor
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(s32) = G_XOR %0, %1
+    $vgpr0 = COPY %2
+...