[PATCH] D24521: [ARM] Add Marvell PJ4 cpu

[Kai Nacke via Phabricator via llvm-commits]

Kai updated this revision to Diff 136464.
Kai added a comment.

Hi Renato,
I updated the patch according to your comments.

A current gcc provides only a -mcpu=marvell-pj4 switch. There is no differentiation between the PJ4 and the PJ4C. gcc defines the cpu as plain armv7-a with no special instructions enabled, but defines a special cost model. (See https://github.com/gcc-mirror/gcc/blob/master/gcc/config/arm/arm-cpus.in#L1377 and https://github.com/gcc-mirror/gcc/blob/master/gcc/config/arm/arm-cpus.in#L467.)

The only drawback I currently see is that the cpu is detected but cannot specified on the command line with -mcpu=marvell-pj4. This feels a bit weird. Does the gcc cost model provide enough information to translate this to LLVM?


https://reviews.llvm.org/D24521

Files:
  include/llvm/Support/ARMTargetParser.def
  lib/Support/Host.cpp
  unittests/Support/Host.cpp
  unittests/Support/TargetParserTest.cpp


Index: unittests/Support/TargetParserTest.cpp
===================================================================
--- unittests/Support/TargetParserTest.cpp
+++ unittests/Support/TargetParserTest.cpp
@@ -277,9 +277,12 @@
   EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
                          ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
                          "7-S"));
+  EXPECT_TRUE(testARMCPU("marvell-pj4", "armv7-a", "vfpv3",
+                         ARM::AEK_DSP | ARM::AEK_IWMMXT2 | ARM::AEK_HWDIVTHUMB,
+                         "7-A"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 82;
+static constexpr unsigned NumARMCPUArchs = 83;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector<StringRef, NumARMCPUArchs> List;
Index: unittests/Support/Host.cpp
===================================================================
--- unittests/Support/Host.cpp
+++ unittests/Support/Host.cpp
@@ -92,6 +92,12 @@
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
                                               "CPU part        : 0x06f"),
             "krait");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x56\n"
+                                              "CPU part        : 0x581"),
+            "marvell-pj4");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x56\n"
+                                              "CPU part        : 0x584"),
+            "marvell-pj4");
 }
 
 TEST(getLinuxHostCPUName, AArch64) {
Index: lib/Support/Host.cpp
===================================================================
--- lib/Support/Host.cpp
+++ lib/Support/Host.cpp
@@ -247,6 +247,19 @@
     }
   }
 
+  if (Implementer == "0x56") { // Marvell Technology Group Ltd.
+    // Look for the CPU part line.
+    for (unsigned I = 0, E = Lines.size(); I != E; ++I)
+      if (Lines[I].startswith("CPU part"))
+        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
+        // values correspond to the "Part number" in the CP15/c0 register. The
+        // contents are specified in the various processor manuals.
+        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
+            .Case("0x581", "marvell-pj4") // Sheeva PJ4 / PJ4B
+            .Case("0x584", "marvell-pj4") // Sheeva PJ4B-MP / PJ4C
+            .Default("generic");
+  }
+
   return "generic";
 }
 
Index: include/llvm/Support/ARMTargetParser.def
===================================================================
--- include/llvm/Support/ARMTargetParser.def
+++ include/llvm/Support/ARMTargetParser.def
@@ -259,6 +259,8 @@
 ARM_CPU_NAME("xscale", XSCALE, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("swift", ARMV7S, FK_NEON_VFPV4, true,
              (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
+ARM_CPU_NAME("marvell-pj4", ARMV7A, FK_VFPV3, false,
+             (ARM::AEK_DSP | ARM::AEK_HWDIVTHUMB | ARM::AEK_IWMMXT2))
 // Invalid CPU
 ARM_CPU_NAME("invalid", INVALID, FK_INVALID, true, ARM::AEK_INVALID)
 #undef ARM_CPU_NAME


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